Semiconductor device and formation method thereof

Abstract

A semiconductor device and a formation method thereof are provided. The semiconductor device includes a substrate, a first buried layer, a second buried layer, a first high-voltage well region, a second high-voltage well region, a third high-voltage well region, and a gate stack. The substrate has a first conductivity type. The first buried layer has a second conductivity type different from the first conductivity type and is disposed in the substrate. The second buried layer has the first conductivity type and is disposed in the first buried layer. The first high-voltage well region has a second conductivity type and is disposed on the second buried layer. The second high-voltage well region has the first conductivity type and is disposed on the second buried layer and the first buried layer. The third high-voltage well region has the second conductivity type and is disposed on the first buried layer. The gate stack is disposed on the first high-voltage well region.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method of forming the same, and particularly to a semiconductor device including a first buried layer and a second buried layer and a method of forming the same. Prior Technology

[0002] Laterally diffused metal oxide semiconductor (LDMOS) field-effect transistors are frequently used in power devices, such as switching regulators. Because LDMOS has a horizontal structure, the primary current flow is horizontal.

[0003] However, current LDMOS devices are primarily driven by positive voltage and cannot be driven by negative voltage. Therefore, although existing semiconductor devices and their fabrication methods have gradually met their intended applications, they still do not completely satisfy requirements in all aspects. Thus, there are still some problems to be overcome regarding semiconductor devices and their fabrication methods. Summary of the Invention

[0004] The semiconductor device and its formation method disclosed herein may include a first buried layer, a second buried layer, a second high-voltage well region, and a third high-voltage well region, serving as an isolation structure between the laterally diffused metal-oxide-semiconductor (LDMOS) and the substrate. Therefore, by providing this isolation structure, the LDMOS can be driven under negative voltage. Accordingly, the semiconductor device disclosed herein can improve reliability and / or applicability.

[0005] In some embodiments, this disclosure provides a semiconductor device. The semiconductor device includes a substrate, a first buried layer, a second buried layer, a first high-voltage well region, a second high-voltage well region, a third high-voltage well region, and a gate stack. The substrate has a first conductivity type. The first buried layer has a second conductivity type different from the first conductivity type and is disposed in the substrate. The second buried layer has the first conductivity type and is disposed in the first buried layer. The first high-voltage well region has the second conductivity type and is disposed on the second buried layer. The second high-voltage well region has the first conductivity type and is disposed on both the second buried layer and the first buried layer. The third high-voltage well region has the second conductivity type and is disposed on the first buried layer. The gate stack is disposed on the first high-voltage well region.

[0006] In some embodiments, this disclosure provides a method for forming a semiconductor device. The method includes providing a substrate having a first conductivity type; forming a first buried layer in the substrate having a second conductivity type different from the first conductivity type; forming a second buried layer in the first buried layer having the first conductivity type; forming an epitaxial layer on the substrate, the first buried layer, and the second buried layer; forming a first high-voltage well region in the epitaxial layer and on the second buried layer, having the second conductivity type; forming a second high-voltage well region in the epitaxial layer and on the second buried layer and the first buried layer, having the first conductivity type; forming a third high-voltage well region in the epitaxial layer and on the first buried layer, having the second conductivity type; and forming a gate stack on the first high-voltage well region.

[0007] The semiconductor device and its fabrication method disclosed herein can be applied to various types of electronic devices. To make the components and advantages of this disclosure more apparent and understandable, various embodiments are described below in detail with reference to the accompanying drawings. Simple Explanation of the Diagram

[0008] This disclosure will be more fully understood when read in conjunction with the drawings, from the following detailed description. It is worth noting that, in accordance with industry standard practice, the components are not drawn to scale. In fact, for clarity, the dimensions of the components may be arbitrarily enlarged or reduced. Figures 1 to 3 are schematic cross-sectional views of each stage of a method for forming a semiconductor device according to an embodiment of the present disclosure. Figures 4 and 5 are schematic cross-sectional views of each stage of a method for forming a semiconductor device according to an embodiment of the present disclosure. Implementation

[0009] The semiconductor devices of various embodiments of this disclosure are described in detail below. It should be understood that the following description provides many different embodiments for implementing various forms of some embodiments of this disclosure. The specific elements and arrangements described below are merely for simple and clear description of some embodiments of this disclosure. Of course, these are only examples and not limitations of this disclosure. Furthermore, similar and / or corresponding element symbols may be used in different embodiments to identify similar and / or corresponding elements for clear description of this disclosure. However, the use of these similar and / or corresponding element symbols is only for simple and clear description of some embodiments of this disclosure and does not represent any relationship between the different embodiments and / or structures discussed.

[0010] It should be understood that relative terms, such as "lower," "bottom," "higher," or "top," may be used in various embodiments to describe the relative relationship of one element to another in the diagram. It is understood that if the arrangement in the diagram is flipped so that it is upside down, an element depicted on the "lower" side will become an element on the "higher" side. The embodiments disclosed herein should be understood in conjunction with the drawings, which are also considered part of the disclosure.

[0011] Furthermore, when it is stated that a first material layer is on or over a second material layer, this may include situations where the first and second material layers are in direct contact, or situations where the first and second material layers are not in direct contact, meaning that there may be one or more other material layers between the first and second material layers. However, if the first material layer is directly on the second material layer, it indicates that the first and second material layers are in direct contact.

[0012] Furthermore, it should be understood that the ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify elements, are not intended to imply any prior ordinal number for that (or those) element, nor to indicate the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another with the same name. The claims and specification may not use the same terminology; for example, the first element in the specification may be the second element in the claims.

[0013] In some embodiments disclosed herein, terms such as "connect," "interconnect," and "bond," unless specifically defined, may refer to two structures being in direct contact, or to two structures not being in direct contact, with other structures disposed between them. Furthermore, these terms may include situations where both structures are movable or both are fixed. Additionally, the terms "electrical connection" or "electrical coupling" include any direct or indirect electrical connection means.

[0014] In this text, the terms "approximately," "about," and "substantially" typically indicate that a given value or range is within 10%, 5%, 3%, 2%, 1%, or 0.5%. The given quantity is an approximate quantity; that is, even without specific mention of "approximately," "about," or "substantially," the meaning of "approximately," "about," or "substantially" is implied. The phrases "the range is between the first value and the second value" or "the first value ~ the second value" indicate that the range includes the first value, the second value, and other values ​​in between. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies that there may be an error between the first and second values ​​within approximately 10%, 5%, 3%, 2%, 1%, or 0.5%.

[0015] Throughout this disclosure and in the claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same elements. This document is not intended to distinguish between elements that function identically but have different names. In the following description and claims, words such as "comprise" and "having" are open-ended terms and should therefore be interpreted as "including but not limited to...". Thus, when the terms "comprise" and / or "having" are used in the description of this disclosure, they specify the presence of corresponding components, areas, steps, operations, and / or elements, but do not exclude the presence of one or more corresponding components, areas, steps, operations, and / or elements.

[0016] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It is understood that these terms, for example, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0017] In this disclosure, the directions are not limited to the three axes of a Cartesian coordinate system such as the X, Y, and Z axes, and can be interpreted in a broader sense. For example, the X, Y, and Z axes may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For ease of explanation, in the following text, the X-axis direction is the first direction D1 (width direction), the Y-axis direction is the second direction D2 (length direction), and the Z-axis direction is the third direction D3 (thickness / height direction). In some embodiments, the cross-sectional schematic diagram described herein is a schematic diagram for viewing the XY plane. In some embodiments, the normal direction of the substrate described herein is the third direction D3.

[0018] Referring to Figure 1, which is a schematic cross-sectional view of a stage of a method for forming a semiconductor device 1 according to an embodiment of the present disclosure. In some embodiments, a substrate 100 may be provided, and the substrate 100 may have a first conductivity type. In some embodiments, the substrate 100 may include a wafer, such as a silicon wafer. In some embodiments, the substrate 100 may include a bulk semiconductor or a semiconductor-on-insulator (SOI) substrate. Generally, an SOI substrate may include a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like, to provide an insulating layer on a silicon or glass substrate. In some embodiments, the substrate may include a multilayer substrate or a gradient substrate. In some embodiments, substrate 100 may include elemental semiconductors, including silicon, germanium, the like, or combinations thereof; substrate 100 may include compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, the like, or combinations thereof; substrate 100 may include alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, the like, or combinations thereof, but this disclosure is not limited thereto.

[0019] As shown in Figure 1, in some embodiments, a first buried layer 110 may be formed in the substrate 100, and the first buried layer 110 may have a second conductivity type different from the first conductivity type. In some embodiments, a second buried layer 120 may be formed in the first buried layer 110, and the second buried layer 120 may have the first conductivity type. In some embodiments, the first buried layer 110 and the second buried layer 120 may be formed by a doping process such as ion implantation, diffusion, drive-in, similar processes, or combinations thereof, but this disclosure is not limited thereto. In addition, the implanted dopant may be further activated by a rapid thermal annealing (RTA) process.

[0020] As shown in Figure 1, in some embodiments, the width w110 of the first buried layer 110 may be greater than the width w120 of the second buried layer 120 in the first direction D1. In some embodiments, the first buried layer 110 may surround at least three sides of the second buried layer 120. In some embodiments, the first buried layer 110 may contact the side surfaces and bottom surfaces of the second buried layer 120. In some embodiments, the projection range of the second buried layer 120 onto the substrate 100 may be within the projection range of the first buried layer 110 onto the substrate 100. In some embodiments, the second buried layer 120 may be physically separated from the substrate 100 by means of the first buried layer 110. In some embodiments, the second buried layer 120 may cover a portion of the top surface of the first buried layer 110, and the second buried layer 120 may expose the remaining portion of the top surface of the first buried layer 110.

[0021] As shown in Figure 1, in some embodiments, the thickness t110 of the first embedded layer 110 on the third-direction D3 may be greater than the thickness t120 of the second embedded layer 120. In some embodiments, the thickness t110 of the first embedded layer 110 may be greater than or equal to 3 μm and less than or equal to 24 μm. For example, the thickness t110 may be 3 μm, 6 μm, 9 μm, 12 μm, 15 μm, 18 μm, 21 μm, 24 μm, or any value or range of values ​​between the aforementioned values, but this disclosure is not limited thereto. In some embodiments, the thickness t120 of the second embedded layer 120 may be greater than or equal to 2 μm and less than or equal to 7 μm. For example, the thickness t120 may be 2 μm, 3 μm, 4 μm, 5 μm, 5.5 μm, 6 μm, 7 μm, or any value or range of values ​​between the aforementioned values, but this disclosure is not limited thereto.

[0022] In some embodiments, a thermal drive-in process can be performed to form the first embedded layer 110 and the second embedded layer 120. In some embodiments, the execution time of the thermal drive-in process can be 450 minutes to 600 minutes. For example, the execution time can be 450 minutes, 475 minutes, 500 minutes, 540 minutes, 580 minutes, 600 minutes, or any value or range of values ​​between the foregoing values, but this disclosure is not limited thereto. In some embodiments, the execution temperature of the thermal drive-in process can be 1000 °C to 1400 °C. For example, the execution temperature can be 1000 °C, 1050 °C, 1100 °C, 1150 °C, 1200 °C, 1250 °C, 1300 °C, 1350 °C, 1400 °C, or any value or range of values ​​between the foregoing values, but this disclosure is not limited thereto. In some embodiments, the thermal drive-in process can be performed two or more times. For example, the hot-drive process can be repeated twice, with each hot-drive process lasting 500 to 580 minutes and at a temperature of 1150 °C to 1250 °C. In other embodiments, the hot-drive process can be performed once, with a duration of 1000 to 1160 minutes and at a temperature of 1150 °C to 1250 °C.

[0023] In some embodiments, the N-type doping concentration of the first buried layer 110 may be 1E12 / cm³ to 5E12 / cm³. For example, the N-type doping concentration of the first buried layer 110 may be 1E12 / cm³, 2E12 / cm³, 3E12 / cm³, 3.5E12 / cm³, 4E12 / cm³, 5E12 / cm³, or any value or range of values ​​between the aforementioned values, but this disclosure is not limited thereto. In some embodiments, the P-type doping concentration of the second buried layer 120 may be 3E12 / cm³ to 8E12 / cm³. For example, the P-type doping concentration of the second buried layer 120 may be 3E12 / cm3, 4E12 / cm3, 5E12 / cm3, 6E12 / cm3, 7E12 / cm3, 8E12 / cm3 or any value between the aforementioned values ​​or any range of values, but this disclosure is not limited thereto.

[0024] As shown in Figure 1, in some embodiments, the first conductivity type and the second conductivity type can be adjusted according to electrical requirements. In some embodiments, the doping concentration, doping depth, and size of the doped region can also be adjusted according to electrical requirements. In some embodiments, the first conductivity type can be either P-type or N-type, and the second conductivity type can be either P-type or N-type. For ease of explanation, in the following description, the first conductivity type can be P-type, and the second conductivity type can be N-type, but this disclosure is not limited thereto. In other words, the substrate 100 and the second buried layer 120 can be P-type, and the first buried layer 110 can be N-type. Therefore, in the following description, a semiconductor device including an N-type LDMOS is used.

[0025] Referring to Figure 2, which is a cross-sectional schematic diagram of a stage of a method for forming a semiconductor device 1 according to an embodiment of the present disclosure. In some embodiments, an epitaxial layer 200 may be formed on a substrate 100, a first buried layer 110, and a second buried layer 120. In other words, after the first buried layer 110 and the second buried layer 120 are formed on the substrate 100, the epitaxial layer 200 is formed on the substrate 100. In some embodiments, the epitaxial layer 200 may have a first conductivity type, namely P-type. In some embodiments, the epitaxial layer 200 may be formed by processes such as metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), similar processes, or combinations thereof, but the present disclosure is not limited thereto.

[0026] As shown in Figure 2, in some embodiments, a first high-pressure well region 210 may be formed in the epitaxial layer 200 and on the second buried layer 120. In some embodiments, the first high-pressure well region 210 may have a second conductivity type, i.e., N-type. In some embodiments, a second high-pressure well region 220 may be formed in the epitaxial layer 200 and on the second buried layer 120 and the first buried layer 110. In some embodiments, the second high-pressure well region 220 may have a first conductivity type, i.e., P-type. In some embodiments, a third high-pressure well region 230 may be formed in the epitaxial layer 200 and on the first buried layer 110. In some embodiments, the third high-pressure well region 230 may have a second conductivity type, i.e., N-type. In some embodiments, the first high-pressure well region 210, the second high-pressure well region 220, and / or the third high-pressure well region 230 may be formed by doping processes such as ion implantation processes, diffusion processes, thermal drive-in processes, similar processes, or combinations thereof, but this disclosure is not limited thereto. Furthermore, the implanted dopants can be further activated by a rapid thermal annealing process. In some embodiments, the first high-pressure well region 210 and the third high-pressure well region 230 can be formed in the same process or in different processes.

[0027] As shown in Figure 2, in some embodiments, the first high-pressure well region 210, the second high-pressure well region 220, and the third high-pressure well region 230 may each penetrate the epitaxial layer 200. In some embodiments, the bottom surfaces of the first high-pressure well region 210, the second high-pressure well region 220, and the third high-pressure well region 230 may be flush with the bottom surface of the epitaxial layer 200. In some embodiments, the second high-pressure well region 220 may surround the first high-pressure well region 210. In some embodiments, the third high-pressure well region 230 may surround the second high-pressure well region 220.

[0028] As shown in Figure 2, in some embodiments, the first high-pressure well region 210 may be disposed on and in contact with the second buried layer 120. In some embodiments, the first high-pressure well region 210 may be spaced apart from the first buried layer 110 by a distance. In some embodiments, the projection range of the first high-pressure well region 210 onto the substrate 100 is located within the projection range of the second buried layer 120 onto the substrate 100.

[0029] As shown in Figure 2, in some embodiments, the second high-pressure well region 220 may be disposed on and in contact with the second buried layer 120 and the first buried layer 110. In some embodiments, the projection range of the second high-pressure well region 220 onto the substrate 100 overlaps with both the projection range of the second buried layer 120 onto the substrate 100 and the projection range of the first buried layer 110 onto the substrate 100. In some embodiments, the second buried layer 120 may contact the first high-pressure well region 210 and the second high-pressure well region 220.

[0030] As shown in Figure 2, in some embodiments, the third high-pressure well region 230 may be disposed on and in contact with the first buried layer 110. In some embodiments, the third high-pressure well region 230 may be spaced apart from the second buried layer 120 by a distance. In some embodiments, the projection range of the third high-pressure well region 230 onto the substrate 100 is located within the projection range of the first buried layer 110 onto the substrate 100. In some embodiments, the first buried layer 110 may contact the second high-pressure well region 220 and the third high-pressure well region 230.

[0031] As shown in Figure 2, in some embodiments, a source region 310 and a drain region 320 may be formed in a first high-pressure well region 210. In some embodiments, the source region 310 may have a first conductivity type, i.e., P-type. In some embodiments, the drain region 320 may have a second conductivity type, i.e., N-type. In some embodiments, in a first direction D1, the source region 310 may be located between adjacent drain regions 320.

[0032] Referring to Figure 3, which is a schematic cross-sectional view of a stage of a method for forming a semiconductor device 1 according to an embodiment of the present disclosure. As shown in Figure 3, in some embodiments, an isolation layer 400 may be formed on the epitaxial layer 200 to define the active region of the subsequently formed semiconductor device. In some embodiments, the isolation layer 400 may include oxides such as silicon oxide, nitrides such as silicon nitride, oxynitrides such as silicon oxynitride, the like, or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the isolation layer 400 may include a field oxide.

[0033] As shown in Figure 3, in some embodiments, a gate stack 500 may be formed on the first high-voltage well region 210. In some embodiments, the gate stack 500 may include a gate dielectric layer 510, a gate electrode 520, and a gate spacer 530. In some embodiments, the gate dielectric layer 510 may be disposed on the first high-voltage well region 210, the gate electrode 520 may be disposed on the isolation layer 400 and the gate dielectric layer 510, and the gate spacer 530 may be disposed on the opposite side surface of the gate electrode 520. In some embodiments, the gate dielectric layer 510 may include a dielectric material with a high dielectric constant. In some embodiments, the gate dielectric layer 510 may include an oxide such as silicon oxide. In some embodiments, the gate electrode 520 may include polycrystalline silicon, amorphous silicon, metals such as silver (Ag), gold (Au), aluminum (Al), manganese (Mn), copper (Cu), tungsten (W), titanium (Ti), molybdenum (Mo), conductive metal nitrides, conductive metal oxides, the like, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the gate spacer 530 may be a single-layer or multi-layer structure. In some embodiments, the gate spacer 530 may include oxides such as silicon oxide, nitrides such as silicon nitride, oxynitrides such as silicon oxynitride, the like, or combinations thereof, but this disclosure is not limited thereto.

[0034] As shown in Figure 3, in some embodiments, a first doped region 610 may be formed in the source region 310, the drain region 320, and the third high-voltage well region 230. In some embodiments, the first doped region 610 may have a second conductivity type, i.e., N-type. In some embodiments, the N-type doping concentration of the first doped region 610 is greater than the N-type doping concentration of the drain region 320. In some embodiments, a second doped region 620 may be formed in the second high-voltage well region 220 and the epitaxial layer 200. In some embodiments, the second doped region 620 may have a first conductivity type, i.e., P-type. In some embodiments, the P-type doping concentration of the second doped region 620 is greater than the P-type doping concentration of the second high-voltage well region 220. Therefore, a semiconductor device 1 can be obtained.

[0035] As shown in Figure 3, in some embodiments, the gate electrode 520 can be electrically connected to the gate terminal G, the first doped region 610 located in the source region 310 can be electrically connected to the source terminal S, and the first doped region 610 located in the drain region 320 can be electrically connected to the drain terminal D. In some embodiments, the second doped region 620 located in the second high-voltage well region 220 can be electrically connected to the first isolation terminal ISO-1, the first doped region 610 located in the third high-voltage well region 230 can be electrically connected to the second isolation terminal ISO-2, and the second doped region 620 located in the epitaxial layer 200 can be electrically connected to the substrate terminal SUB.

[0036] As shown in Figure 3, in some embodiments, the elements located in the first high-pressure well region 210, such as the gate stack 500, the source region 310, and the drain region 320, can collectively serve as an N-type LDMOS. Since the N-type LDMOS is isolated by both the P-type and N-type isolation portions, it can be a fully isolated N-type LDMOS.

[0037] As shown in Figure 3, in some embodiments, the first high-pressure well zone 210 can be physically separated from the third high-pressure well zone 230 and the first buried layer 110 by the interconnected second high-pressure well zone 220 and the second buried layer 120. Therefore, the second high-pressure well zone 220 and the second buried layer 120 can together serve as a P-type isolation portion and are connected to the first isolation terminal ISO-1. For example, the P-type isolation portion can enhance the breakdown voltage of NN between the N-type first high-pressure well zone 210 and the N-type third high-pressure well zone 230.

[0038] As shown in Figure 3, in some embodiments, the second high-voltage well region 220 and the second buried layer 120 can be physically separated from the epitaxial layer 200 and the substrate 100 by the interconnected third high-voltage well region 230 and the first buried layer 110. Therefore, the third high-voltage well region 230 and the first buried layer 110 can together serve as an N-type isolation portion and are connected to the second isolation terminal ISO-2. For example, the N-type isolation portion can enhance the breakdown voltage of the P-type layer (PP) between the P-type second high-voltage well region 220 and the P-type epitaxial layer 200.

[0039] As shown in Figure 3, in some embodiments, the P-type isolation portion can directly contact the N-type LDMOS, and the P-type isolation portion can surround the N-type LDMOS. In some embodiments, the N-type isolation portion can directly contact the P-type isolation portion, and the N-type isolation portion can surround the P-type isolation portion. Accordingly, this disclosure may include an isolation structure, and the isolation structure may include P-type isolation portions and N-type isolation portions with different conductivity types.

[0040] In detail, when an LDMOS is directly mounted on and in direct contact with the substrate, applying a negative voltage to the LDMOS will cause a forward bias between the LDMOS drain and the substrate (e.g., between the drain terminal D and the substrate terminal SUB), rendering the LDMOS inoperable. Therefore, LDMOS is typically limited to circuit designs where the operating voltage can only be positive, thus reducing its widespread application. In contrast, this disclosure avoids forward bias between the drain terminal D and the substrate terminal SUB by setting an isolation structure between the LDMOS and the substrate, specifically between the drain terminal D and the substrate terminal SUB, using a first isolation terminal ISO-1 and a second isolation terminal ISO-2.

[0041] In some embodiments (not shown), in a top view, the second high-pressure well zone 220 may have an annular shape to surround the first high-pressure well zone 210. In this embodiment, the boundary of the second buried layer 120 may lie between the inner and outer boundaries of the second high-pressure well zone 220. In some embodiments (not shown), in a top view, the third high-pressure well zone 230 may have an annular shape to surround the second high-pressure well zone 220. For example, the annular shape may be a frame shape, a racetrack shape, or other suitable closed annular shape. In this embodiment, the boundary of the first buried layer 110 may be flush with the outer boundary of the third high-pressure well zone 230.

[0042] In the following text, identical or similar component symbols or descriptions are omitted.

[0043] Referring to Figure 4, which is a cross-sectional schematic diagram of a stage of a method for forming a semiconductor device 2 according to an embodiment of the present disclosure. As shown in Figure 4, in some embodiments, a first high-voltage well region 210 may surround a portion 200P of the epitaxial layer 200. In some embodiments, the shape of the first high-voltage well region 210 may be changed by adjusting the mask used to form the first high-voltage well region 210. In some embodiments, a second high-voltage well region 220 may surround the first high-voltage well region 210. In some embodiments, a third high-voltage well region 230 may surround the second high-voltage well region 220. In some embodiments, the remaining portion of the epitaxial layer 200 may surround the third high-voltage well region 230.

[0044] Referring to Figure 5, which is a cross-sectional schematic diagram of a stage of a method for forming a semiconductor device 2 according to an embodiment of the present disclosure. Figure 5 shows a cross-sectional schematic diagram based on Figure 4 and continuing the formation process shown in Figure 3. Thus, the semiconductor device 2 can be obtained. As shown in Figure 5, in some embodiments, the source region 310 may contact the first high-voltage well region 210 and a portion 200P of the epitaxial layer 200. Accordingly, while maintaining the doping concentration of the first high-voltage well region 210, the N-type doping amount can be reduced by decreasing the area of ​​the first high-voltage well region 210, thereby increasing the breakdown voltage of the semiconductor device 2. In some embodiments, the N-type doping concentration of the first high-voltage well region 210 shown in Figure 5 may be greater than the N-type doping concentration of the first high-voltage well region 210 shown in Figure 3, thereby increasing the N-type doping amount and reducing the on-resistance of the semiconductor device 2.

[0045] Therefore, the semiconductor device and its formation method disclosed herein may include an isolation structure, and the isolation structure may include two isolation portions with different conductivity types to improve the isolation characteristics between the LDMOS and the substrate. For example, the first buried layer and the third high-voltage well region may serve as N-type isolation portions, and the second buried layer and the second high-voltage well region may serve as P-type isolation portions. Thus, by providing an isolation structure, this disclosure enables the LDMOS to be driven under negative voltage, thereby improving reliability and / or versatility of applications.

[0046] It should be understood that, without departing from the spirit of this disclosure, components in multiple different embodiments can be replaced, reorganized, and combined to complete other embodiments. Components in each embodiment can be arbitrarily combined and used as long as they do not violate the spirit of the invention or conflict with it. The scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material composition, apparatus, methods, and steps in the specific embodiments described in the specification. Anyone skilled in the art can understand from the content of this disclosure the current or future development of processes, machines, manufacturing, material composition, apparatus, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same result in the embodiments described herein, and can be used according to this disclosure. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing, material composition, apparatus, methods, and steps. No embodiment or claim of this disclosure needs to achieve all the purposes, advantages, and / or features described in this disclosure.

[0047] The above outlines several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments disclosed herein. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments disclosed herein to achieve the same purpose and / or advantages as the embodiments herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of this disclosure.

[0048] 1, 2: Semiconductor devices 100:Substrate 110: First Burial Layer 120: Second Embedded Layer 200: Epitaxial layer 200P: Partial 210: First High-Pressure Well Area 220: Second High-Pressure Well Area 230: Third High-Pressure Well Area 310: Source Region 320: Dublin Zone 400: Isolation layer 500: Gate stack 510: Gate dielectric layer 520: Gate electrode 530: Gate spacer 610: First doped region 620: Second doped region D: Extreme D1: First Direction D2: Second Direction D3: Third direction G: Gate extreme ISO-1: First isolation terminal ISO-2: Second isolation terminal S: Source Extreme SUB:Substrate side t110, t120: Thickness w110, w120: Width

Claims

1. A semiconductor device, comprising: A substrate having a first conductivity type; A first buried layer having a second conductivity type different from the first conductivity type is disposed in the substrate; A second embedded layer having the first conductive type and disposed within the first embedded layer; a first high-pressure well zone having the second conductive type and disposed on the second embedded layer; a second high-pressure well zone having the first conductive type and disposed on both the second embedded layer and the first embedded layer; a third high-pressure well zone having the second conductive type and disposed on the first embedded layer; and a gate stack disposed on the first high-pressure well zone, wherein the first embedded layer covers a portion of a bottom surface of the second high-pressure well zone, and the second embedded layer covers the remaining portion of the bottom surface of the second high-pressure well zone.

2. The semiconductor device of claim 1, wherein the second high-pressure well region surrounds the first high-pressure well region, and the second high-pressure well region and the first high-pressure well region are in contact with the second buried layer.

3. The semiconductor device as claimed in claim 1, wherein the first buried layer surrounds at least three sides of the second buried layer.

4. The semiconductor device as claimed in claim 1, wherein the third high-pressure well zone is spaced apart from the second buried layer by a distance.

5. The semiconductor device of claim 1, wherein the first high-pressure well region is separated from the third high-pressure well region and the first buried layer by the second high-pressure well region and the second buried layer.

6. The semiconductor device as claimed in claim 1, further comprising: An epitaxial layer is disposed on the substrate, and the first high-pressure well region, the second high-pressure well region and the third high-pressure well region are disposed in the epitaxial layer, wherein the second high-pressure well region and the second buried layer are separated from the epitaxial layer and the substrate through the third high-pressure well region and the first buried layer.

7. The semiconductor device as claimed in claim 6, wherein the first high-pressure well region surrounds the epitaxial layer.

8. The semiconductor device as claimed in claim 6, further comprising: A source electrode region, having the first conductivity type, is disposed in the first high-pressure well region; And a drain electrode region having the second conductivity type is disposed in the first high-pressure well region.

9. The semiconductor device as claimed in claim 8, wherein the source region is in contact with the epitaxial layer.

10. A method for forming a semiconductor device, comprising: A substrate is provided, and the substrate has a first conductivity type; A first buried layer is formed in the substrate, and the first buried layer has a second conductivity type different from the first conductivity type; a second buried layer is formed in the first buried layer, and the second buried layer has the first conductivity type; an epitaxial layer is formed on the substrate, the first buried layer, and the second buried layer; a first high-voltage well region is formed in the epitaxial layer and on the second buried layer, and the first high-voltage well region has the second conductivity type; a second high-voltage well region is formed in the epitaxial layer and on the second buried layer and the first buried layer, and the second high-voltage well region has the first conductivity type; a third high-voltage well region is formed in the epitaxial layer and on the first buried layer, and the third high-voltage well region has the second conductivity type; and a gate stack is formed on the first high-voltage well region, wherein the first buried layer covers a portion of a bottom surface of the second high-voltage well region, and the second buried layer covers the remaining portion of the bottom surface of the second high-voltage well region.

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