Epi cut and s / d dielectric wall for n-p scaling and effective capacitance reduction

Abstract

The present disclosure provides a method for forming source / drain (S / D) epitaxial regions over gate structures such that the S / D epitaxial regions merge, depositing a hardmask layer over the S / D epitaxial regions, etching the hardmask layer to create openings that laterally trim the S / D epitaxial regions, and depositing a dielectric material over the trimmed S / D epitaxial regions. The dielectric material may be a contact etch stop layer (CESL) that completely encapsulates the trimmed S / D epitaxial regions and that physically separates the trimmed S / D epitaxial regions from each other. The CESL may also assume a shape of the trimmed S / D epitaxial regions.

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