Dummy cell designs for nanosheet devices

Abstract

Various integrated circuit transistor device structures that implement nanosheet fin transistors are disclosed. Layouts for the transistor device structures include active cells with dummy cells positioned between active cells. The active cells and dummy cells may include nanosheet fin regions that have different widths. In certain instances, the transitions between different nanosheet fin regions widths (e.g., jogs in the widths) are positioned inside the dummy cells rather than at interfaces between the dummy cells and the active cells. Placing the jogs in widths inside the dummy cells reduces mechanical stresses between active cells and dummy cells and allows for design changes in the size of active transistors during a manufacturing process.

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