Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate, a first well, two first source / drain regions, a first gate dielectric layer and a first gate. The first well is disposed in the substrate. The two first source / drain regions are disposed in the first well and are separated from each other. The first gate dielectric layer is disposed on the substrate. The first gate dielectric layer is a multi-layered structure. The first gate is disposed on the first gate dielectric layer. At least a portion of the first gate dielectric layer covers the two source / drain regions.

Description

Technical Field

[0001] This invention relates to semiconductor devices and methods of manufacturing the same, and particularly to memory devices and methods of manufacturing the same. Prior Technology

[0002] In recent years, the market demand for semiconductor devices has been increasing, with memory devices being a particularly significant component. Generally speaking, the endurance of memory devices is a crucial consideration. The endurance of a memory device refers to its ability to withstand repeated read and write operations. Each write and erase operation is called a cycle. Poor endurance of a memory device will lead to deterioration in data reliability, potentially causing errors after repeated write and erase operations, resulting in data corruption or loss, and shortening the lifespan of the memory device, thus increasing costs.

[0003] Therefore, there is still an urgent need to develop a memory device that has good tolerance. Summary of the Invention

[0004] This invention improves the durability of semiconductor devices, for example by providing at least a portion of the first gate dielectric layer to cover two first source / drain regions of the semiconductor device, so that the first gate dielectric layer of the semiconductor device has good structural characteristics and good durability in memory operation, and can further extend the service life of the semiconductor device and reduce costs.

[0005] According to some embodiments, the present invention provides a semiconductor device. The semiconductor device includes a substrate, a first well, two first source / drain regions, a first gate dielectric layer, and a first gate. The first well is disposed in the substrate. The two first source / drain regions are disposed in the first well and are separated from each other. The first gate dielectric layer is disposed on the substrate. The first gate dielectric layer has a multilayer structure. The first gate is disposed on the first gate dielectric layer. At least a portion of the first gate dielectric layer covers the two first source / drain regions.

[0006] According to some embodiments, the present invention provides a method for fabricating a semiconductor device. The method includes the following steps: providing a substrate; forming a first well; forming two first source / drain regions; forming a first gate dielectric layer; and forming a first gate. The first well is disposed in the substrate. The two first source / drain regions are disposed in the first well and are separated from each other. The first gate dielectric layer is disposed on the substrate. The first gate dielectric layer has a multilayer structure. The first gate is disposed on the first gate dielectric layer. At least a portion of the first gate dielectric layer covers the two first source / drain regions.

[0007] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: Simple Explanation of the Diagram

[0008] Figure 1A illustrates a schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 1B illustrates a schematic diagram of a semiconductor device according to a comparative example of the present invention; Figure 1C illustrates a schematic diagram of programming the semiconductor device of Figure 1B; Figure 1D illustrates a schematic diagram of erasing the semiconductor device of Figure 1B; Figure 2A illustrates a schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 2B illustrates a schematic diagram of a semiconductor device according to yet another embodiment of the present invention; Figure 3A illustrates a schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 3B illustrates a schematic diagram of a semiconductor device according to yet another embodiment of the present invention; Figure 4A illustrates a schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 4B illustrates a schematic diagram of a semiconductor device according to yet another embodiment of the present invention; Figure 5A illustrates a schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 5B illustrates a schematic diagram of a semiconductor device according to yet another embodiment of the present invention; Figure 6A illustrates a partial cross-sectional view of a semiconductor device according to an embodiment of the present invention; and Figure 6B illustrates an equivalent circuit diagram of the semiconductor device of Figure 6A. Implementation

[0009] The following description, in conjunction with the accompanying drawings, details various embodiments. The descriptions and drawings are provided for illustrative purposes only and are not intended to be limiting. For clarity, some elements and / or symbols may be omitted in some drawings. Furthermore, elements in the drawings may not be drawn to scale. It is anticipated that elements and features in one embodiment can be advantageously incorporated into another embodiment without further repetition.

[0010] The semiconductor device of this invention can be applied to BE-SONOS (Bandgap Engineered SONOS) memory, but this invention is not limited thereto.

[0011] Figure 1A illustrates a schematic diagram of a semiconductor device 10 according to an embodiment of the present invention.

[0012] Referring to Figure 1A, the semiconductor device 10 includes a substrate 100, a first well 110A, two first source / drain regions 120A, a first gate dielectric layer 130A1, and a first gate 140A. The first well 110A is disposed in the substrate 100. The first source / drain regions 120A are disposed in the first well 110A and are separated from each other. The first gate dielectric layer 130A1 is disposed on the substrate 100. The first gate dielectric layer 130A1 has a multilayer structure, including one or more nitride layers and one or more oxide layers. The first gate 140A is disposed on the first gate dielectric layer 130A1, wherein at least a portion of the first gate dielectric layer 130A1 covers the two first source / drain regions 120A.

[0013] Since at least a portion of the first gate dielectric layer 130A1 covers the two first source / drain regions 120A, the etching process that completely removes the first gate dielectric layer 130A1 from above the first source / drain regions 120A (i.e., the etching process NHC described later) can be skipped, making it less likely that the sidewalls of the first gate dielectric layer 130A1 will be damaged by the etching process and / or cleaning process. Therefore, compared to a comparative example where the first gate dielectric layer does not cover the two first source / drain regions 120A (as shown in Figure 1B), the sidewalls of the first gate dielectric layer 130A1 of the semiconductor device 10 have better structural characteristics (less prone to defects) and provide good tolerance in memory operation (details described below).

[0014] In some embodiments, at least a portion of the first gate dielectric layer 130A1 may be covered by two first source / drain regions 120A through other processes (e.g., through the definition of a mask).

[0015] As shown in Figure 1A, a first gate dielectric layer 130A1 and a first gate 140A are stacked on a substrate 100 along a first direction D1, and at least a portion of the first gate dielectric layer 130A1 overlaps two first source / drain regions 120A in the first direction D1. The first direction D1 is, for example, parallel to the normal direction of the upper surface of the substrate 100. In this embodiment, the first gate dielectric layer 130A1 is a multilayer structure including a first layer 1321, a second layer 1341, a third layer 136, and a fourth layer 138. The first layer 1321, the second layer 1341, the third layer 136, and the fourth layer 138 are stacked sequentially on the substrate 100 along the first direction D1. The material of the first layer 1321 includes silicon oxynitride (SiON), the material of the second layer 1341 includes silicon nitride (SiN), the material of the third layer 136 includes oxide, and the material of the fourth layer 138 includes silicon nitride (SiN). It can be simply referred to as an O / N / O / N multilayer structure, but the present invention is not limited thereto. In other embodiments, the first gate dielectric layer 130A1 may be a multilayer structure including a silicon oxynitride layer, a nitride layer, an oxide layer, a nitride layer and an oxide layer (O / N / O / N / O), or other suitable multilayer structures.

[0016] According to this embodiment, the layers overlapping the two first source / drain regions 120A in the first gate dielectric layer 130A1 along the first direction D1 are the first layer 1321 and the second layer 1341. However, the present invention is not limited to this (details are described below). As long as the upper surfaces of the two first source / drain regions 120A are covered by at least a portion of the first gate dielectric layer 130A1, this invention is within its scope of protection. The width W1 of the first layer 1321 and the second layer 1341 in the second direction D2 is greater than the width W2 of the first gate 140A, the third layer 136, and the fourth layer 138 in the second direction D2. There is a gap between the two first source / drain regions 120A in the second direction D2. The first gate 140A and the first gate dielectric layer 130A1 can extend along the third direction D3. The first direction D1, the second direction D2, and the third direction D3 can be perpendicular to each other.

[0017] According to some embodiments, substrate 100 may include more wells or doped regions (e.g., lightly doped regions LA and LB, third well 150, and deep well DNW shown in Figure 6A), which are omitted from the drawing of Figure 1A.

[0018] Figure 1B illustrates a schematic diagram of a semiconductor device 10C according to a comparative example of the present invention. The difference between semiconductor device 10C and semiconductor device 10 is that the first gate dielectric layer 130AC is different from the first gate dielectric layer 130A1; other similar or identical parts will not be described in detail.

[0019] Please refer to Figure 1B. The difference between the first gate dielectric layer 130AC and the first gate dielectric layer 130A1 is that the first layer 132 and the second layer 134 of the first gate dielectric layer 130AC do not cover the two first source / drain regions 120A, that is, the first layer 132 and the second layer 134 do not overlap the two first source / drain regions 120A in the first direction D1. The materials of the first layer 132 and the second layer 134 are the same as the materials of the first layer 1321 and the second layer 1341, respectively.

[0020] According to some embodiments, the manufacturing process of semiconductor devices 10 and 10C may include sequential steps S1 to S13 (not shown). In step S1, a first precursor layer (not shown) of a first layer 132 or 1321 is formed on substrate 100 by a deposition process. In step S3, a second precursor layer (not shown) of a second layer 134 or 1341 is formed on the first precursor layer (not shown) by a deposition process. In step S5, a third precursor layer (not shown) of a third layer 136 is formed on the second precursor layer (not shown) by a deposition process. In step S7, a fourth precursor layer (not shown) of a fourth layer 138 is formed on the third precursor layer (not shown) by a deposition process. The first to fourth precursor layers (not shown) all extend above the two first source / drain regions 120A. In step S9, a first gate precursor layer (not shown) is formed on a fourth precursor layer (not shown) using a deposition process. In step S11, excess first gate precursor layer is removed using an etching process, and the remaining first gate precursor layer forms the first gate 140A. During the etching of the first gate precursor layer, portions of the third precursor layer (not shown) and the fourth precursor layer (not shown) can be removed simultaneously, so that the remaining third and fourth precursor layers form the third layer 136 and the fourth layer 138, respectively. In step S13, a conformal oxide film (not shown) is formed on the structure formed in step S11 using a re-oxidation process. The structure of the semiconductor device formed after this step is similar to the structure of semiconductor device 10 in Figure 1A.

[0021] As shown in Figure 1B, after step S13, the excess first precursor layer (not shown) and second precursor layer (not shown) are removed by the etching process NHC, and the remaining first and second precursor layers form the first layer 132 and the second layer 134, respectively. The etching process NHC ensures that the first gate dielectric layer 130AC does not cover the two first source / drain regions 120A.

[0022] As shown in Figure 1A, the semiconductor device 10 does not undergo an etching process NHC after step S13. The first precursor layer and the second precursor layer extending above the two first source / drain regions 120A form a first layer 1321 and a second layer 1341, respectively, and the first layer 1321 and the second layer 1341 cover the two first source / drain regions 120A.

[0023] During the etching process NHC, the sidewalls of the first gate dielectric layer 130A1 or 130AC may be damaged. Since the semiconductor device 10 does not need to go through the etching process NHC, the chemical damage caused by the etchant can be reduced, and the first gate dielectric layer 130A1 has better structural characteristics than the first gate dielectric layer 130AC.

[0024] Figure 1C illustrates the semiconductor device 10C of Figure 1B being programmed. Figure 1D illustrates the semiconductor device 10C of Figure 1B being erased.

[0025] Please refer to Figure 1C. During the programming process, electrons (EL) are injected from the substrate 100 into the second layer 134 of the first gate dielectric layer 130AC, as shown by arrow AR1.

[0026] Please refer to Figure 1D. During the erasure process, the electrical hole HL is injected from the substrate 100 into the second layer 134 of the first gate dielectric layer 130AC, as shown by arrow AR3.

[0027] During programming or erasing, damage may be caused to the first gate dielectric layer 130AC, especially during erasure operations. Since the mass of holes (HLs) is greater than that of electrons (ELs), the damage caused by HL injection is greater than that caused by EL injection. The more programming / erase cycling (P / E cycling) operations are performed, the more pronounced the damage to the first gate dielectric layer 130AC caused by HL injection becomes.

[0028] Please refer to Table 1 below, which shows the results of the simulated operation of semiconductor device 10 and semiconductor device 10C. After 100,000 program / erase cycles, the critical voltage change (ΔVters) for erasing semiconductor device 10C reaches 0.8V, and the 0V read voltage can no longer distinguish between 0 and 1 states; at this point, semiconductor device 10C has failed. Conversely, the critical voltage change for erasing semiconductor device 10 is only 0.2V, and the 0V read voltage can still distinguish between 0 and 1 states; semiconductor device 10 will only fail after 1,000,000 program / erase cycles. Furthermore, the transconductance (Gm) results show that the transconductance of semiconductor device 10C after the first program / erase cycle is 21μA / V, and after the 100,000th program / erase cycle, the transconductance becomes 9μA / V, i.e., the transconductance degradation (Gm degradation) is 12μA / V (i.e., 21-9=12). The transconductance of semiconductor device 10 after the first program / erase cycle is 21 μA / V, and after the 100,000th program / erase cycle, the transconductance becomes 15 μA / V, that is, the transconductance decay value is 6 μA / V (i.e. 21-15=6), which is a significant improvement over semiconductor device 10C.

[0029]

[0030] Therefore, compared to semiconductor device 10C, since at least a portion of the first gate dielectric layer 130A1 in semiconductor device 10 covers two first source / drain regions 120A (i.e., the first layer 1321 and the second layer 1341 cover two first source / drain regions 120A), the damage caused by the programming / erasing cycle to the first gate dielectric layer 130AC is greater than the damage caused by the programming / erasing cycle to the first gate dielectric layer 130A1. Thus, semiconductor device 10 can undergo more programming / erasing cycles and has better endurance.

[0031] Figure 2A illustrates a schematic diagram of a semiconductor device 20 according to an embodiment of the present invention.

[0032] In the semiconductor device 10 of Figure 1A, the first well 110A, the two first source / drain regions 120A, the first gate dielectric layer 130A1, and the first gate 140A correspond to the first transistor T1. The difference between semiconductor device 20 and semiconductor device 10 is that semiconductor device 20 includes a second transistor T2 in addition to the first transistor T1.

[0033] Referring to Figure 2A, the semiconductor device 20 further includes a second well 110B, two second source / drain regions 120B, a second gate dielectric layer 130B, and a second gate 140B. The second well 110B, the two second source / drain regions 120B, the second gate dielectric layer 130B, and the second gate 140B correspond to the second transistor T2. The second well 110B is disposed on the substrate 100 and adjacent to the first well 110A. The two second source / drain regions 120B are disposed in the second well 110B and are separated from each other. The second gate dielectric layer 130B is disposed on the substrate 100. The second gate 140B is disposed on the second gate dielectric layer 130B, wherein the second gate dielectric layer 130B does not cover the two second source / drain regions 120B, but exposes the upper surfaces of the two second source / drain regions 120B. That is, the second gate dielectric layer 130B does not overlap with the two second source / drain regions 120B in the second direction D2.

[0034] According to some embodiments, the doping concentration of the first well 110A is different from the doping concentration of the second well 110B. In this embodiment, the doping concentration of the first well 110A is less than the doping concentration of the second well 110B, but the present invention is not limited thereto. The threshold voltage of the first gate 140A can be adjusted by adjusting the doping concentration of the first well 110A.

[0035] According to some embodiments, the first well 110A and the second well 110B have a first conductivity type, and the two first source / drain regions 120A and the two second source / drain regions 120B have a second conductivity type, wherein the first conductivity type is different from the second conductivity type. The first conductivity type is, for example, P-type, and the second conductivity type is, for example, N-type.

[0036] According to some embodiments, adjacent first source / drain regions 120A and second source / drain regions 120B of the two first source / drain regions 120A and the two second source / drain regions 120B are connected to each other.

[0037] According to some embodiments, the semiconductor device 20 further includes a drain contact DT1 and a source contact ST1, wherein the drain contact DT1 is disposed on the first source / drain region 120A of the two first source / drain regions 120A that is farther away from the second well 110B, and the source contact ST1 is disposed on the second source / drain region 120B of the two second source / drain regions 120B that is farther away from the first well 110A.

[0038] According to some embodiments, at least a portion of the first gate dielectric layer 130A1 is adjacent to and in contact with the drain contact DT1; the second gate dielectric layer 130B is separated from the source contact ST1. For example, a gap exists between the second gate dielectric layer 130B and the source contact ST1 in the second direction D2.

[0039] Figure 2B illustrates a schematic diagram of a semiconductor device 20' according to another embodiment of the present invention. The difference between the semiconductor device 20' in Figure 2B and the semiconductor device 20 in Figure 2A is that the shape of the first gate dielectric layer 130A1' is different from the shape of the first gate dielectric layer 130A1. Other similar or identical parts will not be described in detail.

[0040] Referring to Figure 2B, the first gate dielectric layer 130A1' includes an arcuate profile AS2. Specifically, the first gate dielectric layer 130A1' has a main body, with wings extending from both sides of the main body. Each wing has an arcuate profile AS2 on its upper side, extending outward from the main body. In this embodiment, the second layer 1341' in the first gate dielectric layer 130A1' includes arcuate profiles AS2 on both sides. The material of the second layer 1341' is the same as that of the second layer 1341. Other identical or similar portions will not be described in detail.

[0041] Figure 3A illustrates a schematic diagram of a semiconductor device 30 according to an embodiment of the present invention. The difference between semiconductor device 30 and semiconductor device 20 is that the first gate dielectric layer 130A2 is different from the first gate dielectric layer 130A1; other similar or identical parts will not be described in detail.

[0042] Please refer to Figures 2A and 3A. The difference between the first gate dielectric layer 130A2 and the first gate dielectric layer 130A1 is that the second layer 134 does not cover the two first source / drain regions 120A. The material of the second layer 134 is the same as that of the second layer 1341. Other similar or identical parts will not be described in detail. In other words, as shown in Figure 3A, the width of the second layer 134 in the second direction D2 is smaller than the width of the first layer 1321 in the second direction D2, so that the second layer 134 does not overlap with the two first source / drain regions 120A in the first direction D1, while the first layer 1321 still overlaps with the two first source / drain regions 120A in the first direction D1.

[0043] Figure 3B illustrates a schematic diagram of a semiconductor device 30' according to another embodiment of the present invention. The difference between the semiconductor device 30' in Figure 3B and the semiconductor device 30 in Figure 3A is that the shape of the first gate dielectric layer 130A2' is different from the shape of the first gate dielectric layer 130A2. Other similar or identical parts will not be described in detail.

[0044] Referring to Figure 3B, the first gate dielectric layer 130A2' includes an arcuate profile AS3. Specifically, the first gate dielectric layer 130A2' has a main body, with wings extending from both sides of the main body. The upper side of the wings has an arcuate profile AS3, which extends outward from the main body. In this embodiment, the first layer 1321' in the first gate dielectric layer 130A2' includes arcuate profiles AS3 on both sides. The material of the first layer 1321' is the same as that of the first layer 1321. Other identical or similar parts will not be described in detail.

[0045] Figure 4A illustrates a schematic diagram of a semiconductor device 40 according to an embodiment of the present invention. The difference between semiconductor device 40 and semiconductor device 20 is that the first gate dielectric layer 130A3 is different from the first gate dielectric layer 130A1; other similar or identical parts will not be described in detail.

[0046] Please refer to Figures 2A and 4A. The difference between the first gate dielectric layer 130A3 and the first gate dielectric layer 130A1 is that the third layer 1361 also covers the two first source / drain regions 120A. The material of the third layer 1361 is the same as that of the third layer 136. Other similar or identical parts will not be described in detail. In other words, as shown in Figure 4A, the width of the third layer 1361 in the second direction D2 is equal to the width of the first layer 1321 and the second layer 1341 in the second direction D2, and less than the width of the fourth layer 138 and the first gate 140A in the second direction D2, so that the third layer 1361 overlaps the two first source / drain regions 120A in the first direction D1.

[0047] Figure 4B illustrates a schematic diagram of a semiconductor device 40' according to another embodiment of the present invention. The difference between the semiconductor device 40' in Figure 4B and the semiconductor device 40 in Figure 4A is that the shape of the first gate dielectric layer 130A3' is different from the shape of the first gate dielectric layer 130A3. Other similar or identical parts will not be described in detail.

[0048] Referring to Figure 4B, the first gate dielectric layer 130A3' includes an arcuate profile AS4. Specifically, the first gate dielectric layer 130A3' has a main body, with wings extending from both sides of the main body. The upper side of the wings has an arcuate profile AS4, which extends outward from the main body. In this embodiment, the third layer 1361' in the first gate dielectric layer 130A3' includes arcuate profiles AS4 on both sides. The material of the third layer 1361' is the same as that of the third layer 1361. Other identical or similar parts will not be described in detail.

[0049] Figure 5A illustrates a schematic diagram of a semiconductor device 50 according to an embodiment of the present invention. The difference between semiconductor device 50 and semiconductor device 20 is that the first gate dielectric layer 130A4 is different from the first gate dielectric layer 130A1; other similar or identical parts will not be described in detail.

[0050] Please refer to Figures 2A and 5A. The difference between the first gate dielectric layer 130A4 and the first gate dielectric layer 130A1 is that the third layer 1361 to the fourth layer 1381 also cover the two first source / drain regions 120A. The materials of the third layer 1361 and the fourth layer 1381 are the same as those of the third layer 136 and the fourth layer 138, respectively. Other similar or identical parts will not be described in detail. In other words, as shown in Figure 5A, the widths of the first layer 1321 to the fourth layer 1341 in the second direction D2 are the same and greater than the width of the first gate 140A in the second direction D2, so that the first layer 1321 to the fourth layer 1341 all overlap the two first source / drain regions 120A in the first direction D1.

[0051] Figure 5B illustrates a schematic diagram of a semiconductor device 50' according to another embodiment of the present invention. The difference between the semiconductor device 50' in Figure 5B and the semiconductor device 50 in Figure 5A is that the shape of the first gate dielectric layer 130A4' is different from the shape of the first gate dielectric layer 130A4. Other similar or identical parts will not be described in detail.

[0052] Referring to Figure 5B, the first gate dielectric layer 130A4' includes an arcuate profile AS5. Specifically, the first gate dielectric layer 130A4' has a main body, with wings extending from both sides of the main body. The upper side of the wings has an arcuate profile AS5, which extends outward from the main body. In this embodiment, the fourth layer 1381' in the first gate dielectric layer 130A4' includes arcuate profiles AS5 on both sides. The material of the fourth layer 1381' is the same as that of the fourth layer 1381. Other identical or similar parts will not be described in detail.

[0053] Figure 6A shows a partial cross-sectional view of a semiconductor device 60 according to an embodiment of the present invention; Figure 6B shows an equivalent circuit diagram of the semiconductor device 60 in Figure 6A.

[0054] Referring to Figures 6A and 6B, the semiconductor device 60 includes at least one transistor row (TW). In some embodiments, the number of transistor rows (TW) is multiple, and multiple transistor rows (TW) form a transistor array. For example, Figure 6B illustrates at least one transistor row (TW) including two transistor rows (TW1 and TW2), but the number of transistor rows in this invention is not limited to this. Transistor row (TW1) is composed of a combination of a first bonding unit U1 and a second bonding unit U2. Transistor row (TW2) has the same structure as transistor row (TW1), and is also composed of a combination of a first bonding unit U1 and a second bonding unit U2. In this embodiment, each transistor row (TW) is composed of a first bonding unit U1 and a second bonding unit U2, but this invention is not limited to this. In other embodiments, each transistor row (TW) may be composed of multiple first bonding units U1 and multiple second bonding units U2.

[0055] Each transistor arrangement TW includes a first side SD1 and a second side SD2, with the second side SD2 relative to the first side. For example, the first side SD1 and the second side SD2 correspond to the right and left sides, respectively. The first bonding unit U1 includes a first transistor T1 adjacent to the first side SD1 and a second transistor T2 adjacent to the second side SD2. The second bonding unit U2 includes a first transistor T1 adjacent to the second side SD2 and a second transistor T2 adjacent to the first side SD1. As shown in Figure 6A, the structure of the first gate dielectric layer 130A1' corresponding to the first transistor T1 in the first bonding unit U1 and the second bonding unit U2 is the same as the structure of the first gate dielectric layer 130A1' shown in Figure 2B, having an arc-shaped profile AS2. However, the present invention is not limited to this. The structure of the first gate dielectric layer 130A1' corresponding to the first transistor T1 in the first bonding unit U1 and the second bonding unit U2 can be the structure of the first gate dielectric layer 130A1~130A4' corresponding to the first transistor T1 shown in Figures 2A~5B or other suitable structures.

[0056] The first transistor T1 of the first bonding unit U1 and the first transistor T1 of the second bonding unit U2 share a drain contact SD1. The second transistor T2 of the first bonding unit U1 and the second transistor T2 of the second bonding unit U2 are electrically connected to different source contacts ST1 and ST2, respectively.

[0057] According to some embodiments, the first bonding unit U1 and the second bonding unit U2 can be arranged in an alternating or repeating manner. For example, each transistor arrangement TW can be four repetitions of the first bonding unit U1 and the second bonding unit U2, that is, from the second side SD2 to the first side SD1, the sequence is first bonding unit U1-second bonding unit U2-first bonding unit U1-second bonding unit U2-first bonding unit U1-second bonding unit U2-first bonding unit U1-second bonding unit U2, but the present invention is not limited thereto.

[0058] According to some embodiments, the substrate 100 further includes a plurality of lightly doped regions LA and LB, a third well 150, and a deep well DNW. Two lightly doped regions LA are disposed in a first well 110A and are separated from each other, and the two lightly doped regions LA are respectively adjacent to two first source / drain regions 120A. Two lightly doped regions LB are disposed in a second well 110B and are separated from each other, and the two lightly doped regions LB are respectively adjacent to two second source / drain regions 120B. The third well 150 is adjacent to the second well 110B. The deep well DNW is disposed below the first well 110A and the second well 110B.

[0059] According to some embodiments, the lightly doped regions LA and LB have a second conductivity type (e.g., N-type), and the doping concentrations of the lightly doped regions LA and LB are lower than the doping concentrations of the first source / drain region 120A and the second source / drain region 120B, respectively. The third well 150 and the deep well DNW also have a second conductivity type (e.g., N-type).

[0060] As shown in Figures 6A and 6B, in each transistor arrangement TW1 and TW2, the first transistor T1 and the second transistor T2 in the first bonding unit U1 and the second bonding unit U2 are electrically connected to each other through the corresponding first source / drain region 120A and second source / drain region 120B.

[0061] Each transistor array TW1 and TW2 has a first bonding unit U1 and a second bonding unit U2, which can each serve as a memory cell. Figure 6B illustrates a 2×2 memory cell array, but the invention is not limited thereto. The first gate 140A in the first transistor T1 serves as a memory gate, and the second gate 140B in the second transistor T2 serves as a selective gate. The first bonding unit U1 and the second bonding unit U2 in transistor array TW1 are electrically connected to bit line BL0 via a shared drain contact DT1, and the first bonding unit U1 and the second bonding unit U2 in transistor array TW2 are electrically connected to bit line BL1 via a shared drain contact DT1. The source contacts ST1 and ST2 in transistor arrays TW1 and TW2 are electrically connected to a common source line CSL. The first gate 140A of the first bonding unit U1 in transistor array TW1 is electrically connected to the first gate 140A of the first bonding unit U1 in transistor array TW2 (labeled as word line MG1). The second gate 140B of the first bonding unit U1 in transistor array TW1 is electrically connected to the second gate 140B of the first bonding unit U1 in transistor array TW2 (labeled as word line SG1). The first gate 140A of the second bonding unit U2 in transistor array TW1 is electrically connected to the first gate 140A of the second bonding unit U2 in transistor array TW2 (labeled as word line MG0). The second gate 140B of the second bonding unit U2 in transistor array TW1 is electrically connected to the second gate 140B of the second bonding unit U2 in transistor array TW2 (labeled as word line SG0).

[0062] During operation of the semiconductor device 60, voltages can be applied to bit lines BL0~BL1, common source line CSL, and word lines SG0~SG1 and MG0~MG1 to turn on or off the memory cells (e.g., four memory cells) corresponding to the first junction units U1 and the second junction units U2 of transistor arrays TW1 and TW2. When the second junction unit U2 of transistor array TW1 is a selected memory cell, the first junction unit U1 of transistor array TW1 is a half-selected memory cell (selecting the corresponding word lines SG1 and MG1), the second junction unit U2 of transistor array TW2 is a half-selected memory cell (selecting the corresponding bit line BL1), and the first junction unit U1 of transistor array TW2 is an unselected memory cell.

[0063] Compared to comparative examples where the memory cell has only a single transistor, the memory cell of the semiconductor device of the present invention uses two transistors (i.e., a first transistor T1 and a second transistor T2). The selective gate (second gate 140B) can be better controlled, resulting in lower leakage current and improved reliability during memory cell operation. While the selective gate (second gate 140B) of the semiconductor device of the present invention can operate as a high-voltage metal-oxide-semiconductor (HV MOS), the present invention is not limited thereto.

[0064] In summary, the present invention provides a semiconductor device with improved durability, wherein at least a portion of the first gate dielectric layer covers two first source / drain regions. According to an embodiment of the present invention, the sidewalls of the first gate dielectric layer of the semiconductor device are less susceptible to damage from the chemical agents used in etching or cleaning processes. Therefore, the first gate dielectric layer has good structural characteristics (less prone to defects) and exhibits good durability in memory operation, further extending the lifespan of the semiconductor device and reducing costs.

[0065] While the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0066] 10,10C,20,20',30,30',40,40',50,50',60: Semiconductor devices

[0067] 100:Substrate

[0068] 110A: Well No. 1

[0069] 110B: Second Well

[0070] 120A: First source / drain region

[0071] 120B: Second source / drain region

[0072] 130A1, 130A1', 130AC, 130A2, 130A2', 130A3, 130A3', 130A4, 130A4': First gate dielectric layer

[0073] 130B: Second gate

[0074] 132,1321,1321': First layer

[0075] 134,1341,1341': Second layer

[0076] 136,1361,1361': Third layer

[0077] 138,1381,1381': Fourth layer

[0078] 140A: First gate

[0079] 140B: Second gate

[0080] 150: Third Well

[0081] AS2, AS3, AS4, AS5: Arc-shaped profile

[0082] AR1, AR3: Arrows

[0083] BL0, BL1: Bit lines

[0084] CSL: Common Source Line

[0085] D1: First Direction

[0086] D2: Second Direction

[0087] D3: Third direction

[0088] DT1: Drain Contact

[0089] DNW: deep well

[0090] EL: Electronic

[0091] HL: Electric Hole

[0092] LA, LB: Lightly doped regions

[0093] MG0, MG1, SG0, SG1: Character lines

[0094] NHC: Etching Process

[0095] SD1: First side

[0096] SD2: Second side

[0097] ST1, ST2: Source contacts

[0098] T1: First transistor

[0099] T2: Second transistor

[0100] TW, TW1, TW2: Transistor arrangement

[0101] U1: First bonding unit

[0102] U2: Second Combining Unit

[0103] W1, W2: Width

Claims

1. A semiconductor device, comprising: substrate; The first well is disposed in the substrate; Two first source / drain regions are located in the first well and are separated from each other; A first gate dielectric layer is disposed on the substrate, wherein the first gate dielectric layer has a multilayer structure; a first gate is disposed on the first gate dielectric layer, wherein at least a portion of the first gate dielectric layer covers the two first source / drain regions; a second well is disposed on the substrate and adjacent to the first well; two second source / drain regions are disposed in the second well and separated from each other; a second gate dielectric layer is disposed on the substrate; And a second gate, disposed on the second gate dielectric layer, wherein the second gate dielectric layer exposes the upper surface of the two second source / drain regions; The first well, the two first source / drain regions, the first gate dielectric layer, and the first gate corresponding to a first transistor; the second well, the two second source / drain regions, the second gate dielectric layer, and the second gate corresponding to a second transistor; wherein the semiconductor device further includes a transistor arrangement, the transistor arrangement being composed of a combination of a first bonding unit and a second bonding unit, the first bonding unit including a first transistor adjacent to a first side and a second transistor adjacent to a second side, the second side being relative to the first side; the second bonding unit including a first transistor adjacent to the second side and a second transistor adjacent to the first side.

2. The semiconductor device as claimed in claim 1, wherein the multilayer structure comprises one or more nitride layers and one or more oxide layers.

3. The semiconductor device as claimed in claim 1, wherein the first gate dielectric layer and the first gate are stacked on the substrate along a first direction, and at least a portion of the first gate dielectric layer overlaps the two first source / drain regions in the first direction.

4. The semiconductor device as claimed in claim 1, wherein the doping concentration of the first well is different from the doping concentration of the second well.

5. The semiconductor device as claimed in claim 1, wherein the first well and the second well have a first conductivity type, the two first source / drain regions and the two second source / drain regions have a second conductivity type, and the first conductivity type is different from the first conductivity type.

6. The semiconductor device as claimed in claim 1, wherein the two first source / drain regions and the two second source / drain regions are connected to each other, with the adjacent first source / drain region and second source / drain region being connected to each other.

7. The semiconductor device as claimed in claim 1 further includes a drain contact and a source contact, wherein the drain contact is disposed on the first source / drain region of the two first source / drain regions that is farther away from the second well, and the source contact is disposed on the second source / drain region of the two second source / drain regions that is farther away from the first well.

8. The semiconductor device as claimed in claim 7, wherein at least a portion of the first gate dielectric layer is adjacent to the drain contact; and the second gate dielectric layer is separated from the source contact.

9. The semiconductor device of claim 1, wherein the first gate dielectric layer has a body, and wings extend from both sides of the body to form wings, wherein the upper side of each wing has an arcuate profile that extends outward from the body.

10. The semiconductor device as claimed in claim 1, wherein the first bonding unit and the second bonding unit are arranged in an alternating or repeating manner.

11. The semiconductor device as claimed in claim 1, wherein the number of transistors arranged is a plurality of transistors, the plurality of transistors arranged to form a transistor array.

12. The semiconductor device of claim 1, wherein the first transistor of the first bonding unit and the first transistor of the second bonding unit share a drain contact, and the second transistor of the first bonding unit and the second transistor of the second bonding unit are electrically connected to different source contacts.

13. A method for manufacturing a semiconductor device, comprising: Provide a substrate; A first well is formed, and the first well is disposed in the substrate; Two first source / drain regions are formed, the two first source / drain regions being disposed in the first well and separated from each other; a first gate dielectric layer is formed, the first gate dielectric layer being disposed on the substrate, wherein the first gate dielectric layer is a multilayer structure; a first gate is formed, the first gate being disposed on the first gate dielectric layer, wherein at least a portion of the first gate dielectric layer covers the two first source / drain regions; a second well is formed, the second well being disposed on the substrate and adjacent to the first well; two second source / drain regions are formed, the two second source / drain regions being disposed in the second well and separated from each other; A second gate dielectric layer is formed, and the second gate dielectric layer is disposed on the substrate; And a second gate is formed, the second gate being disposed on the second gate dielectric layer, wherein the second gate dielectric layer exposes the upper surface of the two second source / drain regions; The first well, the two first source / drain regions, the first gate dielectric layer, and the first gate corresponding to a first transistor; the second well, the two second source / drain regions, the second gate dielectric layer, and the second gate corresponding to a second transistor; wherein the semiconductor device further includes a transistor arrangement, the transistor arrangement being composed of a combination of a first bonding unit and a second bonding unit, the first bonding unit including a first transistor adjacent to a first side and a second transistor adjacent to a second side, the second side being relative to the first side; the second bonding unit including a first transistor adjacent to the second side and a second transistor adjacent to the first side.

14. A method of manufacturing a semiconductor device as claimed in claim 13, wherein the first well and the second well have a first conductivity type, and the two first source / drain regions and the two second source / drain regions have a second conductivity type, the second conductivity type being different from the first conductivity type.

15. The method of manufacturing a semiconductor device as claimed in claim 13 further includes forming a drain contact and a source contact, wherein the drain contact is disposed on the first source / drain region of the two first source / drain regions that is farther away from the second well, and the source contact is disposed on the second source / drain region of the two second source / drain regions that is farther away from the first well.

16. A method of manufacturing a semiconductor device as claimed in claim 15, wherein at least a portion of the first gate dielectric layer is adjacent to the drain contact; and the second gate dielectric layer is separated from the source contact.

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