Cross-couple gate input connections in complementary field-effect transistor cell architecture

Abstract

A chip includes a first source / drain, a second source / drain, a top gate disposed between the first source / drain and the second source / drain, and one or more first channels coupled between the first source / drain and the second source / drain, wherein the one or more first channels pass through the top gate. The chip also includes a third source / drain, wherein the third source / drain is vertically stacked with the first source / drain, a fourth source / drain, wherein the fourth source / drain is vertically stacked with the second source / drain, and a first insulator disposed below the top gate and between the third source / drain and the fourth source / drain, wherein the first insulator electrically isolates the top gate from the third source / drain and the fourth source / drain.

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