SCR layout structure

Abstract

A SCR (Silicon Controlled Rectifier) layout structure includes a substrate, a plurality of cathode active areas, a plurality of anode active areas, and a plurality of trigger nodes. The plurality of cathode active areas, the plurality of anode active areas, and the plurality of trigger nodes are all disposed in the substrate. The cathode active areas and the anode active areas are alternately arranged. The trigger nodes are disposed close to two sides of each of the cathode active areas, and the trigger nodes at different sides are staggered with each other.

Description

[Technical Field]

[0001] This invention relates to a silicon controlled rectifier (SCR), and more particularly to a silicon controlled rectifier layout structure. [Previous Technology]

[0002] A silicon controlled rectifier is a three-terminal thyristor element used to control the current flowing to a load.

[0003] In current silicon controlled rectifiers, the active region of the cathode is in the reverse bias region, where electrostatic discharge (ESD) / surge energy generates power consumption and heat. Since the current layout cannot fully utilize the area of ​​the active region of the cathode, the ESD / surge capacity per unit area is relatively low; to achieve a higher ESD / surge capacity, the area needs to be increased.

[0004] However, the increase in area will increase the capacitance. And the requirements for the capacitance value of ESD protection components in high-speed interface are getting lower and lower. This means that when designing ESD protection components with small capacitors, the ESD / Surge capability will be sacrificed, resulting in the ESD protection capability not meeting the application requirements. [Summary of the Invention]

[0005] The silicon controlled rectifier layout structure proposed in this invention includes a substrate, multiple cathode active regions, multiple anode active regions, and multiple trigger nodes. The cathode active regions are disposed within the substrate. The anode active regions are disposed within the substrate, and the multiple anode active regions and multiple cathode active regions are alternately distributed. The trigger nodes are all disposed within the substrate and are adjacent to both sides of each cathode active region. The multiple trigger nodes located on different sides are staggered.

[0006] In one embodiment of the present invention, the trigger node is connected to each cathode active region.

[0007] In one embodiment of the present invention, the trigger node and each cathode active region have an isolation structure.

[0008] In one embodiment of the present invention, the number of trigger nodes adjacent to the first side of each cathode active region is less than the number of trigger nodes adjacent to the second side of each cathode active region, wherein the first side is relative to the second side.

[0009] In one embodiment of the present invention, the number of trigger nodes adjacent to the first side of each cathode active region is greater than the number of trigger nodes adjacent to the second side of each cathode active region, wherein the first side is relative to the second side.

[0010] In one embodiment of the present invention, in a top view, the cathode active region extends along a first direction, and the anode active region also extends along a first direction.

[0011] In one embodiment of the present invention, in a top view, trigger nodes located on different sides are staggered with each other in a second direction, the second direction being perpendicular to the first direction.

[0012] In one embodiment of the present invention, the trigger nodes located on different sides do not overlap in the second direction described above.

[0013] In one embodiment of the present invention, the trigger nodes located on different sides partially overlap in the second direction described above.

[0014] In one embodiment of the present invention, the edges of the trigger nodes located on different sides are aligned with each other in the second direction described above.

[0015] Another silicon controlled rectifier layout structure proposed in this invention includes at least a substrate, a first P+ region, a P-well region, a plurality of first N+ regions, a second P+ region, a second N+ region, and a third N+ region. The substrate has a plurality of alternating first active regions and a plurality of second active regions. The first P+ region is disposed within the first active region, and the P-well region is disposed within the second active region. The plurality of first N+ regions are disposed within the plurality of second active regions on both sides of the P-well region, and the first N+ regions located on different sides are staggered, wherein the aforementioned first N+ regions serve as trigger nodes for the silicon controlled rectifier. The second P+ region is disposed within the P-well region, the second N+ region is disposed within the first side P-well region of the second P+ region, and the third N+ region is disposed within the second side P-well region of the second P+ region. The first side of the second P+ region is the second side relative to the second P+ region.

[0016] In another embodiment of the present invention, the plurality of first N+ regions are connected to the P well region.

[0017] In another embodiment of the present invention, the above-described layout structure may further include an isolation structure to separate the first N+ region from the second N+ region or the third N+ region in the P well region.

[0018] In another embodiment of the present invention, the number of first N+ regions located on the first side of the above-mentioned P well region is less than the number of first N+ regions located on the second side of the above-mentioned P well region, wherein the first side of the above-mentioned P well region is relative to the second side of the P well region.

[0019] In another embodiment of the present invention, the number of first N+ regions located on the first side of the above-mentioned P well region is greater than the number of first N+ regions located on the second side of the above-mentioned P well region, wherein the first side of the above-mentioned P well region is relative to the second side of the P well region.

[0020] In another embodiment of the present invention, in a top view, the first P+ region extends along a first direction, and the second P+ region also extends along the first direction.

[0021] In another embodiment of the present invention, in a top view, a plurality of first N+ regions located on different sides are staggered with each other in a second direction, and the second direction is perpendicular to the first direction.

[0022] Based on the above, in the silicon controlled rectifier layout structure of the present invention, the trigger nodes are arranged in an alternating manner on both sides of the cathode active area. Therefore, without affecting the electrical properties, the heat dissipation capacity of the component can be increased, thereby improving the ESD / Surge capability of the ESD component. When the component is subjected to electrostatic discharge or surge, more of the cathode active area (also known as cathode OD) is used to withstand the energy of ESD or surge, thereby improving the ESD and surge protection capability. Moreover, because an alternating trigger node layout is adopted, the number of trigger nodes can be reduced, thus reducing capacitance and making the layout design of the present invention suitable for low-capacitance applications.

[0023] In order to make the above features of the present invention more obvious and understandable, specific embodiments are given below, and detailed descriptions are provided in conjunction with the accompanying drawings.

Implementation Method

[0024] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. Furthermore, the dimensions of the components in the drawings are for illustrative purposes only and do not represent actual proportions.

[0025] Figure 1 is a plan view of a silicon controlled rectifier layout structure according to an embodiment of the present invention.

[0026] Referring to Figures 1 and 2, the silicon controlled rectifier layout structure 10 of this embodiment includes a substrate 100 and multiple anode active regions OD1 (or first active regions), multiple cathode active regions OD2 (or second active regions), and multiple trigger nodes OD3 disposed within the substrate 100. The anode active regions OD1 and cathode active regions OD2 are alternately distributed. For example, in the top view (Figure 1), the cathode active region OD2 extends along the first direction D1, and the anode active region OD1 also extends along the first direction D1. The trigger nodes OD3 are adjacent to both sides of each cathode active region OD2, and the multiple trigger nodes OD3 located on different sides are staggered. For example, in Figure 1, the trigger node OD3 located on the first side s1 and the trigger node OD3 located on the second side s2 are staggered in the second direction D2, wherein the second direction D2 is perpendicular to the first direction D1, and the first side s1 is relative to the second side s2.

[0027] In this embodiment, the trigger nodes OD3 located on different sides do not overlap in the second direction D2. However, the present invention is not limited thereto. In another embodiment, the trigger nodes OD3 located on different sides may partially overlap in the second direction D2; or, the edges of the trigger nodes OD3 located on different sides are tangent to each other in the second direction D2. In other words, different application requirements (such as ESD / Surge, capacitance, etc.) can be met by adjusting the length l1~l2, width w1~w2, and / or the distance d1~d2 between each trigger node OD3. In some embodiments, for applications requiring low capacitance, the number of trigger nodes OD3 can be reduced by increasing the distance d1~d2 between trigger nodes OD3. In some embodiments, for applications requiring high ESD / Surge capability, the area or number of trigger nodes OD3 can be increased by adjusting the size of the trigger nodes OD3 or the distance d1~d2.

[0028] In Figures 2 and 3, which are cross-sections along the second direction D2, the anode active region OD1, the cathode active region OD2, and the trigger node OD3 are regions defined by the isolation structure O1. In some embodiments, the isolation structure O1 is, for example, a shallow trench insulation (STI) structure or a silicon localized oxidation (LOCOS) structure. The anode active region OD1 may include a first P+ region 200, the trigger node OD3 may include a first N+ region 204, and the cathode active region OD2 includes a P-well region 202 and a second P+ region 206, a second N+ region 208, and a third N+ region 210 disposed within the P-well region 202. Therefore, the aforementioned doped regions (first P+ region 200, P-well region 202, second P+ region 206, second N+ region 208, and third N+ region 210) all extend along the first direction D1, and the plurality of first N+ regions 204 located on different sides are staggered on the second direction D2, and the first N+ regions 204 are connected to the P-well regions 202. The second N+ region 208 is disposed on the first side s3 of the second P+ region 206, and the third N+ region 210 is disposed on the second side s4 of the second P+ region 206, wherein the first side s3 of the second P+ region 206 is relative to the second side s4 of the second P+ region 206. In some embodiments, any one of the anode active region OD1, the cathode active region OD2, and the trigger node OD3 may also include other doped regions or buried regions (not shown) with different doping concentrations, etc., to adjust the electrical characteristics or SCR device characteristics.

[0029] In Figure 1, trigger nodes OD3 are connected to each cathode active region OD2, and the number of trigger nodes OD3 adjacent to the first side s1 of each cathode active region OD2 is less than the number of trigger nodes OD3 adjacent to its second side s2. Therefore, referring to Figures 2 and 3, the number of first N+ regions 204 located on the first side s1 of the P-well region 202 is also less than the number of first N+ regions 204 located on the second side s2 of the P-well region. However, the present invention is not limited thereto; in other embodiments, the number of trigger nodes OD3 adjacent to the first side s1 of each cathode active region OD2 may be greater than the number of trigger nodes OD3 adjacent to its second side s2 (not shown). In other words, the number of first N+ regions 204 located on the first side s1 of the P-well region 202 in Figures 2 and 3 may also be greater than the number of first N+ regions 204 located on the second side s2 of the P-well region.

[0030] Figure 4 is a schematic diagram of the silicon controlled rectifier layout structure in Figure 1 subjected to ESD / Surge energy.

[0031] Since the trigger node OD3 is a reverse bias region, it generates high power consumption and high heat, which is then transferred to the cathode. Therefore, the higher the ability of the cathode active region OD2 to withstand power consumption and heat, the higher the ESD / Surge capability. Through the staggered trigger node OD3 layout shown in Figure 1, the area that can withstand power consumption and heat (circled by the dotted line) can be increased, allowing the cathode to utilize almost its entire area, thus improving the ESD / Surge capability, as shown in Figure 4. In other words, without changing the area of ​​the cathode active region OD2, a larger area can be used, thereby increasing the ESD / Surge capability. On the other hand, if a low capacitance application is required, this can be achieved by reducing the number of trigger nodes OD3 without affecting or minimally affecting the ESD / Surge capability.

[0032] Figure 5 is a plan view of a silicon controlled rectifier layout structure according to another embodiment of the present invention. Figure 6 is a cross-sectional view along line VI-VI' of Figure 5. Figure 7 is a cross-sectional view along line VII-VII' of Figure 5. In Figures 5 to 7, the same terms or component symbols as in the previous embodiment are used to represent the same or similar parts and components, and the relevant content of the same or similar parts and components can also refer to the content of the previous embodiment, and will not be repeated here.

[0033] To enhance electrical isolation, the silicon controlled rectifier layout structure 50, compared to the previous embodiment, further includes another isolation structure O2, as shown in Figures 6 and 7. In Figure 6, the isolation structure O2 separates the first N+ region 204 from the third N+ region 210 disposed on the second side s4 of the second P+ region 206. In Figure 7, the isolation structure O2 separates the first N+ region 204 from the second N+ region 208 disposed on the first side s3 of the second P+ region 206. Therefore, the isolation structure O2 is located between the trigger node OD4 and each cathode active region OD2. The first N+ region 204 may still be connected to the first side s5 or the second side s6 of the P-well region 202, but is not limited thereto. In Figures 6 and 7, the first side s5 is relative to the second side s6. In some embodiments, the isolation structure O2 is, for example, a shallow trench insulation structure or a silicon localized oxide structure, and the isolation structure O2 may be formed simultaneously with the isolation structure O1, thus not adding any additional steps in the manufacturing process.

[0034] In Figure 5, the edges of the trigger nodes OD4 on different sides are tangent to each other in the second direction D2. However, the present invention is not limited thereto. In another embodiment, the trigger nodes OD4 on different sides may partially overlap in the second direction D2; or, the trigger nodes OD4 on different sides may not overlap in the second direction D2. The length l1~l2, width w1~w2, and / or the distance d1~d2 between the trigger nodes OD4 can be adjusted to meet different application requirements (e.g., ESD / Surge, capacitors, etc.).

[0035] The layout structures of the above embodiments can be applied to unidirectional or bidirectional SCRs to increase ESD / Surge capability and reduce component capacitance. Therefore, the present invention proposes a layout method for ESD protection components with low capacitance and high power tolerance, suitable for high-speed interface.

[0036] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0037] Figure 1 is a plan view of a silicon controlled rectifier layout structure according to an embodiment of the present invention. Figure 2 is a cross-sectional view along line II-II' of Figure 1. Figure 3 is a cross-sectional view along line III-III' of Figure 1. Figure 4 is a schematic diagram of the silicon controlled rectifier layout structure of Figure 1 subjected to ESD / Surge energy. Figure 5 is a plan view of a silicon controlled rectifier layout structure according to another embodiment of the present invention. Figure 6 is a cross-sectional view along line VI-VI' of Figure 5. Figure 7 is a cross-sectional view along line VII-VII' of Figure 6.

Claims

1. A silicon-controlled rectifier layout structure, comprising: substrate; Multiple cathode active regions are disposed within the substrate; Multiple anode active regions are disposed within the substrate, and the multiple anode active regions and the multiple cathode active regions are alternately distributed; multiple trigger nodes are disposed within the substrate adjacent to both sides of each cathode active region, and the multiple trigger nodes located on different sides are staggered with each other; and an isolation structure is disposed between the multiple trigger nodes and each cathode active region.

2. The silicon controlled rectifier layout structure as described in claim 1, wherein the plurality of trigger nodes are connected to each of the cathode active regions.

3. The silicon controlled rectifier layout structure as claimed in claim 1, wherein the number of the plurality of trigger nodes adjacent to a first side of each of the cathode active regions is less than the number of the plurality of trigger nodes adjacent to a second side of each of the cathode active regions, the first side being relative to the second side.

4. The silicon controlled rectifier layout structure as claimed in claim 1, wherein the number of the plurality of trigger nodes adjacent to a first side of each of the cathode active regions is greater than the number of the plurality of trigger nodes adjacent to a second side of each of the cathode active regions, the first side being relative to the second side.

5. The silicon controlled rectifier layout structure as claimed in claim 1, wherein, in a top view, the plurality of cathode active regions extend along a first direction, and the plurality of anode active regions also extend along the first direction.

6. The silicon controlled rectifier layout structure as described in claim 5, wherein, in the top view, the plurality of trigger nodes located on different sides are staggered with each other in a second direction, the second direction being perpendicular to the first direction.

7. The silicon controlled rectifier layout structure as described in claim 6, wherein the plurality of trigger nodes located on different sides do not overlap in the second direction.

8. The silicon controlled rectifier layout structure as described in claim 6, wherein the plurality of trigger nodes located on different sides partially overlap in the second direction.

9. The silicon controlled rectifier layout structure as described in claim 6, wherein the edges of the plurality of trigger nodes located on different sides are tangent to each other in the second direction.

10. A silicon-controlled rectifier layout structure, comprising: The substrate has multiple first active regions and multiple second active regions that are alternately distributed; The first P+ area is set within these multiple first active areas; A P-well region is located within the plurality of second active regions; a plurality of first N+ regions are located within the plurality of second active regions on both sides of the P-well region, and the plurality of first N+ regions located on different sides are staggered with each other, wherein the plurality of first N+ regions serve as trigger nodes for silicon controlled rectifiers; a second P+ region is located within the P-well region; a second N+ region is located within the P-well region on the first side of the second P+ region; And a third N+ region, located in the P well region on the second side of the second P+ region, wherein the first side of the second P+ region is relative to the second side of the second P+ region.

11. The silicon controlled rectifier layout structure as described in claim 10, wherein the plurality of first N+ regions are connected to the P-well region.

12. The silicon controlled rectifier layout structure as described in claim 10 further includes an isolation structure to separate the plurality of first N+ regions from the second N+ region or the third N+ region within the P-well region.

13. The silicon controlled rectifier layout structure as claimed in claim 10, wherein the number of the plurality of first N+ regions located on the first side of the P-well region is less than the number of the plurality of first N+ regions located on the second side of the P-well region, wherein the first side of the P-well region is relative to the second side of the P-well region.

14. The silicon controlled rectifier layout structure as claimed in claim 10, wherein the number of the plurality of first N+ regions located on the first side of the P-well region is greater than the number of the plurality of first N+ regions located on the second side of the P-well region, wherein the first side of the P-well region is relative to the second side of the P-well region.

15. The silicon controlled rectifier layout structure as described in claim 10, wherein, in a top view, the first P+ region extends along a first direction, and the second P+ region also extends along the first direction.

16. The silicon controlled rectifier layout structure as claimed in claim 15, wherein, in the top view, the plurality of first N+ regions located on different sides are staggered with each other in a second direction, and the second direction is perpendicular to the first direction.

Images