Mask, integrated circuit, and method of controlling threshold voltages of the integrated circuit by using the mask
TW202641107APending Publication Date: 2026-10-01SAMSUNG ELECTRONICS CO LTD
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Patent Information
- Application Number
- TW114129173
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-12-11
- Filing Date
- 2025-07-31
- Publication Date
- 2026-10-01
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Abstract
A method controls threshold voltages for a plurality of transistors of a device to be manufactured. The device to be manufactured includes a plurality of logic cell regions in which a logic cell is formed, an active cell region in which an active cell is formed, and a first dummy cell region adjacent to a first logic cell region of the plurality of logic cell regions and adjacent to the active cell region , the first dummy cell region including a break region electrically isolated from each of the plurality of logic cell regions, the logic cell having a first width in a first direction and the active cell having a second width smaller than the first width in the first direction, the first dummy cell region being adjacent to the active cell region in the first direction. The method includes placing a device under manufacture that is to be formed into the device to be manufactured in a process chamber, the device under manufacture having device regions that correspond to the regions of the device to be manufactured; performing a first doping process on the device under manufacture by using a first mask that includes an opening exposing the device region corresponding to the active cell, exposing the device region corresponding to the first dummy cell region, and exposing the device region corresponding to the first logic cell region; and performing a second doping process on the device under manufacture by using a second mask that includes an opening exposing the device region corresponding to the active cell, exposing the device region corresponding to the first dummy cell region, and covering the device region corresponding to the first logic cell region.
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