Memory device and methods of fabricating the same

Abstract

A memory device and its fabricating method are provided. The method includes forming a first word line (WL) nitride layer on an active area and a STI region, forming a WL mask layer on the first WL nitride layer, forming WL trenches extending through the WL mask layer, forming a WL metal layer and a second WL nitride layer in the WL trenches, removing the WL mask layer to form trenches, forming a bit line (BL) contact and a capacitor contact in the trenches, filling the trenches with a WL filling layer, forming a bit line on the BL contact through the WL filling layer, and forming a contact plug on the capacitor contact. The second WL nitride layer includes a first portion above a top surface of the first WL nitride layer and a second portion between the first portion and the WL metal layer.

Description

Technical Field

[0001] This disclosure relates to memory devices and methods of manufacturing them. Prior Technology

[0002] Advances in semiconductor technology have reduced the critical dimension (CD) of semiconductor components in memory devices, thereby increasing component integration within memory devices. However, as the critical dimension of components decreases, semiconductor manufacturing technology faces many challenges. For example, the reduction in the size of semiconductor components in memory devices may make it more difficult to align components between different layers of the memory device. Summary of the Invention

[0003] According to some embodiments of this disclosure, a method of manufacturing a memory device includes forming an active region and a shallow trench isolation region adjacent to the active region; forming a first word line nitride layer on the active region and the shallow trench isolation region; forming a word line masking layer on the first word line nitride layer; forming a plurality of word line trenches extending into the active region and the shallow trench isolation region; and forming a word line metal layer and a second word line nitride layer in the word line trenches to form a plurality of word lines. The second word line nitride layer includes a first portion located above the top surface of the first word line nitride layer and a second portion located between the first portion and the word line metal layer. The method further includes removing the word line masking layer to form a plurality of trenches between the word lines; extending the trenches into the active region and the shallow trench isolation region; forming bit line contacts and capacitor contacts in the trenches; filling the trenches with a word line filling layer; forming bit lines through the word line filling layer on the bit line contacts; and forming contact plugs on the capacitor contacts.

[0004] In some embodiments, the thickness of the character line masking layer is the same as the height of the first portion of the second character line nitride layer.

[0005] In some embodiments, the thickness of the character line fill layer is the same as the height of the first portion of the second character line nitride layer.

[0006] In some embodiments, after a second character line nitride layer is formed in the character line trench, the top surface of the second character line nitride layer is flush with the top surface of the character line mask layer.

[0007] In some embodiments, the distance between the top surface of the bit line contact and the top surface of the first word line nitride layer is less than or equal to half the thickness of the first word line nitride layer.

[0008] In some embodiments, the method further includes forming a bitline trench through the wordline filling layer to expose bitline contacts, forming a plurality of bitline spacers on a plurality of sidewalls of the bitline trench, and filling the bitline trench with a bitline polysilicon layer, a bitline metal layer on the bitline polysilicon layer, and a bitline nitride layer on the bitline metal layer.

[0009] In some embodiments, the height of the bit line is the same as the sum of the thickness of the word line fill layer and the thickness of the etch stop layer located below the word line fill layer.

[0010] In some embodiments, the method further includes forming an etch stop layer covering a first character line nitride layer, a second character line nitride layer, a bit line contact, and a capacitor contact, and forming a character line fill layer on the etch stop layer located in a trench, wherein the top surface of the etch stop layer located on the second character line nitride layer is flush with the top surface of the character line fill layer.

[0011] In some embodiments, the method further includes removing the character line fill layer, performing a through-process on the etch stop layer to form a contact trench exposing the capacitor contacts, and forming a contact plug in the contact trench.

[0012] In some embodiments, the method further includes forming a sacrificial layer on the first word line nitride layer and the second word line nitride layer, and performing an etching process on the sacrificial layer located on the bottom surface of the trenches to extend the trenches through the sacrificial layer and the first word line nitride layer, and to extend the trenches into the active region and the shallow trench isolation region, wherein after the etching process, a portion of the sacrificial layer remains on the sidewall of the trench.

[0013] In some embodiments, the sacrificial layer is removed after the bit line contacts and capacitor contacts are formed and before the word line fill layer is formed.

[0014] In some embodiments, the etching process includes etching a sacrificial layer using a first etching gas, etching a first character line nitride layer using a second etching gas, and etching an active region using a third etching gas, wherein the first etching gas, the second etching gas, and the third etching gas are different from each other.

[0015] In some embodiments, the method further includes planting bit line contacts and capacitor contacts before forming a word line fill layer, or forming a silicon layer on the bit line contacts and capacitor contacts before forming a word line fill layer.

[0016] In some embodiments, forming a character line trench includes patterning a photoresist located on a character line mask layer to form a plurality of openings that expose the character line mask layer, and etching the character line mask layer, a first character line nitride layer, an active region, and a shallow trench isolation region through the openings in the photoresist.

[0017] In some embodiments, the depth of the character line trench extending into the active region is less than the depth of the character line trench extending into the shallow trench isolation region.

[0018] According to some embodiments of this disclosure, a memory device includes an active region and a shallow trench isolation region located above a substrate, a first word line nitride layer located on the active region and the shallow trench isolation region, a first word line extending into the active region, and a second word line extending into the shallow trench isolation region. Each of the first word line and the second word line includes a word line metal layer and a second word line nitride layer located on the word line metal layer, wherein the second word line nitride layer includes a first portion located above the top surface of the first word line nitride layer and a second portion located between the first portion and the word line metal layer. The memory device further includes an etch stop layer located on the first word line nitride layer and the active region, a bit line connected to a bit line contact in the active region, and a contact plug connected to a capacitor contact in the active region.

[0019] In some embodiments, the top surface of the bit line contact and the top surface of the capacitor contact are higher than or flush with the middle height position of the first bit line nitride layer.

[0020] In some embodiments, the thickness of the bit line located on the etch stop layer is the same as the height of the first portion of the second word line nitride layer.

[0021] In some embodiments, the first character line nitride layer and the second character line nitride layer are formed of the same nitride material.

[0022] In some embodiments, the top surface of the character line metal layer is lower than the top surface of the active region.

[0023] According to the above embodiments, the method for manufacturing a memory device disclosed herein includes forming word lines in word line trenches through a word line mask layer, and forming bit line contacts and capacitor contacts in trenches between the word lines. The pattern of the word line mask layer defines the patterns of the word lines, bit line contacts, and capacitor contacts, thereby reducing the number of masks used in the process, improving critical dimension accuracy, and improving the alignment of these components of the memory device. Simple Explanation of the Diagram

[0024] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Figure 1 illustrates a flowchart of an example method for manufacturing a memory device according to some embodiments of the present disclosure. Figure 2A illustrates a schematic top view of a manufacturing stage of a memory device according to some embodiments of the present disclosure. Figures 2B to 2C, 3 to 7, and 8A illustrate schematic cross-sectional views of the memory device at various manufacturing stages according to some embodiments of the present disclosure. Figure 8B illustrates a schematic top view of a memory device at a manufacturing stage, according to some embodiments of the present disclosure. Figures 9A to 9B and 10 to 13 illustrate schematic cross-sectional views of a memory device at various manufacturing stages according to some embodiments of the present disclosure. Implementation

[0025] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0026] Furthermore, this document may use spatial relative terms such as "below," "under," "lower," "above," "upper," etc., to facilitate the description of the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to encompass different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly.

[0027] According to several embodiments of the present disclosure, Figure 1 illustrates a flowchart of an example method 1000 for manufacturing a memory device. The following description will be based on Figure 1, Figures 2A to 2C, Figures 3 to 7, Figures 8A to 8B, Figures 9A to 9B, and Figures 10 to 13. According to some embodiments of the present disclosure, Figures 2A and 8B illustrate schematic top views of the memory device 100 at various manufacturing stages; Figure 2B illustrates a schematic cross-sectional view of the memory device 100 along line AA in Figure 2A; Figures 2C, 3 to 7, 8A, and 9A illustrate schematic cross-sectional views of the memory device 100 at various manufacturing stages along line BB in Figure 2A; and Figures 9B and 10 to 13 illustrate schematic cross-sectional views of the memory device 100 at various manufacturing stages along line CC in Figure 8B.

[0028] Method 1000 is merely an example. In other embodiments of method 1000, additional steps may be provided before, during, and after method 1000, and some of the steps may be moved, replaced, or deleted. In other embodiments, the memory device 100 in the figures may have additional features added, and some of the features described below may be replaced, modified, or deleted.

[0029] In block 1010, method 1000 includes forming an active region and a shallow trench isolation (STI) region over a substrate. Referring to Figures 2A through 2C, in one embodiment of block 1010, a substrate 102 for forming a memory device 100 is provided. In some embodiments, substrate 102 may be a semiconductor substrate, such as a silicon (Si) substrate. Substrate 102 may include single-crystal semiconductor materials, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Alternatively, substrate 102 may include compound semiconductors and / or alloy semiconductors.

[0030] A plurality of active regions 104 are formed above the substrate 102. The active regions 104 are separated from each other and serve as channel regions for a plurality of memory cells in the memory device 100. For example, as shown in Figure 2A, the active regions 104 may have an island pattern in a top view. However, other embodiments may also include active regions with different patterns. In some embodiments, the active regions 104 may be formed of a silicon-containing material, such as Si or SiGe. Depending on device requirements, the active regions 104 may include various doping configurations. The active regions 104 may be formed by depositing a silicon-containing layer on the substrate 102 and then patterning the silicon-containing layer into active regions 104 by an etching process.

[0031] Shallow trench isolation regions 106 are formed above substrate 102 and adjacent to active regions 104, wherein two shallow trench isolation regions 106 sandwich one active region 104. The sidewalls of the shallow trench isolation regions 106 can directly contact the sidewalls of the active regions 104, such that the contour of the shallow trench isolation regions 106 is related to the contour of the active regions 104. For example, as shown in Figure 2C, the width of the shallow trench isolation regions 106 along the x-axis can gradually decrease towards substrate 102, while the width of the active regions 104 increases accordingly towards substrate 102. In some embodiments, the shallow trench isolation regions 106 can be formed of oxide, such as SiOx. The shallow trench isolation regions 106 can be formed by filling the gaps between the active regions 104 with an oxide material. After the formation of the active regions 104 and the shallow trench isolation regions 106 and before the formation of other components on the active regions 104, annealing and planarization processes, such as chemical mechanical polishing (CMP), can be performed.

[0032] In block 1020, method 1000 includes forming a first word line (WL) nitride layer and a word line masking layer on the active region and the shallow trench isolation region. Referring to Figures 2B to 2C, in one embodiment of block 1020, a first word line nitride layer 110 is formed on the active region 104 and the shallow trench isolation region 106, such that the first word line nitride layer 110 covers the top surfaces of the active region 104 and the shallow trench isolation region 106. Next, a word line masking layer 112 is formed on the top surface of the first word line nitride layer 110. In some embodiments, the first word line nitride layer 110 may be formed of, for example, a SiN nitride, and may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or similar methods. The character line masking layer 112 can be formed by depositing or spin-coating a hard masking material, such that the hard masking material has a thickness H1 along the z-axis. It should be noted that the thickness H1 of the character line masking layer 112 is related to the height of the subsequently formed bit line (BL) structure, which will be described in further detail below.

[0033] In block 1030, method 1000 includes forming a plurality of character line trenches extending into the active region and the shallow trench isolation region. Referring to Figure 3, in one embodiment of block 1030, a plurality of character line trenches 114 are formed, wherein the character line trenches 114 pass through the character line masking layer 112, pass through the first character line nitride layer 110, and extend into the active region 104 or the shallow trench isolation region 106. Specifically, in a cross-sectional view, the character line trenches 114 may include character line trenches 114a and 114b, wherein character line trench 114a extends into the active region 104 and has a smaller depth, and character line trench 114b extends into the shallow trench isolation region 106 and has a larger depth. It should be noted that a character line groove 114 may be a character line groove 114a for an active region 104 in one cross-sectional view, but may be a character line groove 114b for a shallow trench isolation region 106 in another cross-sectional view.

[0034] Character line trenches 114b can be formed along the sidewalls of the shallow trench isolation region 106, so that the shallow trench isolation region 106 retained in the character line trenches 114b has a uniform thickness. Character line trenches 114a and 114b are formed in the same process, therefore the contour of character line trench 114a can be similar to the contour of character line trench 114b. Depending on the process for forming the character line trenches 114, the width of the character line trenches 114 in the active region 104 or the shallow trench isolation region 106 along the x-axis can gradually decrease towards the substrate 102. In some embodiments, forming the character line trench 114 can be achieved by patterning a photoresist (not shown) on the character line mask layer 112 to form an opening that exposes the top surface of the character line mask layer 112, followed by etching the character line mask layer 112, the first character line nitride layer 110, the active region 104, and the shallow trench isolation region 106 through the opening in the photoresist. The patterning process and the etching process can be combined into a self-aligned double patterning (SADP) process.

[0035] In block 1040, method 1000 includes forming a plurality of character lines by forming a character line metal layer and a second character line nitride layer in a character line trench. Referring to Figure 4, in one embodiment of block 1040, a character line metal layer 116 is formed at the bottom of a character line trench 114 in Figure 3. In some embodiments, the character line metal layer 116 may first be filled into the character line trench 114 by any suitable process, such as atomic layer deposition, sputtering, electroplating, and / or combinations thereof. Subsequently, an etch-back process is performed on the character line metal layer 116 until the top surface of the character line metal layer 116 is lower than the top surface of the active region 104. Prior to forming the character line metal layer 116, a dielectric layer, such as an oxide layer, may be deposited in the character line trench 114, such that the dielectric layer separates the character line metal layer 116 from the active region 104 (or shallow trench isolation region 106).

[0036] Next, a second character line nitride layer 118 is formed in the character line trench 114 above the character line metal layer 116. The second character line nitride layer 118 fills the remaining portion of the character line trench 114 such that the top surface of the second character line nitride layer 118 is flush with the top surface of the character line masking layer 112. Therefore, the second character line nitride layer 118 includes a first portion 118a located above the top surface of the first character line nitride layer 110 and a second portion 118b located between the first portion 118a and the character line metal layer 116. The height H2 of the first portion 118a along the z-axis can be the same as the thickness H1 of the character line masking layer 112.

[0037] In some embodiments, the second character line nitride layer 118 may be formed of a nitride material identical to the first character line nitride layer 110, such as SiN. In such embodiments, when the second character line nitride layer 118 is formed in the character line trench 114, the second character line nitride layer 118 can directly contact the first character line nitride layer 110 without forming an observable interface between the first character line nitride layer 110 and the second character line nitride layer 118. The second character line nitride layer 118 can be deposited in the character line trench 114 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable deposition processes, followed by a planarization process or an etch-back process to form a top surface where the second character line nitride layer 118 and the character line masking layer 112 are coplanar.

[0038] In block 1050, method 1000 includes removing a character line masking layer to form a plurality of trenches between character lines. Referring to Figure 5, in one embodiment of block 1050, the character line masking layer 112 in Figure 4 is removed from the first character line nitride layer 110 by a wet etching process or a wet stripping process, leaving trenches 130 located above the first character line nitride layer 110 and between first portions 118a of the second character line nitride layer 118. Thus, the character line 120 includes a character line metal layer 116 and a second character line nitride layer 118 forming a striped pattern in the top view (as shown in Figure 8B), wherein the trenches 130 separate the first portions 118a of the character line 120. In the cross-sectional view, the character line 120 includes a character line 120a extending into the active region 104 and a character line 120b extending into the shallow trench isolation region 106, wherein a first character line nitride layer 110 connects a second character line nitride layer 118 to the character lines 120a and 120b. It should be noted that a character line 120 may be a character line 120a for an active region 104 in one cross-sectional view, but may be a character line 120b for a shallow trench isolation region 106 in another cross-sectional view. The pattern and height H2 of the character line 120 are related to the pattern and height of the subsequently formed bit line structure, which will be described in further detail below.

[0039] In block 1060, method 1000 includes forming a sacrificial layer on the first character line nitride layer and the second character line nitride layer. Referring to Figure 6, in one embodiment of block 1060, the sacrificial layer 140 is formed on the top surface of the first character line nitride layer 110, on the sidewalls of a first portion 118a of the second character line nitride layer 118, and on the top surface of the first portion 118a. The formed sacrificial layer 140 has a thin thickness such that a portion of each trench 130 remains between the character lines 120. In some embodiments, the sacrificial layer 140 may be an oxide material such as SiOx, and the sacrificial layer 140 may be formed by a highly conformal deposition process, such as atomic layer deposition.

[0040] In block 1070, method 1000 includes extending a trench between word lines into an active region and a shallow trench isolation region. Referring to Figure 7, in one embodiment of block 1070, an etching process is performed on the sacrificial layer 140 on the bottom surface of trench 130, thereby extending trench 130 downward through the sacrificial layer 140 and the first word line nitride layer 110. The bottom surface of trench 130 terminates in active region 104 (as shown in Figure 7) or in shallow trench isolation region 106 (refer to bit line contact 150 and capacitor contact 152 in Figure 9B). The etching process extends trench 130 along the sidewalls of sacrificial layer 140 located on the sidewalls of trench 130, and after extending trench 130, a portion of sacrificial layer 140 remains on the sidewalls of trench 130. Therefore, the width of the trench 130 in the active region 104 along the x-axis direction depends on the thickness of the sacrificial layer 140 on the sidewall of the trench 130.

[0041] In some embodiments, the etching process can be an anisotropic dry etching process. A multi-step etching process can be performed by changing the composition and flow rate of the etching gas, thereby effectively controlling material loss in the active region 104. For example, a first etching gas, a second etching gas different from the first etching gas, and a third etching gas different from the first and second etching gases can be used sequentially to etch the sacrificial layer 140, the first word line nitride layer 110, and the active region 104. During the etching process of the trench 130, the shallow trench isolation region 106 surrounding the word line metal layer 116 can remain unetched, thus protecting the word line metal layer 116 from exposure to the trench 130.

[0042] In block 1080, method 1000 includes forming bit line contacts and capacitor contacts in a trench located between word lines. Referring to Figures 8A to 8B, in one embodiment of block 1080, respective bit line contacts 150 and capacitor contacts 152 are formed in a trench 130 between two adjacent word lines 120. Specifically, in a cross-sectional view, bit line contacts 150 are formed at the bottom of the trench 130 between two word lines 120a, and capacitor contacts 152 are formed at the bottom of the trench 130 between word lines 120a and 120b.

[0043] The pattern of the trench 130 between the word lines 120 forms the pattern of the bit line contacts 150 and the capacitor contacts 152, wherein the pattern of the trench 130 (or word line 120) is based on the pattern of the word line masking layer 112. In other words, the pattern of the word line masking layer 112 defines the patterns of the word lines 120, the bit line contacts 150, and the capacitor contacts 152. Therefore, the word line masking layer 112 reduces the number of masks used in the process of forming the memory device 100. Using the word line masking layer 112 also improves the critical dimensional accuracy of the word lines 120, the bit line contacts 150, and the capacitor contacts 152, and improves the x-axis (or y-axis) alignment between the word lines 120, the bit line contacts 150, and the capacitor contacts 152. Specifically, bit line contacts 150 are formed according to the pattern of grooves 130 between word lines 120, so that the self-aligned bit line contacts 150 and word lines 120 can reduce the overlap of bit line contacts 150 on word lines 120. Similarly, capacitor contacts 152 and word lines 120 are also self-aligned, so that capacitor contacts 152 can have a uniform contact area.

[0044] The thickness of the bit line contact 150 and the capacitor contact 152 along the z-axis can be controlled so that the top surfaces of the bit line contact 150 and the capacitor contact 152 are higher than or flush with the middle height of the first word line nitride layer 110. In other words, the distance between the top surface of the bit line contact 150 (or the capacitor contact 152) and the top surface of the first word line nitride layer 110 is less than or equal to half the thickness of the first word line nitride layer 110, thereby reducing the risk of leakage current between the word lines 120. In some embodiments, the top surfaces of the bit line contact 150 and the capacitor contact 152 are lower than or flush with the top surface of the first word line nitride layer 110. Additionally, the width of the bit line contact 150 and the capacitor contact 152 along the x-axis depends on the width of the trench 130 with the sacrificial layer 140 located on the sidewall. Therefore, the critical dimensions of the bit line contact 150 and the capacitor contact 152 can be controlled by the thickness of the sacrificial layer 140 deposited on the sidewall of the trench 130.

[0045] In some embodiments, the bit line contact 150 and capacitor contact 152 can be formed by filling the trench 130 with a conductive material, such as polycrystalline silicon, using a deposition process. The conductive material in the trench 130 is etched back until the top surfaces of the bit line contact 150 and capacitor contact 152 are below or flush with the top surface of the first word line nitride layer 110. To adjust the resistance of the bit line contact 150 and capacitor contact 152, a dopant can be used to implant the conductive material of the bit line contact 150 and capacitor contact 152, or a silicon layer can be formed on the conductive material of the bit line contact 150 and capacitor contact 152.

[0046] In block 1090, method 1000 includes removing a sacrificial layer and forming a word line fill layer between word lines. Referring to Figures 9A and 9B, in one embodiment of block 1090, the sacrificial layer 140 is removed from the word line 120 by, for example, an etching process, thus exposing the first word line nitride layer 110 and the second word line nitride layer 118 again. An etch stop layer 160 is formed to cover the first word line nitride layer 110, the second word line nitride layer 118, the bit line contact 150, and the capacitor contact 152. The formed etch stop layer 160 has a thin thickness such that a portion of each trench 130 remains between the word lines 120. In some embodiments, the etch stop layer 160 may be formed of, for example, a SiN nitride, and the etch stop layer 160 may have a thickness H3 along the z-axis direction. The etch stop layer 160 can be formed by a highly conformal deposition process, such as atomic layer deposition, so that the etch stop layer 160 conformally covers the top surface of the first word line nitride layer 110, the sidewalls of the second word line nitride layer 118, the top surface of the second word line nitride layer 118, the top surface of the bit line contact 150, and the top surface of the capacitor contact 152.

[0047] Next, a character line fill layer 170 is formed to fill the remaining portion of the trench 130. After forming the character line fill layer 170, the top surface of the etch stop layer 160 located on the second character line nitride layer 118 is flush with the top surface of the character line fill layer 170. In some embodiments, the character line fill layer 170 may be formed of a dielectric material different from that of the etch stop layer 160. For example, the character line fill layer 170 may be formed of an oxide, while the etch stop layer 160 may be formed of a nitride. The character line fill layer 170 may be formed by a spin coating process followed by a planarization process or an etch-back process stopping on the top surface of the etch stop layer 160. Therefore, the thickness H4 of the character line fill layer 170 along the z-axis is the same as the height H2 of the first portion 118a of the second character line nitride layer 118.

[0048] In block 1100, method 1000 includes forming bitline trenches to expose bitline contacts. Referring to Figure 10, in one embodiment of block 1100, forming bitline trench 180 can be achieved by etching through wordline fill layer 170. The width of bitline trench 180 along the y-axis corresponds to the critical dimensions of subsequently formed bitline spacers and bitlines. Specifically, in a cross-sectional view, bitline trench 180a is formed above bitline contact 150, and bitline trench 180b is formed in wordline fill layer 170 adjacent to capacitor contact 152. For the bitline trench 180 above bitline contact 150, etching through wordline fill layer 170 and etch stop layer 160 exposes the top surface of bitline contact 150. The etching process can stop at the top surface of the bitline contact 150, or it can be etched so that the top surface of the bitline contact 150 is lower than the bottom surface of the etch stop layer 160. For the bitline trench 180 above the capacitor contact 152, the etching process of the bitline trench 180 etches through the word line fill layer 170 and stops at the top surface of the etch stop layer 160 or the first word line nitride layer 110. During the etching process of the bitline trench 180, the shallow trench isolation region 106 can remain unetched. It should be noted that the bitline trench 180 located above the capacitor contact 152 in one cross-sectional view may be located above the bitline contact 150 in another cross-sectional view.

[0049] In some embodiments, forming the bitline trench 180 can be achieved by forming a bitline mask layer (not shown) on the wordline fill layer 170, patterning the bitline mask layer to form an opening in the bitline mask layer, and etching the wordline fill layer 170 and / or the etch stop layer 160 through the opening in the bitline mask layer. The patterning process and the etching process can be combined into a self-aligned dual patterning process.

[0050] In block 1110, method 1000 includes forming bit lines in bit line trenches. Referring to Figure 11, in one embodiment of block 1110, bit line spacers 195 are first formed on the sidewalls of bit line trenches 180. The bit line spacers 195 have a thin thickness such that a portion of each bit line trench 180 remains above the bit line contact 150 or capacitor contact 152. In some embodiments, the formed bit line spacers 195 may be multilayered low-dielectric-constant dielectric materials, such as nitride-oxide-nitride layers. The bit line spacers 195 can be formed by depositing dielectric material in the bit line trenches 180, for example, by atomic layer deposition or other highly conformal deposition processes. Next, the bit line contact 150 is exposed again by removing the dielectric material on the bottom surface of the bit line trench 180 through an etching process, wherein the same etching process can also remove the dielectric layer deposited on the word line fill layer 170 by the bit line spacer 195.

[0051] After forming the bit line spacers 195, a bit line polysilicon layer 192, a bit line metal layer 194, and a bit line nitride layer 196 are sequentially formed in the bit line trench 180, forming bit lines 190 between the bit line spacers 195, wherein the bit line polysilicon layer 192 contacts the bit line contact 150. Since the bit line spacers 195 are formed before the bit line polysilicon layer 192 and the bit line metal layer 194 are formed, the process of forming the bit lines 190 can be called a reverse bit line process. After forming the bit lines 190, the word line 120 can extend along a first direction, while the bit line 190 can extend along a second direction perpendicular to the first direction.

[0052] In some embodiments, the bit line 190 can be formed by filling the bit line trench 180 with a bit line polysilicon layer 192, etching back the bit line polysilicon layer 192 to a predetermined thickness, filling the bit line trench 180 with a bit line metal layer 194, etching back the bit line metal layer 194 to a predetermined thickness, depositing a bit line nitride layer 196 in the bit line trench 180 and on the word line filling layer 170, and performing a planarization process or an etching back process on the bit line nitride layer 196, so that the top surface of the bit line 190 is coplanar with the top surface of the word line filling layer 170.

[0053] The top surface of the topmost layer of bit line 190 (e.g., bit line nitride layer 196) is flush with the top surface of bit line spacer 195 and word line fill layer 170. In the cross-sectional view, the height H5 of bit line 190a on bit line contact 150 along the z-axis is the same as the sum of the thickness H3 of etch stop layer 160 and the thickness H4 of word line fill layer 170, and the height H6 of bit line 190b above capacitor contact 152 along the z-axis is the same as the thickness H4 of word line fill layer 170. As described above, the thickness H4 can be equal to the height H2 of the first portion 118a of the second word line nitride layer 118 (as shown in Figure 9A), where the height H2 of the first portion 118a is the same as the thickness H1 of word line mask layer 112 (as shown in Figure 4). In other words, the thickness H1 of word line mask layer 112 can define the height of bit line 190.

[0054] In block 1120, method 1000 includes forming contact trenches between bit lines. Referring to Figure 12, in one embodiment of block 1120, the word line fill layer 170 is removed from the etch stop layer 160 by an etching process, such as a wet etching process. A punch-through process is performed on the etch stop layer 160 located on the capacitor contact 152 and between the bit lines 190 to form a contact trench 200 exposing at least a portion of the top surface of the capacitor contact 152. The punch-through process may be performed on the etch stop layer 160 along the sidewalls of the bit line spacers 195. In some embodiments, a cleaning process may be performed after forming the contact trench 200 to remove contamination that may have been caused by the punch-through process.

[0055] In block 1130, method 1000 includes forming a contact plug in a contact trench. Referring to Figure 13, in one embodiment of block 1130, a contact plug 210 is formed in the contact trench 200 of Figure 12. The contact plug 210 contacts a capacitor contact 152, and the contact plug 210 may be further connected to a capacitor located above the contact plug 210. In some embodiments, forming the contact plug 210 may be performed by a deposition process of filling a polycrystalline silicon layer 212 in the contact trench 200, etching back the polycrystalline silicon layer 212 to a predetermined thickness, filling the contact trench 200 with a contact metal layer 214, and performing a planarization process or an etching back process on the contact metal layer 214, such that the top surface of the contact plug 210 is coplanar with the top surface of the bit line 190. To adjust the resistance of the contact plug 210, a polycrystalline silicon layer 212 can be implanted with a dopant, or a silicon layer can be formed on the capacitor contact 152 or the polycrystalline silicon layer 212.

[0056] In block 1140, method 1000 includes performing further manufacturing steps. The memory device (e.g., memory device 100 in Figure 13) can be further processed to form various features and regions known in the art. For example, subsequent processes can form capacitors, and various contacts / vias / traces and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) configured to connect multiple features to form functional circuitry and located above the substrate. Additionally, extra process steps can be performed before, during, and after method 1000, and various embodiments of method 1000 can replace or omit some of the aforementioned process steps.

[0057] According to the above embodiments, the method for manufacturing a memory device disclosed herein includes depositing a second word line nitride layer in word line trenches passing through a word line mask layer and a first word line nitride layer to form word lines, and forming bit line contacts and capacitor contacts in trenches between the word lines. The pattern of the word line mask layer defines the patterns of the word lines, bit line contacts, and capacitor contacts, thereby reducing the number of masks used in the process of forming the memory device. This also improves the critical dimensional accuracy of the word lines, bit line contacts, and capacitor contacts, and improves the alignment between the word lines, bit line contacts, and capacitor contacts.

[0058] The foregoing outlines features of some embodiments to enable those skilled in the art to better understand the ideas presented in this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0059] 100: Memory Device 102:Substrate 104: Active Zone 106: Shallow trench isolation area 110: First character line nitride layer 112: Character Line Masking Layer 114, 114a, 114b: Character line grooves 116: Character line metal layer 118: Nitride layer of the second character line 118a: Part One 118b: Part Two 120, 120a, 120b: Character lines 130: Trench 140: Sacrifice Layer 150: Bit line contact 152: Capacitor Contact 160: Etching Stop Layer 170: Character line fill layer 180, 180a, 180b: Bit line grooves 190, 190a, 190b: Bit lines 192: Bit line polycrystalline silicon layer 194: Bit line metal layer 195: Bit line spacers 196: nitride layer of the bit line 200: Contact groove 210: Contact plug 212: Polycrystalline silicon layer 214: Contact metal layer 1000: Method 1010, 1020, 1030, 1040, 1050, 1060, 1070, 1080, 1090, 1100, 1110, 1120, 1130, 1140: Square AA, BB, CC: lines H1: Thickness H2: Height H3, H4: Thickness H5, H6: Height x, y, z: axes

[0060] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for manufacturing a memory device, comprising: An active zone and a shallow trench isolation zone adjacent to the active zone are formed; A first character line nitride layer is formed on the active region and the shallow trench isolation region; a character line masking layer is formed on the first character line nitride layer; a plurality of character line trenches are formed, wherein the character line trenches extend through the character line masking layer and into the active region and the shallow trench isolation region; a character line metal layer and a second character line nitride layer are formed in the character line trenches to form a plurality of character lines, wherein the second character line nitride layer includes a first portion located above a top surface of the first character line nitride layer and a second portion located between the first portion and the character line metal layer; Remove the character line masking layer to form a plurality of trenches located between the character lines; extend the trenches into the active region and the shallow trench isolation region; form a character line contact and a capacitor contact in the trenches; fill the trenches with a character line filling layer; form a character line through the character line filling layer on the character line contact; and form a contact plug on the capacitor contact.

2. The method as described in claim 1, wherein the thickness of the character line mask layer is the same as the height of the first portion of the second character line nitride layer.

3. The method as described in claim 1, wherein the thickness of the character line fill layer is the same as the height of the first portion of the second character line nitride layer.

4. The method as described in claim 1, wherein after the second character line nitride layer is formed in the character line trenches, a top surface of the second character line nitride layer is flush with a top surface of the character line masking layer.

5. The method as described in claim 1, wherein the distance between a top surface of the bit line contact and the top surface of the first word line nitride layer is less than or equal to half the thickness of the first word line nitride layer.

6. The method as described in claim 1, further comprising: A bit line trench is formed through the bit line fill layer to expose the bit line contact; A plurality of bitline spacers are formed on a plurality of sidewalls of the bitline trench; and the bitline trench is filled with a bitline polycrystalline silicon layer, a bitline metal layer located on the bitline polycrystalline silicon layer, and a bitline nitride layer located on the bitline metal layer.

7. The method as described in claim 6, wherein the height of the bit line is the same as the sum of the thickness of the word line fill layer and the thickness of an etch stop layer located below the word line fill layer.

8. The method as described in claim 1, further comprising: An etch stop layer is formed, wherein the etch stop layer covers the first character line nitride layer, the second character line nitride layer, the bit line contact, and the capacitor contact; and the character line fill layer is formed on the etch stop layer located in the trenches, wherein a top surface of the etch stop layer located on the second character line nitride layer is flush with a top surface of the character line fill layer.

9. The method as described in claim 8, further comprising: Remove the character line fill layer; Perform a through-process on the etch stop layer to form a contact trench that exposes the capacitor contact; The contact plug is formed in the groove of the contact element.

10. The method as described in claim 1, further comprising: A sacrificial layer is formed on the first character line nitride layer and the second character line nitride layer; An etching process is performed on the sacrificial layer located on the bottom surface of the trenches to extend the trenches through the sacrificial layer and the first character line nitride layer, and to extend the trenches into the active region and the shallow trench isolation region, wherein after the etching process, a portion of the sacrificial layer remains on the sidewalls of the trenches.

11. The method as described in claim 10, wherein the sacrificial layer is removed after the bit line contact and the capacitor contact are formed and before the word line fill layer is formed.

12. The method as described in claim 10, wherein the etching process includes: The sacrificial layer is etched using a first etching gas; The first character line nitride layer is etched using a second etching gas. The active region is etched using a third etching gas, wherein the first etching gas, the second etching gas, and the third etching gas are different from each other.

13. The method as described in claim 1, further comprising: Before forming the character line fill layer, the bit line contact and the capacitor contact are deployed; or before forming the character line fill layer, a silicon layer is formed on the bit line contact and the capacitor contact.

14. The method as described in claim 1, wherein forming the character line trenches includes: A photoresist is patterned on the character line mask layer to form a plurality of openings that expose the character line mask layer; and the character line mask layer, the first character line nitride layer, the active region and the shallow trench isolation region are etched through the openings in the photoresist.

15. The method as described in claim 1, wherein the depth of one of the character line trenches extending into the active region is less than the depth of the other of the character line trenches extending into the shallow trench isolation region.

16. A memory device, comprising: An active region and a shallow trench isolation region are located above a substrate; A first character line nitride layer is located on the active region and the shallow trench isolation region; a first character line and a second character line, wherein the first character line extends into the active region and the second character line extends into the shallow trench isolation region, wherein each of the first character line and the second character line includes a character line metal layer and a second character line nitride layer located on the character line metal layer, and the second character line nitride layer includes a first portion located above a top surface of the first character line nitride layer and a second portion located between the first portion and the character line metal layer; an etch stop layer is located on the first character line nitride layer and the active region; a character line connected to a character line contact located in the active region; and a contact plug connected to a capacitor contact located in the active region.

17. The memory device as claimed in claim 16, wherein a top surface of the bit line contact and a top surface of the capacitor contact are above or flush with the midpoint height of the first word line nitride layer.

18. The memory device as claimed in claim 16, wherein the thickness of the bit line located on the etch stop layer is the same as the height of the first portion of the second word line nitride layer.

19. The memory device as claimed in claim 16, wherein the first word line nitride layer and the second word line nitride layer are formed of the same nitride material.

20. The memory device as claimed in claim 16, wherein a top surface of the character line metal layer is lower than a top surface of the active region.

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