Scribe seal structure

Abstract

This invention provides a scribe seal structure located between an integrated circuit area and a cutting path. The scribe seal structure includes: a substrate; a metal stack structure, which is formed by stacking multiple metal layers on the substrate, with multiple via plugs penetrating through multiple dielectric layers between the metal layers to electrically connect the metal layers, wherein a top metal layer of the metal layers is divided into two isolated blocks; a trench, which surrounds the integrated circuit area and is located between the two blocks of the top metal layer, with the trench laterally separating the two blocks of the top metal layer, and the trench extending below the top surface of the top metal layer; and a sealing material, which covers the metal stack structure and fills the trench.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit, and more particularly to a dicing and sealing structure for a semiconductor wafer. Prior Technology

[0002] Semiconductor chips are crucial in modern electronic devices, especially in high-voltage operating environments where their reliability and durability are paramount. With technological advancements, electronic devices place increasingly higher demands on the performance of semiconductor chips. However, traditional chip structures are prone to cracking and electrical failures under high-voltage operation, which can affect the stability and lifespan of the equipment.

[0003] In multi-chip module (MCM) and small outline integrated circuit (SOIC) packages, electrical connections between different chips are typically achieved via bonding wires. In high-voltage applications, the close proximity of the bonding wires to the chip surface generates a high electric field, causing premature breakdown of the isolation material, leading to short circuits and IC failures. Furthermore, improperly designed grooved seals near the chip edges can also cause cracks to propagate during chip dicing, further impacting chip reliability.

[0004] As shown in Figure 1, US Patent 11,069,627B2 discloses an improved integrated circuit structure 100 to enhance its reliability and durability under high-voltage environments. The integrated circuit structure 100 includes a multilayer structure 301, each layer having a top surface. A grooved seal 130 is provided in the multilayer structure 301, including a top metal layer 340 near the top surface. The grooved seal 130 includes a first metal stack 330 and a second metal stack 332. A trench 334 formed in the multilayer structure 301 is located between the first metal stack 330 and the second metal stack 332. An electrical insulating layer 302 covers the top surface of the top metal layer 340 and extends a certain distance. Summary of the Invention

[0005] This invention provides a cut-and-seal structure, which allows semiconductor wafers to effectively block stress generated during cutting. Subsequently, in electronic modules fabricated from these semiconductor wafers, the cut-and-seal structure provides an effective protective barrier against electric shock.

[0006] According to the above, the present invention provides a cutting and sealing structure, located between an integrated circuit region and a cutting channel, comprising: a substrate; a metal stack structure, which is composed of multiple metal layers stacked on the substrate and multiple via plugs passing through multiple dielectric layers between the metal layers to electrically connect the metal layers, wherein a top metal layer of the metal layers is divided into two isolated blocks; a trench, which is disposed around the integrated circuit region between the two blocks of the top metal layer, the trench being laterally separated from the two blocks of the top metal layer, wherein the trench extends to the area below the top surface of the top metal layer; and a sealing material, which covers the metal stack structure and fills the trench.

[0007] In one embodiment, the cut-and-seal structure further includes a protective layer located on the metal stack structure and covering the metal layer, the protective layer having an opening forming a groove, and a sealing material covering the protective layer and filling the opening.

[0008] In one embodiment, the groove in the cut-and-close structure extends downward beyond the bottom surface of the top metal layer.

[0009] According to the above, the present invention provides a semiconductor wafer, comprising: an integrated circuit region located in the middle portion of a substrate; and a dicing and sealing structure located around the substrate. The dicing and sealing structure comprises: a composite metal stack structure consisting of a first metal stack and a second metal stack, wherein the first metal stack and the second metal stack are each composed of multiple metal layers stacked on the substrate and multiple vias pass through multiple dielectric layers between the metal layers to electrically connect the metal layers; at least one of the metal layers is shared by the first metal stack and the second metal stack; and a top metal layer of the first metal stack and a top metal layer of the second metal stack are isolated from each other; a trench disposed around the integrated circuit region between the top metal layers and laterally separated from the top metal layers, wherein the trench extends to below the top surface of the top metal layer; and a sealing material covering the metal stack structure and filling the trench.

[0010] In one embodiment, the dicing and sealing structure of the semiconductor wafer further includes a protective layer located on the metal stack structure and covering the metal layer, the protective layer having an opening to form a trench, and a sealing material covering the protective layer and filling the opening.

[0011] In one embodiment, in the dicing and sealing structure of the semiconductor wafer, the metal layer shared by the first metal stack and the second metal stack is a narrower section (neck) of the composite metal stack structure.

[0012] In one embodiment, in the dicing and sealing structure of the semiconductor wafer, the plurality of metal layers shared by the first metal stack and the second metal stack are multiple narrower sections (necks) of the composite metal stack structure, so that the composite metal stack structure has a serrated side structure in the direction parallel to the dicing track.

[0013] In one embodiment, in the dicing and sealing structure of the semiconductor wafer, the trench extends beyond the top surface of the top metal layer.

[0014] Based on the above, the present invention provides a multi-chip module, including multiple semiconductor chips, at least one of which is a semiconductor chip as described above or a semiconductor chip having a cut-and-close structure as described above; and multiple bond wires electrically connecting the semiconductor chips.

[0015] In one embodiment, the semiconductor wafers of the multi-wafer module are all semiconductor wafers as described above or semiconductor wafers having the cut-and-closed-ring structure as described above. Simple Explanation of the Diagram

[0016] Figure 1 is a side cross-sectional view of a partial integrated circuit. Figure 2 is a top view of the enclosed ring structure surrounding a single wafer. Figure 3 is a cross-sectional view of a closed-loop structure along line AA in Figure 1 according to an embodiment of the present invention. Figure 4 is a cross-sectional schematic diagram of a closed-loop structure along line AA in Figure 1 according to an embodiment of the present invention. Figure 5 is a cross-sectional schematic diagram of a closed-loop structure along line AA in Figure 1 according to an embodiment of the present invention. Figure 6 is a schematic diagram of a multi-chip module according to an embodiment of the present invention. Implementation

[0017] Figure 2 is a top view of the sealing ring structure surrounding a single wafer. Referring to Figure 2, before wafer dicing, the dicing 20 separates the wafer 10 with the integrated circuit region 30 from other wafers 10'. To prevent microcracks in the integrated circuit region 30 caused by the stress generated during wafer dicing, a dicing sealing ring structure 40 is formed around the integrated circuit region 30. Therefore, the dicing sealing ring structure 40 is located between the integrated circuit region 30 and the dicing 20. Figure 3 is a cross-sectional view of the sealing ring structure along line AA in Figure 1 according to an embodiment of the present invention. Referring to Figure 3, the dicing sealing ring structure 40 includes: a substrate 400; a metal stack structure (not shown in the figure); a trench 440; and a sealing material 450. The metal stack structure consists of multiple metal layers 410 stacked on the substrate 400, with multiple via plugs 420 passing through multiple dielectric layers 430 between the metal layers 410 for electrical connection of the metal layers 410.

[0018] Continuing the above description, the top metal layer of metal layer 410 is divided into two isolated blocks 412 and 414. The top metal layer refers to the uppermost metal layer 410. A trench 440 is disposed around the integrated circuit area 30 between blocks 412 and 414 of the top metal layer. The trench 440 is laterally separated from blocks 412 and 414 of the top metal layer. The trench 440 may extend to below the top surface of the top metal layer (412, 414), that is, the trench 440 is parallel to and separate from blocks 412 and 414. The trench 440 may also extend beyond the bottom surface of the top metal layer, with a depth exceeding that of the top metal layer. As shown in Figure 3, in this embodiment, the depth of the trench 440 extends to the bottom surface (bottom plane) of the top metal layer (412, 414). The sealing material 450 covers the metal stack structure and fills the trench 440. The grooves 440 filled with sealant 450 help to inhibit the formation of cracks and their lateral propagation.

[0019] In this invention, the via plug 420 that electrically connects the upper and lower metal layers 410 refers to a conductor in the internal metal stack, typically forming a complete metal wall to prevent moisture, contaminants, and cracks from entering the internal integrated circuit area. In this invention, at least one via plug 420 with a complete metal wall is used to connect the upper and lower metal layers 410. Alternatively, conductors that serve only as electrical connections and do not form a complete metal wall may also be provided.

[0020] Referring to Figure 3, the cut-off ring structure 40 further includes a protective layer 452 disposed on the metal stack structure and covering the metal layer 410 and the dielectric layer 430. The protective layer 452 has an opening 454 forming part of the trench 440. The sealing material 450 covers the protective layer 452 and fills the opening 454. The protective layer 452, formed on the dielectric layer 430 and the metal layer 410, prevents damage or contamination to the surface of the ring structure. The protective layer 452 is patterned using a photolithography process to form the opening 454. In one embodiment, multiple protective layers may also be provided on the ring structure as needed.

[0021] Figure 5 is a cross-sectional schematic diagram of a sealing ring structure along line AA in Figure 1 according to an embodiment of the present invention. Referring to Figures 2 and 5, in one embodiment, the present invention provides a semiconductor wafer 10 including an integrated circuit region 30 and a diced sealing ring structure 40. The integrated circuit region 30 is located in the middle portion of a substrate 400. The diced sealing ring structure 40 is located around the substrate 400. In this embodiment, the diced sealing ring structure 40 includes a composite metal stack structure (not shown in the figure) composed of a first metal stack 42 and a second metal stack 44. The first metal stack 42 and the second metal stack 44 are respectively stacked on the substrate 400 by multiple metal layers 410. A plurality of via plugs 420 pass through a plurality of dielectric layers 430 between the metal layers 410 for electrically connecting the metal layers 410. A top metal layer of the first metal stack 42 and a top metal layer of the second metal stack 44 are isolated. The two isolated top metal layers can be fabricated using a patterning process.

[0022] Continuing the above description, in the multilayer metal layers 410, at least one metal layer 410 is shared by the first metal stack 42 and the second metal stack 44. In one embodiment, as shown in FIG5, three metal layers 410 are shown to be shared by the first metal stack 42 and the second metal stack 44. A trench 440 is disposed around the integrated circuit region 30 between the top metal layer 410 of the first metal stack 42 and the second metal stack 44, and the trench 440 is laterally separated from the top metal layer 410. The trench 440 may extend below the top surface of the top metal layer 410 or extend beyond the bottom surface of the top metal layer 410, as shown in FIG5. A sealing material 450 covers the metal stack structure and fills the trench 440. The sealing material 450 covering the metal stack structure and filling the trench 440 further enhances the stability and stress resistance of the structure. The sealing material can prevent the influence of the external environment on the structure and reduce the risk of stress concentration and cracking.

[0023] In one embodiment, the diced sealing ring structure 40 of the semiconductor wafer 10 further includes a protective layer 452 disposed on the metal stack structure and covering the metal layer 410 and the dielectric layer 430. The protective layer 452 has an opening 454 forming part of the trench 440. A sealing material 450 covers the protective layer 452 and fills the opening 454. The protective layer 452 formed on the dielectric layer 430 and the metal layer 410 can prevent damage or contamination of the sealing ring structure surface. The protective layer 452 is then patterned using a photolithography process to form the opening 454. In one embodiment, multiple protective layers may also be provided as needed.

[0024] Referring to Figures 2 and 4, in one embodiment, in the dicing and sealing structure 40 of the semiconductor wafer 10, the metal layer 410 shared by the first metal stack 42 and the second metal stack 44 is a narrower section (e.g., a neck) in the composite metal stack structure. The presence of the neck in the structure allows for a more uniform distribution of stress within the structure. When stress is transferred to the neck, it is redistributed, reducing stress concentration at a single point and thus reducing the risk of cracking and failure. As shown in Figure 4, three metal layers 410 are shared by the first metal stack 42 and the second metal stack 44. In this embodiment, the composite metal stack structure has multiple necks. This gives the composite metal stack structure a serrated side structure in the direction parallel to the dicing. The serrated side structure helps to disperse stress because the serrated design can change the stress transmission path and reduce stress concentration at a single point. Such a design can improve the stress resistance capability of the structure.

[0025] Based on the above, please refer to Figure 6. The present invention provides a multi-chip module 100 including a plurality of semiconductor chips 110, 120; and a plurality of bonding lines (not shown in the figure) electrically connecting the semiconductor chips 110, 120. Wherein, at least one of the semiconductor chips 110, 120 is a semiconductor chip as described above or a semiconductor chip having a cut-and-closed structure as described above.

[0026] In one embodiment, the semiconductor wafers of the multi-wafer module 100 are all semiconductor wafers as described above or semiconductor wafers having the cut-and-closed structure as described above.

[0027] With the rapid development of technologies such as electric vehicles, renewable energy, 5G communications, data centers, and high-performance computing (HPC), the demand for high-voltage multi-chip modules is constantly increasing, requiring higher power density, better heat dissipation performance, higher reliability, and long-term stable operation in extreme environments. The cut-and-seal structure provided by this invention features a composite metal stack structure, a serrated side design, and grooves filled with sealing material. The isolated top metal layer and groove-filled design reduce the risk of breakdown under high-voltage operation. The sealing material effectively shields against external environmental influences, improves voltage withstand capability, and ensures the stability of the chip in high-power applications. The serrated side structure effectively disperses mechanical stress and reduces cracking and material degradation caused by thermal stress concentration.

[0028] The embodiments described above are merely for illustrating the technical ideas and features of the present invention. Their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be used to limit the patent scope of the present invention. That is, all equivalent changes or modifications made in accordance with the spirit disclosed in the present invention should still be covered within the patent scope of the present invention.

[0029] 10, 10': Chip 20: Cutting track 30: Integrated Circuit Area 40: Cutting and sealing ring structure 42: First metal stack 44: Second metal stack 400:Substrate 410: Metal layer 412: Block 1 414: Second Block 420: Guide hole plug 430: Dielectric layer 440: Trench 450: Packaging material 452: Protective layer 454: Opening

Claims

1. A cut-and-close structure, located between an integrated circuit region and a cut track, comprising: One substrate; A composite metal stack structure comprising a first metal stack and a second metal stack, wherein the first metal stack and the second metal stack are each composed of multiple metal layers stacked on a substrate and multiple via plugs pass through multiple dielectric layers between the metal layers to electrically connect the metal layers; at least one of the metal layers is shared by the first metal stack and the second metal stack; a top metal layer of the first metal stack and a top metal layer of the second metal stack are independently isolated; and the metal layers shared by the first metal stack and the second metal stack are multiple narrower sections (necks) of the composite metal stack structure, giving the composite metal stack structure a serrated side structure in the direction parallel to the cut-out; a trench is disposed between the two top metal layers surrounding the integrated circuit area, the trench laterally separating the two top metal layers, wherein the trench extends downward beyond the bottom surface of the top metal layer; and a sealing material covers the composite metal stack structure and fills the trench.

2. The cut-and-close structure as claimed in claim 1 further includes a protective layer located on the composite metal stack structure and covering the metal layers, the protective layer having an opening forming the groove, and the sealing material covering the protective layer and filling the opening.

Images