Semiconductor devices

Abstract

A semiconductor device with excellent transistor characteristics is provided. The semiconductor device includes: a first oxide semiconductor layer and a second oxide semiconductor layer, extending along a first direction and arranged in a second direction, and comprising a first metal element and oxygen; a first conductive layer, extending along the second direction and facing a portion of the outer peripheral surfaces of the first oxide semiconductor layer and the second oxide semiconductor layer; and a first gate insulating layer and a second gate insulating layer, disposed between the first oxide semiconductor layer and the second oxide semiconductor layer and the first conductive layer. In a first cross-section extending along a third direction and including the first oxide semiconductor layer, the second oxide semiconductor layer, and the first conductive layer, the first conductive layer includes: an annular first portion disposed from the outer peripheral surface of the first oxide semiconductor layer with a distance of a first width and surrounding the first oxide semiconductor layer; and an annular second portion disposed from the outer peripheral surface of the second oxide semiconductor layer with a distance of a first width and surrounding the second oxide semiconductor layer. A portion of a circle, ellipse, or oblong circumscribed by the first portion and a portion of a circle, ellipse, or oblong circumscribed by the second portion overlap.

Description

Technical Field

[0001] This embodiment relates to a semiconductor device. Prior Technology

[0002] A semiconductor device is known, comprising: an oxide semiconductor layer, a first wiring facing the oxide semiconductor layer, and a gate insulating film disposed between the oxide semiconductor layer and the first wiring. Summary of the Invention

[0003] A semiconductor device with excellent transistor characteristics is provided. One embodiment of a semiconductor device includes: a substrate; a first oxide semiconductor layer and a second oxide semiconductor layer, extending along a first direction intersecting the surface of the substrate and arranged in a second direction intersecting the first direction, and comprising a first metal element and oxygen (O); a first conductive layer, extending along the second direction and facing a portion of the outer peripheral surface of the first oxide semiconductor layer and a portion of the outer peripheral surface of the second oxide semiconductor layer; a first gate insulating layer disposed between the first oxide semiconductor layer and the first conductive layer; and a second gate insulating layer disposed between the second oxide semiconductor layer and the first conductive layer. In a first cross-section extending along the second direction and a third direction intersecting the first and second directions and including the first oxide semiconductor layer, the second oxide semiconductor layer, and the first conductive layer, the first conductive layer includes: an annular first portion disposed from the outer peripheral surface of the first oxide semiconductor layer with a first width and surrounding the first oxide semiconductor layer; and an annular second portion disposed from the outer peripheral surface of the second oxide semiconductor layer with a first width and surrounding the second oxide semiconductor layer. A portion of a circle, ellipse, or oblong circumscribed by the first portion and a portion of a circle, ellipse, or oblong circumscribed by the second portion overlap. Simple Explanation of the Diagram

[0004] Figure 1 is a schematic circuit diagram showing a portion of the structure of the semiconductor device in the first embodiment. Figure 2 is a schematic cross-sectional view showing a portion of the structure of the semiconductor device. Figure 3 is a schematic cross-sectional view showing a portion of the structure of the semiconductor device. Figure 4 is a schematic perspective view showing a portion of the structure of the semiconductor device. Figure 5 is a schematic plan view showing a portion of the structure of the semiconductor device. Figure 6 is a schematic plan view showing a portion of the structure of the semiconductor device. Figure 7 is a schematic plan view showing a portion of the structure of the semiconductor device. Figure 8 is a schematic plan view showing a portion of the structure of the semiconductor device. Figure 9 is a schematic plan view showing a portion of the structure of the semiconductor device. Figure 10 is a schematic perspective view showing a portion of the structure of the semiconductor device. Figure 11 is a schematic cross-sectional view showing a portion of the structure of the semiconductor device. Figure 12 is a schematic cross-sectional view showing a portion of the structure of the semiconductor device. Figure 13 is a schematic plan view showing a portion of the structure of the semiconductor device. Figure 14 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor device. Figure 15 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 16 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 17 is a schematic cross-sectional view illustrating the manufacturing method. Figure 18 is a schematic plan view illustrating the manufacturing method. Figure 19 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 20 is a schematic cross-sectional view illustrating the manufacturing method. Figure 21 is a schematic plan view illustrating the manufacturing method. Figure 22 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 23 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 24 is a schematic plan view illustrating the manufacturing method. Figure 25 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 26 is a schematic cross-sectional view illustrating the manufacturing method. Figure 27 is a schematic plan view illustrating the manufacturing method. Figure 28 is a schematic cross-sectional view illustrating the manufacturing method. Figure 29 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 30 is a schematic cross-sectional view illustrating the manufacturing method. Figure 31 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 32 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 33 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 34 is a schematic plan view illustrating the manufacturing method. Figure 35 is a schematic cross-sectional view illustrating the manufacturing method. Figure 36 is a schematic cross-sectional view illustrating the manufacturing method. Figure 37 is a schematic plan view illustrating the manufacturing method. Figure 38 is a schematic cross-sectional view illustrating the manufacturing method. Figure 39 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 40 is a schematic plan view illustrating the manufacturing method. Figure 41 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 42 is a schematic cross-sectional view illustrating the manufacturing method. Figure 43 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 44 is a schematic cross-sectional view illustrating the manufacturing method. Figure 45 is a schematic cross-sectional view illustrating the manufacturing method. Figure 46 is a schematic cross-sectional view illustrating the manufacturing method. Figure 47 is a schematic cross-sectional view illustrating the manufacturing method. Figure 48 is a schematic cross-sectional view illustrating the manufacturing method. Figure 49 is a schematic cross-sectional view illustrating the manufacturing method. Figure 50 is a schematic cross-sectional view illustrating the manufacturing method. Figure 51 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 52 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 53 is a schematic cross-sectional view showing a portion of the structure of a modified example 1 of the semiconductor device in the first embodiment. Figure 54 is a schematic plan view showing a portion of the structure of the modified example. Figure 55 is a schematic cross-sectional view illustrating the manufacturing method of the modified example. Figure 56 is a schematic cross-sectional view illustrating the manufacturing method. Figure 57 is a schematic plan view showing a portion of the structure of a modified example 2 of the semiconductor device in the first embodiment. Figure 58 is a schematic perspective view showing a portion of the structure of the modified example. Figure 59 is a schematic cross-sectional view showing a portion of the structure of the modified example. Figure 60 is a schematic plan view showing a portion of the structure of a modified example 3 of the semiconductor device in the first embodiment. Figure 61 is a schematic perspective view showing a portion of the structure of the modified example. Figure 62 is a schematic cross-sectional view showing a portion of the structure of the modified example. Figure 63 is a schematic cross-sectional view showing a portion of the structure of the semiconductor device in the second embodiment. Figure 64 is a schematic cross-sectional view showing a portion of the structure of the semiconductor device. Figure 65 is a schematic cross-sectional view showing a portion of the structure of the semiconductor device. Figure 66 is a schematic cross-sectional view showing a portion of the structure of the semiconductor device. Figure 67 is a schematic cross-sectional view illustrating method 1 for manufacturing the semiconductor device. Figure 68 is a schematic cross-sectional view illustrating the manufacturing method. Figure 69 is a schematic plan view illustrating the manufacturing method. Figure 70 is a schematic cross-sectional view illustrating the manufacturing method. Figure 71 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 72 is a schematic plan view illustrating the manufacturing method. Figure 73 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 74 is a schematic cross-sectional view illustrating the manufacturing method. Figure 75 is a schematic plan view illustrating the manufacturing method. Figure 76 is a schematic cross-sectional view illustrating the manufacturing method. Figure 77 is a schematic cross-sectional view illustrating the manufacturing method. Figure 78 is a schematic plan view illustrating the manufacturing method. Figure 79 is a schematic cross-sectional view illustrating the manufacturing method. Figure 80 is a schematic cross-sectional view illustrating the manufacturing method. Figure 81 is a schematic plan view illustrating the manufacturing method. Figure 82 is a schematic cross-sectional view illustrating the manufacturing method. Figure 83 is a schematic cross-sectional view illustrating the manufacturing method. Figure 84 is a schematic plan view illustrating the manufacturing method. Figure 85 is a schematic cross-sectional view illustrating the manufacturing method. Figure 86 is a schematic cross-sectional view illustrating the manufacturing method. Figure 87 is a schematic plan view illustrating the manufacturing method. Figure 88 is a schematic cross-sectional view illustrating the manufacturing method. Figure 89 is a schematic cross-sectional view illustrating the manufacturing method. Figure 90 is a schematic plan view illustrating the manufacturing method. Figure 91 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 92 is a schematic cross-sectional view illustrating method 2 for manufacturing the semiconductor device. Figure 93 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 94 is a schematic plan view illustrating the manufacturing method. Figure 95 is a schematic cross-sectional view illustrating the manufacturing method. Figure 96 is a schematic cross-sectional view illustrating the manufacturing method. Figure 97 is a schematic plan view illustrating the manufacturing method. Figure 98 is a schematic cross-sectional view illustrating the manufacturing method. Figure 99 is a schematic cross-sectional view illustrating the manufacturing method. Figure 100 is a schematic plan view illustrating the manufacturing method. Figure 101 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 102 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 103 is a schematic plan view illustrating the manufacturing method. Figure 104 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 105 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 106 is a schematic plan view illustrating the manufacturing method. Figure 107 is a schematic cross-sectional view showing a portion of the structure of a modified example 1 of the semiconductor device in the second embodiment. Figure 108 is a schematic cross-sectional view showing a portion of the structure of the semiconductor device in the third embodiment. Figure 109 is a schematic plan view showing a portion of the structure of the semiconductor device. Figure 110 is a schematic perspective view showing a portion of the structure of the semiconductor device. Figure 111 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor device. Figure 112 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 113 is a schematic plan view illustrating the manufacturing method. Figure 114 is a schematic cross-sectional view illustrating the manufacturing method. Figure 115 is a schematic cross-sectional view illustrating the manufacturing method. Figure 116 is a schematic plan view illustrating the manufacturing method. Figure 117 is a schematic cross-sectional view illustrating the manufacturing method. Figure 118 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 119 is a schematic cross-sectional view illustrating the manufacturing method. Figure 120 is a schematic cross-sectional view illustrating the manufacturing method. Figure 121 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 122 is a schematic cross-sectional view illustrating the manufacturing method. Figure 123 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 124 is a schematic cross-sectional view illustrating the manufacturing method. Figure 125 is a schematic cross-sectional view illustrating the manufacturing method. Figure 126 is a schematic cross-sectional view illustrating the manufacturing method. Figure 127 is a schematic cross-sectional view illustrating the manufacturing method. Figure 128 is a schematic cross-sectional view illustrating the manufacturing method. Figure 129 is a schematic plan view illustrating the manufacturing method. Figure 130 is a schematic cross-sectional view illustrating the manufacturing method. Figure 131 is a schematic cross-sectional view illustrating the manufacturing method. Figure 132 is a schematic plan view for illustrating the manufacturing method. Figure 133 is a schematic cross-sectional view showing a portion of the structure of the semiconductor device in the third embodiment. Implementation

[0005] Next, the semiconductor device of each embodiment will be described in detail with reference to the drawings. Furthermore, the embodiments described below are merely examples and are not intended to limit the scope of the invention. Additionally, the drawings below are schematic diagrams, and sometimes parts of the structure are omitted for ease of explanation. Also, sometimes common parts in multiple embodiments are labeled with the same symbols and their descriptions are omitted.

[0006] Furthermore, in this specification, when the first structure and the second structure are described as "electrically connected," the first structure can be directly connected to the second structure, or the first structure can be connected to the second structure via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is still "electrically connected" to the third transistor.

[0007] In addition, in this specification, the specified direction parallel to the upper surface of the substrate is called the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and the direction perpendicular to the upper surface of the substrate is called the Z direction.

[0008] Furthermore, in this specification, the direction along a specified surface is sometimes referred to as the first direction, the direction along the specified surface and intersecting the first direction is referred to as the second direction, and the direction intersecting the specified surface is referred to as the third direction. These first, second, and third directions may correspond to any one of the X, Y, and Z directions, or they may not correspond to each other.

[0009] Furthermore, in this specification, the terms "upper" or "lower" are used with reference to the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction closer to the substrate along the Z direction is called "lower." Also, regarding a certain structure, when referring to a lower surface or lower end, it refers to the surface or end of the structure on the substrate side; when referring to an upper surface or upper end, it refers to the surface or end of the structure on the side opposite to the substrate. Additionally, surfaces intersecting the X or Y direction are referred to as side surfaces, outer peripheral surfaces, etc.

[0010] [First Implementation Form] [Circuit Structure] Figure 1 is a schematic circuit diagram showing a portion of the structure of a semiconductor device according to a first embodiment. The semiconductor device according to the first embodiment includes, for example, a memory cell array (MCA) and peripheral circuitry (PC) as shown in Figure 1.

[0011] The memory cell array (MCA) includes: multiple bit lines (BL), multiple word lines (WL), multiple board lines (PL), and multiple memory cells (MC) connected to these bit lines (BL), word lines (WL), and board lines (PL). Multiple memory cells (MC) connected to a single word line (WL) are each connected to a different bit line (BL). Furthermore, multiple memory cells (MC) connected to a single bit line (BL) are each connected to a different word line (WL).

[0012] The memory cell MC includes a select transistor ST and a capacitor Cap, which are connected in series between the bit line BL and the plate line PL, respectively.

[0013] The selector transistor ST is a field-effect transistor comprising a semiconductor layer that functions as a channel region, a gate insulating layer, and a gate electrode. The word lines WL are connected to the gate electrode of the selector transistor ST.

[0014] A capacitor (Cap) is a capacitor that includes a pair of electrodes and an insulating film. A capacitor (Cap) includes a memory cell portion.

[0015] Peripheral circuits PC may include, for example, a voltage generation circuit that generates an operating voltage and outputs it to a voltage supply line, a decoding circuit that connects the desired voltage supply line to the wiring (bit line BL, word line WL, and board line PL) within the memory cell array MCA, and a sensing amplifier circuit that detects the current or voltage of the bit line BL.

[0016] Figure 2 is a schematic cross-sectional view showing a portion of the structure of a semiconductor device. As shown in Figure 2, the semiconductor device of the first embodiment includes: a substrate Sub, a transistor layer LTr extending from the substrate Sub along the Z direction, a wiring layer LML disposed above the transistor layer LTr, a wiring layer LUL disposed above the wiring layer LML, a capacitor layer LCP disposed below the transistor layer LTr, a board line layer LPT disposed below the capacitor layer LCP, and a peripheral circuit layer LPC disposed on the substrate Sub below the board line layer LPT. The substrate Sub, for example, contains P-type silicon (Si) containing P-type impurities such as boron (B).

[0017] Additionally, as shown in Figure 2, the semiconductor device in the first embodiment includes a memory region RMC and a peripheral region RPC disposed on a substrate Sub.

[0018] [Structure of the Memory Region RMC] Next, the structure of the memory region RMC will be described with reference to Figures 2 to 8. Figures 3 to 8 are schematic cross-sectional views, plan views, and perspective views showing a portion of the structure of the semiconductor device according to the first embodiment. In Figure 3, a portion of the structure of the memory region RMC is shown. In Figure 4, the structure of the transistor layer LTR and the connection portion for the transistor layer LTR are shown. Furthermore, in Figure 4, for ease of explanation, a portion of the insulating layer 140 disposed above and below the conductive layer 150 is omitted. Figure 5 is a schematic plan view showing the structure shown in Figure 3 cut along line A-A' and viewed in the direction of the arrow. Figure 6 is a schematic plan view showing the structure shown in Figure 3 cut along line B-B' and viewed in the direction of the arrow. Figure 7 is a schematic plan view showing the structure shown in Figure 3 cut along line C-C' and viewed in the direction of the arrow. Furthermore, in Figure 7, a portion of the structure shown in Figure 6 is indicated by dashed lines. Figure 8 is a schematic plan view showing an enlarged portion of the structure shown in Figure 5.

[0019] For example, as shown in FIG3, the transistor layer LTR of the memory region RMC includes: an insulating layer 111 disposed on the upper surface of the capacitor layer LCP, and an insulating layer 113 disposed above the insulating layer 111. Additionally, as shown in FIG5, the transistor layer LTR of the memory region RMC includes a plurality of insulating layers 112 and a plurality of conductive layers 150 disposed between the insulating layers 111 and 113 and alternately arranged in the Y direction. Furthermore, as shown in FIGS. 4 and 5, the transistor layer LTR of the memory region RMC includes: a plurality of semiconductor layers 130 arranged in the X direction corresponding to the conductive layers 150 extending in the X direction, and insulating layers 140 disposed between the semiconductor layers 130 and the conductive layers 150.

[0020] Furthermore, for example, as shown in FIG5, the positions of the plurality of semiconductor layers 130 arranged corresponding to one of the two conductive layers 150 adjacent in the Y direction and the plurality of semiconductor layers 130 arranged corresponding to the other conductive layer 150 in the X direction may also be different.

[0021] Additionally, as shown in Figure 5, the direction in which the semiconductor layers 130 are arranged corresponding to different conductive layers 150 is sometimes referred to as the Y2 direction (Figure 5). The Y2 direction is a direction different from the X direction. The Y2 direction may be different from or the same as the Y direction. Additionally, the direction intersecting the Y2 direction and the Z direction is sometimes referred to as the X2 direction (Figure 5).

[0022] Insulating layers 111, 112, and 113 may contain, for example, silicon oxide (SiO2).

[0023] Semiconductor layer 130 extends, for example, along the Z direction and has a generally cylindrical shape. Semiconductor layer 130 is an oxide semiconductor and functions, for example, as a channel region of a selective transistor ST (FIG. 1). Semiconductor layer 130 contains, for example, at least one element selected from the group of metal elements GP1, and oxygen (O).

[0024] The metal group GP1 includes: indium (In), gallium (Ga), aluminum (Al), zinc (Zn), tin (Sn), titanium (Ti), tungsten (W), and molybdenum (Mo).

[0025] Semiconductor layer 130 may include, for example, indium (In), zinc (Zn), and oxygen (O), or indium (In), gallium (Ga), and oxygen (O), or gallium (Ga), zinc (Zn), and oxygen (O), or indium (In), gallium (Ga), zinc (Zn), and oxygen (O), or indium (In), gallium (Ga), tin (Sn), and oxygen (O), or indium (In), tungsten (W), and oxygen (O).

[0026] For example, as shown in Figure 5, in an XY cross-section including multiple semiconductor layers 130 and multiple conductive layers 150, the closest distance between the outer peripheral surfaces of one of the two semiconductor layers 130 arranged in the X direction and the outer peripheral surface of the other semiconductor layer 130 is the width DX10. Similarly, the closest distance between the outer peripheral surfaces of one of the two semiconductor layers 130 arranged in the Y2 direction and the outer peripheral surface of the other semiconductor layer 130 is the width DT10. The width DT10 is larger than the width DX10.

[0027] The insulating layer 140 extends, for example, along the Z-direction and has a generally cylindrical shape. The insulating layer 140 is disposed, for example, on at least a portion of the outer peripheral surface of the semiconductor layer 130. The insulating layer 140 functions, for example, as the gate insulating layer of a transistor ST (FIG. 1). The insulating layer 140 may comprise, for example, silicon oxide (SiO2), silicon nitride (SiN), or other insulating layers with high dielectric constants. The insulating layer 140 may also be a multilayer structure comprising two or more insulating layers including silicon oxide (SiO2), silicon nitride (SiN), and other insulating layers with high dielectric constants.

[0028] For example, as shown in Figures 3 and 4, the conductive layer 150 faces a portion of the outer peripheral surface of the semiconductor layer 130. Regarding the conductive layer 150, for example, as shown in Figure 4, a generally cylindrical portion surrounding a portion of the semiconductor layer 130 and the insulating layer 140 is connected in the X direction. At least one side surface S11 (Figures 4 and 8) of the conductive layer 150 in the Y direction is provided without a planar portion, but rather with curved surfaces connected.

[0029] For example, in the XY cross-section shown in FIG8, which includes two adjacent semiconductor layers 130 in the X direction, the conductive layer 150 includes annular portions PT11 disposed from the outer peripheral surface of the semiconductor layer 130 with a width DW11 and surrounding the semiconductor layer 130. The width DW11 is, for example, equivalent to the film thickness of the insulating layer 140. In the XY cross-section shown in FIG8, a portion of the external tangent line OT that is externally tangent to one portion of PT11 and a portion of the external tangent line OT that is externally tangent to the other portion of PT11 overlap. The external tangent line OT is, for example, a circle, an ellipse, or an oblong.

[0030] Furthermore, in the XY cross-section shown in Figure 8, a portion of the PT11 arranged in the X direction overlaps. In Figures 5 and 8, the overlapping portion of the PT11 arranged in the X direction is illustrated as region R10. Moreover, the portion of the outer peripheral surface of the PT11, excluding the portion contained in region R10, is in contact with the insulating layer 112.

[0031] The conductive layer 150 functions, for example, as the gate electrode of a plurality of selective transistors ST arranged in the X direction, and as the word line WL (FIG. 1) of a memory cell array MCA. The conductive layer 150 may be, for example, tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), titanium nitride (TiN), etc., or may contain a multilayer structure comprising one or more of tungsten (W), molybdenum (Mo), ruthenium (Ru), and cobalt (Co) and titanium nitride (TiN).

[0032] For example, as shown in Figure 3, the wiring layer LML of the memory region RMC includes: an insertion layer LLP disposed on the upper surface of the transistor layer LTR, and a bit line layer LBL disposed on the upper surface of the insertion layer LLP.

[0033] For example, as shown in Figures 3 and 6, the plug layer LLP, at the position corresponding to the semiconductor layer 130, includes conductive layers 170, 171, and 172 sequentially disposed on the upper surface of the transistor layer LTR. Conductive layers 170, 171, and 172 are electrically connected to the semiconductor layer 130. Furthermore, hereinafter, the structure including conductive layers 170, 171, and 172 is sometimes referred to as the plug LP. Moreover, the structure of the plug LP can be appropriately adjusted; for example, any one of the conductive layers 170, 171, and 172 may be omitted.

[0034] For example, as shown in Figures 3 and 6, multiple plugs LP extend along the Z direction and are arranged in the X and Y directions. For example, the plugs LP function as the source electrodes of the selective transistor ST. An insulating layer 173, such as silicon oxide (SiO2), is provided between the multiple plugs LP.

[0035] The conductive layer 170 may contain, for example, at least one element selected from the group GP2 of metallic elements, and oxygen (O). The group GP2 of metallic elements includes indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), manganese (Mn), tin (Sn), niobium (Nb), titanium (Ti), tantalum (Ta), calcium (Ca), tungsten (W), and molybdenum (Mo). The conductive layer 170 may also be, for example, indium tin oxide (InSnO). In addition, the conductive layer 170 may also contain a laminated film containing at least one of these materials.

[0036] The conductive layer 171 may include, for example, titanium nitride (TiN) or titanium oxide (TiO). Alternatively, the conductive layer 171 may also contain a laminated film containing at least one of these materials.

[0037] The conductive layer 172 may contain, for example, tungsten (W), aluminum (Al), molybdenum (Mo), etc. Alternatively, the conductive layer 172 may also contain a laminated film containing at least one of these materials.

[0038] For example, as shown in Figures 3 and 7, the bit line layer LBL includes conductive layers 182 and 184 sequentially disposed on a portion of the upper surface of the plug layer LLP at the position corresponding to conductive layer 172. Conductive layers 182 and 184 are electrically connected to a plurality of conductive layers 172 arranged in the Y direction corresponding to conductive layers 182 and 184 (Figure 7). Furthermore, the structure of conductive layers 182 and 184 can be appropriately adjusted; for example, either conductive layer 182 or conductive layer 184 may be omitted.

[0039] For example, as shown in Figures 3 and 7, multiple structures including conductive layers 182 and 184 extend along the Y direction and are arranged in the X direction. Conductive layers 182 and 184 function, for example, as bit lines BL (Figure 1) of a memory cell array (MCA). An insulating layer 183, such as silicon oxide (SiO2), is disposed between these structures arranged in the X direction.

[0040] The conductive layer 182 may contain metallic elements such as tungsten (W), aluminum (Al), and molybdenum (Mo).

[0041] The conductive layer 184 may contain, for example, titanium nitride (TiN).

[0042] For example, as shown in Figures 2 and 3, the capacitor layer LCP of the memory region RMC includes: a plurality of conductive layers 120 disposed corresponding to and connected to the lower ends of the plurality of semiconductor layers 130, a plurality of conductive layers 201 disposed corresponding to and connected to the lower ends of the plurality of conductive layers 120, and a plurality of conductive layers 121 disposed on the outer peripheral surfaces of the plurality of conductive layers 120 and on the outer peripheral surfaces and lower surfaces of the plurality of conductive layers 201. Furthermore, the capacitor layer LCP includes: an insulating layer 202 disposed on the outer peripheral surfaces and lower surfaces of the conductive layers 121, and a conductive layer 203 disposed on the outer peripheral surfaces and lower surfaces of the insulating layers 202 (Figure 3). Moreover, in the following description, the structure of the capacitor Cap (Figure 1) disposed in the capacitor layer LCP of these memory regions RMCs is sometimes referred to as "capacitor structure CP10". The capacitor structure CP10 includes, for example, a conductive layer 120, a conductive layer 121, a conductive layer 201, an insulating layer 202, and a conductive layer 203. An insulating layer 100, such as silicon oxide (SiO2), is disposed between the plurality of capacitor structures CP10.

[0043] The conductive layer 120 functions, for example, as the drain electrode of the selective transistor ST (FIG. 1) and as part of one of the electrodes of the capacitor Cap (FIG. 1). The conductive layer 120 is generally circular in the XY cross-section, but may also have a plug shape. The conductive layer 120 may contain, for example, the same material as the conductive layer 170. The conductive layer 120 may also be, for example, indium tin oxide (InSnO).

[0044] The conductive layer 121 functions as part of one of the electrodes of a capacitor Cap (FIG. 1). The conductive layer 121 may also be, for example, titanium nitride (TiN).

[0045] The conductive layer 201 functions as part of one of the electrodes of the capacitor Cap (Figure 1). The conductive layer 201 may include, for example, a multilayer structure of titanium nitride (TiN) and tungsten (W).

[0046] The insulating layer 202 functions as an insulating layer between the electrodes of the capacitor Cap (FIG. 1). The insulating layer 202 may contain, for example, aluminum oxide (AlO). The insulating layer 202 may also be, for example, silicon oxide (SiO2) or other insulating metal oxides.

[0047] The conductive layer 203 functions as another electrode in a capacitor (Figure 1), for example. The conductive layer 203 may include, for example, a multilayer structure of titanium nitride (TiN) and tungsten (W).

[0048] For example, as shown in Figure 2, the board line layer LPT of the memory region RMC includes a conductive layer 204 disposed on the lower surface of the capacitor layer LCP. The conductive layer 204 is electrically connected to multiple conductive layers 203. The conductive layer 204 functions, for example, as a board line PL (Figure 1). The conductive layer 204 may include, for example, a multilayer structure of tungsten (W) or titanium nitride (TiN) and tungsten (W).

[0049] [Structure of RPC in the surrounding area] Next, referring to Figures 2 and 9-13, the structure of the peripheral region RPC (Figure 2) will be described. Figures 9-13 are schematic cross-sectional views, plan views, and perspective views showing a portion of the structure of the semiconductor device according to the first embodiment. Figure 9 is a schematic plan view showing the structure shown in Figure 2 cut along line D-D' and viewed in the direction of the arrow. Furthermore, in Figure 9, to indicate positional relationships, the conductive layer 150, which is not shown in the cross-section, and a portion of the electrodes C1_WL and C1_WLP described later are indicated by dashed lines. Figure 10 shows the structure of the memory region RMC and the peripheral region RPC. Figure 11 shows a portion of the structure of region RPC1. Figure 12 shows a portion of the structure of region RPC2. Figure 13 shows the structure of the end of the conductive layer 150.

[0050] For example, as shown in Figure 2, the board line layer LPT of the peripheral region RPC includes multiple conductive layers 205. The conductive layers 205 may, for example, contain the same material as the conductive layer 204.

[0051] For example, as shown in Figure 2, the peripheral circuit layer (LPC) of the peripheral region RPC includes: a plurality of transistors TrP1 disposed on the substrate Sub, and a plurality of electrodes 210 connected to the plurality of transistors TrP1. The plurality of electrodes 210 are connected to the conductive layer 205 at their upper ends, for example. The plurality of electrodes 210 are connected to the source region, drain region, gate electrode, etc., of the plurality of transistors TrP1 at their lower ends, for example. The plurality of transistors TrP1 constitute the peripheral circuit PC (Figure 1).

[0052] The wiring layer LML of the peripheral area RPC includes: a conductive layer BP disposed on the same layer as the bit line BL, and an electrode 192 connected to the upper surface of the conductive layer BP.

[0053] The conductive layer BP (FIG. 12) includes, for example, conductive layers 182a and 184a containing the same material as conductive layers 182 and 184.

[0054] For example, as shown in Figure 2, electrode 192 extends along the Z direction and has a generally cylindrical shape. Electrode 192 may, for example, include tungsten (W), or a multilayer structure of titanium nitride (TiN) and tungsten (W).

[0055] For example, as shown in Figure 2, the wiring layer LUL includes: wiring 301 disposed on the upper surface of the wiring layer LML, wiring 302 disposed on the upper surface of wiring 301 in connection with wiring 301, and wiring 303 disposed on the upper surface of wiring 302 in connection with wiring 302. An insulating layer 304, such as silicon oxide (SiO2), is disposed between wiring 301, wiring 302, and wiring 303.

[0056] Wiring 301, wiring 302, and wiring 303 function, for example, as wiring to supply voltage and current to peripheral circuits PC and bit lines BL. Wiring 301, wiring 302, and wiring 303 may include, for example, copper (Cu), tungsten (W), aluminum (Al), etc.

[0057] For example, as shown in Figures 2 and 9, the capacitor layer LCP of the peripheral region RPC includes multiple through electrodes CC_WL and multiple through electrodes CC_WLP extending along the Z direction. Furthermore, the region in the peripheral region RPC with through electrodes CC_WL is sometimes referred to as region RPC1, and the region with through electrodes CC_WLP is referred to as region RPC2. Region RPC1 is located between region RPC2 and the memory region RMC (Figure 10).

[0058] For example, as shown in Figure 2, the through electrode CC_WL is connected at its upper end to the electrode C1_WL of the transistor layer LTR (described later), and at its lower end to a portion of the plurality of conductive layers 205 in the plate wire layer LPT (Figure 2). For example, as shown in Figures 10 and 11, the through electrode CC_WL includes a conductive layer 220 such as tungsten (W) and a conductive layer 221 such as titanium nitride (TiN).

[0059] For example, as shown in Figure 2, the through electrode CC_WLP is connected at its upper end to the electrode C1_WLP of the transistor layer LTR (described later), and at its lower end to a portion of a plurality of conductive layers 205 in the plate wire layer LPT (Figure 2). For example, as shown in Figures 10 and 12, the through electrode CC_WLP includes conductive layers 220 and 221.

[0060] [Structure of Region RPC1] The transistor layer LTr (FIG. 11) of region RPC1 includes insulating layers 111, 112, and 113, and a portion of conductive layer 150, which are identical to those of the transistor layer LTr (FIG. 3) of memory region RMC. Furthermore, one end of conductive layer 150 in the X direction is provided in the transistor layer LTr of region RPC1. Additionally, the transistor layer LTr of region RPC1 includes: semiconductor layers 130D1 and 130D2 arranged in the X direction corresponding to conductive layer 150; insulating layers 140 disposed between semiconductor layers 130D1 and 130D2 and conductive layer 150; and an electrode C1_WL disposed between conductive layer 150 and through electrode CC_WL.

[0061] Semiconductor layers 130D1 and 130D2 are configured in essentially the same manner as semiconductor layer 130, contain the same material, and are arranged in the X direction as semiconductor layer 130. However, semiconductor layers 130D1 and 130D2 are configured as virtual structures and do not function as channel regions for the selected transistor ST (Figure 1).

[0062] Electrode C1_WL surrounds a portion of the side surface and the lower surface of semiconductor layer 130D2. For example, as shown in Figures 10 and 11, electrode C1_WL includes: a conductive layer 150a containing the same material as conductive layer 150, and a conductive layer 152 such as titanium nitride (TiN). Conductive layer 150a may also be formed continuously with conductive layer 150. Conductive layer 150 and through electrode C1_WL are electrically connected via electrode C1_WL.

[0063] Figure 13 shows the semiconductor layer 130D1, located at its outermost end in the X direction within region RPC1, and the X-direction end of the conductive layer 150 facing the semiconductor layer 130D1. The conductive layer 150 includes, for example, an annular portion PT12 disposed at a distance of width DW11 from the outer peripheral surface of the semiconductor layer 130D1 in the XY cross-section shown in Figure 13, surrounding the semiconductor layer 130D1. The portion PT12 is at least a portion of the X-direction end of the conductive layer 150. A portion of the outer peripheral surface of the portion PT12 is in contact with the insulating layer 112.

[0064] [Structure of Region RPC2] The transistor layer LTR of region RPC2 (Figure 12) includes: electrode WLP and electrode C1_WLP.

[0065] The electrode WLP is connected to the conductive layer BP at its upper end and to the electrode C1_WLP at its lower end. The electrode WLP includes a conductive layer 153 of tungsten (W) and a conductive layer 154 of titanium nitride (TiN).

[0066] Electrode C1_WLP is disposed between electrode WLP and through electrode CC_WLP. Electrode WLP and through electrode CC_WLP are electrically connected via electrode C1_WLP. Electrode C1_WLP includes conductive layer 150a and conductive layer 152.

[0067] [Manufacturing method of the first embodiment] Next, the manufacturing method of the semiconductor device according to this embodiment will be described with reference to Figures 14 to 52. Figures 14 to 52 are schematic cross-sectional and plan views for illustrating the manufacturing method of the semiconductor device according to the first embodiment.

[0068] Furthermore, Figures 14, 16, 19, 22, 25, 28, 30, 32, 35, 38, 41, 43, 45, 49, and 51 are schematic cross-sectional views of the portions corresponding to those in Figure 11. Figures 15, 17, 20, 23, 26, 29, 31, 33, 36, 39, 42, 44, 46, 50, and 52 are schematic cross-sectional views of the portions observed along line E-E', cutting through the structure shown in Figure 5 and following the direction of the arrows. Figures 18, 24, 27, 34, 37, and 40 are plan views showing the same portions as those in Figure 5. Figure 21 is a schematic plan view illustrating the method of forming the structures shown in Figures 19 and 20. Figures 47 and 48 are schematic cross-sectional views of the portions corresponding to those in Figure 12. Furthermore, the following diagrams illustrating the manufacturing method are schematic diagrams, and some structures may be omitted for ease of explanation.

[0069] In this manufacturing method, a peripheral circuit layer LPC (Fig. 2), a line layer LPT (Fig. 2), and a capacitor layer LCP (Fig. 2) including through electrodes CC_WL, through electrodes CC_WLP, and a conductive layer 120 (Fig. 14) are formed above the substrate Sub (Fig. 1). Additionally, as shown in Figs. 14 and 15, an insulating layer 111 is formed on the upper surface of the capacitor layer LCP. Furthermore, an opening TH_150 is formed in the portion of the insulating layer 111 corresponding to the electrodes CC_WL and CC_WLP, and a conductive layer 152 is formed inside the opening TH_150. This step is performed, for example, by chemical vapor deposition (CVD) and reactive ion etching (RIE).

[0070] Next, for example, as shown in Figures 16-18, conductive layers 150B' and 150a, containing the same material as conductive layer 150, are formed on the upper surface of the structure shown in Figures 14 and 15 and inside the opening TH_150. Additionally, an insulating layer 230, such as silicon oxide (SiO2), is formed on the upper surface of conductive layer 150B'. This step is performed, for example, by CVD and RIE.

[0071] Next, for example, as shown in Figures 19 and 20, a masking material HM10 is formed on the upper surface of the structure shown in Figures 16 and 17 by photolithography or the like. The masking material HM10 may also include insulating layers such as silicon nitride (SiN) and silicon oxide (SiO2), or materials such as photoresist.

[0072] Furthermore, Figure 21 shows an example of the shape of the photoresist RM10 used to form the mask material HM10 by photolithography. The photoresist RM10 includes: a first portion extending in the X direction and having a width DRY1 in the Y direction, and a second portion extending in a direction that differs from the extension direction of the first portion by an angle AG1 and having a width DRX2 in a direction orthogonal to the extension direction. By appropriately adjusting the width DRY1, the width DRX2, and the angle AG1, the shape, size, and arrangement spacing of TH_130 and TH_130a formed in the steps shown in Figures 22 to 24 described later can be set to the desired values.

[0073] Next, for example, as shown in Figures 22-24, openings TH_130 and TH_130a are formed. Opening TH_130 extends along the Z-direction, penetrating the insulating layer 230, conductive layer 150B', and insulating layer 111, and exposing the conductive layer 120. Opening TH_130a extends along the Z-direction, penetrating the insulating layer 230, conductive layer 150B', and insulating layer 111, and exposing electrodes C1_WL, etc. Through this step, a conductive layer 150B containing the same material as conductive layer 150 is formed. This step is performed, for example, by means of a RIE (Reinforcing Electrode Interface).

[0074] Next, for example, as shown in Figures 25-27, a sacrificial layer SC_130, such as amorphous silicon (αSi), is formed inside the openings TH_130 and TH_130a. This step is performed, for example, by CVD.

[0075] Next, for example, as shown in Figures 28 and 29, the insulating layer 230 is removed, exposing the upper surface of the conductive layer 150B and the upper end of the sacrificial layer SC_130. This step is performed, for example, by wet etching.

[0076] Next, for example, as shown in Figures 30 and 31, an insulating layer MS_113, such as silicon oxide (SiO2), is formed on the upper surface of the structure shown in Figures 28 and 29. Through this step, the spaces between the sacrificial layers SC_130 arranged in the X direction are closed by the insulating layer MS_113 (Figure 30). On the other hand, the spaces between the sacrificial layers SC_130 arranged in the Y2 direction are not closed by the insulating layer MS_113, and an opening TH_112B is formed between the sacrificial layers SC_130 arranged in the Y2 direction (Figure 31). This step is performed, for example, by CVD, atomic layer deposition (ALD), etc.

[0077] Next, for example, as shown in Figures 32-34, the insulating layer MS_113 is etched back to form the insulating layer 113'. In this step, the portion of the insulating layer MS_113 below the opening TH_112B is removed, and then a portion of the conductive layer 150B below the opening TH_112B is removed, forming the opening TH_112 in the portion between the sacrificial layers SC_130 arranged in the Y2 direction (Figure 33). The opening TH_112 extends along the X and Z directions, penetrating the insulating layer 113' and the conductive layer 150B, exposing the insulating layer 111. Through this step, a conductive layer 150 truncated in the Y direction is formed (Figure 34). This step is performed, for example, by means of a RIE (Reinforcing Interchange).

[0078] Next, for example, as shown in Figures 36 and 37, an insulating layer 112 is formed at the opening TH_112. This step is performed, for example, by CVD. Additionally, for example, as shown in Figures 35-37, a portion of the upper surface of the insulating layer 113' and the sacrificial layer SC_130 are removed to form openings TH_130_1 and TH_130_1a. This step is performed, for example, by chemical mechanical planarization (CMP) or wet etching.

[0079] Next, for example, as shown in Figures 38-40, an insulating layer 140 is formed inside the openings TH_130_1 and TH_130_1a. Then, a semiconductor layer 130 is formed inside the opening TH_130_1, and semiconductor layers 130D1 and 130D2 are formed inside the opening TH_130_1a. In this step, the insulating layer 140 is formed by removing the portion of the insulating layer formed on the bottom surface of the openings TH_130_1 and TH_130_1a after forming an insulating layer containing the same material as the insulating layer on the inner and bottom surfaces of the openings TH_130_1 and TH_130_1a. The semiconductor layers 130, 130D1, and 130D2 are connected to the inner surfaces of the insulating layer 140 and are formed in a manner that embeds them into the openings TH_130_1 and TH_130_1a. This step is performed, for example, by ALD, CVD, RIE, CMP, etc.

[0080] Next, for example, as shown in Figures 41 and 42, conductive layers 170'', 171'', and 172'' are sequentially formed on the upper surface of the structure shown in Figures 38 and 39. Conductive layers 170'', 171'', and 172'', for example, contain the same material as conductive layers 170, 171, and 172, respectively. This step is performed, for example, by CVD.

[0081] Next, for example, as shown in Figures 43 and 44, a masking material is formed at positions corresponding to conductive layers 170, 171, and 172 using photolithography or the like. The portions not covered by the masking material are then removed, thereby forming conductive layers 170', 171', and 172'. This step is performed, for example, by using a resonant optical imager (RIE).

[0082] Next, for example, as shown in Figures 45 and 46, an insulating layer 173' such as silicon oxide (SiO2) is formed on the upper surface of the structure shown in Figures 43 and 44. This step is performed, for example, by CVD.

[0083] Next, for example, as shown in FIG47, an opening TH_WLP is formed at a position corresponding to the electrode WLP. The opening TH_WLP extends along the Z direction, penetrates the insulating layer 173' and the insulating layer 112, and exposes the electrode C1_WLP. This step is performed, for example, by means of a RIE or the like.

[0084] Next, for example, as shown in FIG48, the same material as conductive layer 154 and conductive layer 153 is sequentially formed inside the opening TH_WLP. In addition, the upper surface of the structure shown in FIG48 is planarized until conductive layer 172' is exposed, thereby forming conductive layer 154, conductive layer 153 and insulating layer 173. This step is performed, for example, by CVD, CMP or the like.

[0085] Next, for example, as shown in Figures 49 and 50, conductive layers 182' and 184' are formed on the upper surfaces of insulating layer 173 and conductive layer 172'. This step is performed, for example, by CVD.

[0086] Next, as shown in Figures 51 and 52, conductive layer 182, conductive layer 184, and insulating layer 183 are formed. This step is performed, for example, by forming a masking material at positions corresponding to conductive layers 182 and 184 using photolithography, and removing the portions not covered by the masking material. Through this step, a portion of conductive layers 170', 171', and 172' is simultaneously removed to form conductive layers 170, 171, and 172. This step is performed, for example, using a resonant electronic material (RIE).

[0087] Next, a wiring layer LUL (Fig. 2) is formed on the upper surface of the structure shown in FIG. 51 and FIG. 52, thereby manufacturing a semiconductor device of the first embodiment.

[0088] [Effect] In the semiconductor device of this embodiment, as shown in FIG5, the closest distance between the outer peripheral surfaces of the two semiconductor layers 130 arranged in the Y2 direction, i.e., the width DT10, is greater than the closest distance between the outer peripheral surfaces of the two semiconductor layers 130 arranged in the X direction, i.e., the width DX10.

[0089] In this structure, during the steps described with reference to Figures 30-34, the sacrificial layers SC_130 arranged in the Y2 direction corresponding to the location where the semiconductor layer 130 is formed are not blocked by the insulating layer MS_113 (Figure 31). Therefore, the conductive layer 150 (Figures 32-34) formed by etching back the insulating layer MS_113 is connected in the X direction and truncated in the Y direction. In this step, the conductive layer 150 can be self-aligned and formed along the sacrificial layers SC_130 arranged in the X direction.

[0090] In the semiconductor device of this embodiment, even when the semiconductor layer 130, which functions as a channel for the select transistor ST (FIG. 1), is further configured with a fine shape and high density, the conductive layer 150, which functions as a word line WL, can be precisely aligned with the formation position of the semiconductor layer 130, allowing for high-precision processing. This enables the manufacture of a select transistor ST (FIG. 1) with high density and excellent transistor characteristics, as well as a fine word line WL. Furthermore, the fine photolithography step for processing the conductive layer 150 is eliminated, thereby reducing manufacturing costs.

[0091] [Variation 1 of the first embodiment] Next, a modification 1 of the semiconductor device according to the first embodiment will be described with reference to FIGS. 53 and 54. FIGS. 53 and 54 are schematic cross-sectional and plan views showing a portion of the structure of the semiconductor device of this modification. Furthermore, FIG. 53 shows the portion corresponding to FIG. 11. FIG. 54 shows the structure of the end of the conductive layer 150.

[0092] In the semiconductor device of this modified example (FIG. 53), insulating layers 132D1 and 132D2 are provided instead of semiconductor layers 130D1 and 130D2 (FIG. 11).

[0093] Insulating layers 132D1 and 132D2 extend, for example, along the Z direction and have a generally cylindrical shape. A portion of insulating layers 132D1 and 132D2 faces the conductive layer 150. Insulating layers 132D1 and 132D2 contain the same materials as insulating layer 173, such as silicon oxide (SiO2). Insulating layers 132D1 and 132D2 may also be disposed continuously with insulating layer 173.

[0094] In addition, in this modified example, the electrode C1_WL is disposed in such a way that it surrounds a portion of the side surface of the insulating layer 132D2 and the lower surface of the insulating layer 132D2.

[0095] Figure 54 shows the outermost end of the insulating layer 132D1 in the X direction and the end of the conductive layer 150 in the X direction. The conductive layer 150 includes, for example, an annular portion PT13 that extends a width DW11 away from the outer peripheral surface of the insulating layer 132D1 in the XY cross-section shown in Figure 54 and surrounds the insulating layer 132D1. The portion PT13 is at least a part of the end of the conductive layer 150 in the X direction. Furthermore, a portion of the outer peripheral surface of the portion PT13 is in contact with the insulating layer 112.

[0096] [Manufacturing method of Modification 1 of the first embodiment] Next, the manufacturing method of the semiconductor device of this modified example will be described with reference to FIGS. 55 and 56. FIGS. 55 and 56 are schematic cross-sectional views illustrating the manufacturing method of the semiconductor device of Modified Example 1 of the first embodiment. Furthermore, FIGS. 55 and 56 are schematic cross-sectional views corresponding to the portions of FIG. 53.

[0097] In the manufacture of the semiconductor device of this modified example, the same steps as those in the first embodiment are performed up to the steps described with reference to Figures 14 to 44.

[0098] Next, for example, as shown in FIG55, semiconductor layers 130D1 and 130D2 are removed to form an opening TH_130_1a. This step is performed, for example, by wet etching.

[0099] Next, for example, as shown in FIG56, an insulating layer such as silicon oxide (SiO2) is formed on the upper surface of the structure shown in FIG55, thereby forming insulating layers 132D1, 132D2, and 173' inside the opening TH_130_1a. This step is performed, for example, by CVD.

[0100] Next, the steps described with reference to Figures 47 onwards will be performed, for example, in the same manner as the manufacturing method of the first embodiment.

[0101] [Variation 2 of the first embodiment] Next, a modification 2 of the semiconductor device according to the first embodiment will be described with reference to Figures 57 to 59. Figures 57 to 59 are schematic plan views, perspective views, and cross-sectional views showing a portion of the structure of the semiconductor device of this modification. Furthermore, in Figures 57, 58, and 59, the portions corresponding to Figures 9, 10, and 12 are shown, respectively.

[0102] In this modified example, the transistor layer LTR (Fig. 59) of region RPC2 is not provided with electrode WLP (Fig. 12), but instead, electrode WLP2 and conductive layer 150_1a (Fig. 59) are provided therein.

[0103] For example, as shown in Figure 59, electrode WLP2 is connected to conductive layer BP at its upper end and electrically connected to electrode C1_WLP at its lower end. A portion of the side surface and the lower surface of electrode WLP2 may be surrounded by electrode C1_WLP. Electrode WLP2 includes the same conductive layer 153 and conductive layer 154 as electrode WLP (Figure 12).

[0104] For example, as shown in Figures 58 and 59, conductive layer 150_1a is disposed in the same layer as conductive layer 150. Conductive layer 150_1a may also contain the same material as conductive layer 150 and be formed by the same steps as conductive layer 150. For example, as shown in Figures 58 and 59, conductive layer 150_1a may also be disposed in a manner that surrounds a portion of electrode WLP2.

[0105] Regarding the formation of the conductive layer 150_1a, it can be performed as follows, for example. For instance, in the steps corresponding to Figures 22-24, an opening identical to the opening TH_130a is also formed on the electrode C1_WLP. Furthermore, in the steps corresponding to Figures 25-29, a sacrificial layer identical to the sacrificial layer SC_130 is also formed on the electrode C1_WLP. Therefore, in the steps corresponding to Figures 30-34, a conductive layer 150_1a comprising the same material as the conductive layer 150 is also formed on the electrode C1_WLP.

[0106] [Modification 3 of the first embodiment] Next, with reference to FIGS. 60 to 62, a modification 3 of the semiconductor device according to the first embodiment will be described. FIGS. 60 to 62 are schematic plan views, perspective views, and cross-sectional views showing a portion of the structure of the semiconductor device of this modification. Furthermore, in FIGS. 60, 61, and 62, the portions corresponding to FIGS. 9, 10, and 12 are shown, respectively.

[0107] In this modified example, the transistor layer LTr (Fig. 62) of region RPC2 does not have an electrode WLP (Fig. 12). Instead, the same electrode WLP2 as in modified example 2 (Fig. 59) is provided there, and then an insulating layer 132D3 and a conductive layer 150_1b (Fig. 62) are provided. In addition, in this modified example, as shown in Fig. 60, an insulating layer 101 such as silicon oxide (SiO2) may also be provided between region RPC1 and region RPC2.

[0108] For example, as shown in Figures 61 and 62, conductive layer 150_1b is disposed in the same layer as conductive layer 150. Conductive layer 150_1b contains the same material as conductive layer 150 and is formed by the same steps as conductive layer 150. For example, as shown in Figures 61 and 62, conductive layer 150_1b may also be disposed in a manner that surrounds a portion of electrode WLP2 and insulating layer 132D3.

[0109] For example, as shown in Figure 60, the insulating layer 101 can also be configured to cut off the conductive layer 150 of region RPC1 and the conductive layer 150_1b of region RPC2.

[0110] The insulating layer 132D3 (FIG. 62) extends, for example, along the Z direction and has a generally cylindrical shape. A portion of the insulating layer 132D3 faces the conductive layer 150_1b. The insulating layer 132D3 contains the same materials as the insulating layer 173, such as silicon oxide (SiO2). The insulating layer 132D3 may also be disposed continuously with the insulating layer 173.

[0111] Regarding the formation of conductive layer 150_1b, it can be performed as follows, for example. For instance, in the steps corresponding to Figures 22-24, multiple openings identical to opening TH_130a are also formed in region RPC2. Furthermore, in the steps corresponding to Figures 25-29, multiple sacrificial layers identical to sacrificial layer SC_130 are also formed in region RPC2. Therefore, in the steps corresponding to Figures 30-34, conductive layer 150_1b containing the same material as conductive layer 150 is also formed in region RPC2.

[0112] Furthermore, in the example of the XY cross-section shown in Figure 60, the conductive layer 150_1b of region RPC2 has a shape with annular portions connected, similar to the conductive layer 150 of region RPC1. However, the shape of the conductive layer 150_1b can be appropriately adjusted. For example, the conductive layer 150_1b may also have annular portions connected in a shape such as an ellipse or an oblong shape with both its minor and major axes longer than those of the conductive layer 150. In addition, even if the conductive layer 150_1b has the same shape as the conductive layer 150 at its central portion in the X direction, it may have different shapes such as an ellipse or an oblong shape with a longer major axis at its ends in the X direction.

[0113] [Second Implementation Form] Next, the semiconductor device of the second embodiment will be described using Figures 63 to 66. Figures 63 to 66 are schematic cross-sectional views showing a portion of the structure of the semiconductor device of the second embodiment. Furthermore, Figures 63 and 66 show the portions corresponding to Figures 11 and 12. Figure 64 is a schematic cross-sectional view enlarged from a portion of the structure shown in Figure 63. Figure 65 is a schematic cross-sectional view showing the structure shown in Figure 5 cut along line F-F' and viewed in the direction of the arrow.

[0114] The semiconductor device of this embodiment is basically constructed in the same manner as the semiconductor device of the first embodiment (Figs. 11 and 12). However, in the semiconductor device of this embodiment (Fig. 63), an insulating layer 140_2 is included instead of an insulating layer 140 (Fig. 11), a conductive layer 150_2 is included instead of a conductive layer 150 (Fig. 11), an electrode C1_WL2 is included instead of an electrode C1_WL and a semiconductor layer 130D2 (Fig. 11), and an electrode C1_WLP2 is included instead of an electrode C1_WLP and an electrode WLP (Fig. 12) (Fig. 66).

[0115] The insulating layer 140_2 (Fig. 63) is disposed in essentially the same manner as the insulating layer 140 (Fig. 11). However, unlike the insulating layer 140 (Fig. 11), the insulating layer 140_2 (Fig. 63) is not disposed between the insulating layer 111 and the semiconductor layer 130. In addition, as shown in Figs. 64 and 65, the insulating layer 140_2 is also continuously disposed on the lower surface of the conductive layer 150_2 (Fig. 64) and a portion of the lower surface of the insulating layer 112 (Fig. 65).

[0116] The insulating layer 140_2, for example, in the XZ cross-section shown in FIG64, includes a portion PT_140_1 disposed between the insulating layer 113 and the conductive layer 150_2 and the semiconductor layer 130, and a portion PT_140_2 disposed on the lower surface (substrate side) of the conductive layer 150_2. The portions PT_140_1 and PT_140_2 are disposed continuously.

[0117] The insulating layer 140_2, for example, includes a portion of PT_140_1, a portion of PT_140_2, and a portion of PT_140_3 disposed between the portions of PT_140_1 and PT_140_2 in the YZ cross-section shown in FIG. 65. The portion of PT_140_3 is disposed on a portion of the lower surface (substrate side surface) of the insulating layer 112. The portions of PT_140_1, PT_140_2, and PT_140_3 are disposed continuously.

[0118] The conductive layer 150_2 (Fig. 63) is disposed in essentially the same manner as the conductive layer 150 (Fig. 11). However, the lower surface of the conductive layer 150_2 is in contact with the insulating layer 140_2.

[0119] Electrode C1_WL2 (Figure 63) is connected to the through electrode CC_WL on its lower surface. Electrode C1_WL2 includes a conductive layer 150a_2 such as tungsten (W) and a conductive layer 152_2 such as titanium nitride (TiN). The conductive layer 150_2 is electrically connected to the through electrode CC_WL via electrode C1_WL2.

[0120] Electrode C1_WLP2 (Figure 66) is connected to conductive layer BP at its upper end and electrically connected to through electrode CC_WLP at its lower end. Electrode WLP includes conductive layer 150a_2 and conductive layer 152_2.

[0121] [Manufacturing method 1 of the second embodiment] Next, referring to FIGS. 67 to 91, the manufacturing method 1 of the semiconductor device of this embodiment will be described. FIGS. 67 to 91 are schematic cross-sectional views and plan views for illustrating the manufacturing method 1 of the semiconductor device of the second embodiment.

[0122] Furthermore, Figures 67, 70, 73, 76, 79, 82, 85, 88, and 91 are schematic cross-sectional views corresponding to the portion shown in Figure 63. Figures 68, 71, 74, 77, 80, 83, 86, and 89 are schematic cross-sectional views corresponding to the portion observed along line E-E', cutting through the structure shown in Figure 5 and following the direction of the arrow. Figures 69, 72, 75, 78, 81, 84, 87, and 90 are plan views showing the same portion as in Figure 5. Furthermore, the following diagrams illustrating the manufacturing method are schematic; for ease of explanation, some structural elements may be omitted.

[0123] In the manufacturing method described above, similar to the first embodiment, a peripheral circuit layer LPC (FIG. 2), a board line layer LPT (FIG. 2), and a capacitor layer LCP (FIG. 2) including a through electrode CC_WL, a through electrode CC_WLP, and a conductive layer 120 (FIG. 14) are formed on the substrate Sub (FIG. 1). Additionally, as shown in FIG. 67-69, for example, an insulating layer 111 and a sacrificial layer SC_230 such as amorphous silicon (αSi) are formed on the upper surface of the capacitor layer LCP. This step is performed, for example, by CVD.

[0124] Next, for example, as shown in Figures 70-72, openings TH_130_2 and TH_130_2a are formed. Opening TH_130_2 extends along the Z direction, penetrating the sacrificial layer SC_230 and the insulating layer 111, exposing the conductive layer 120. Opening TH_130_2a extends along the Z direction, penetrating the insulating layer 111, exposing the through electrode CC_WL, etc. This step is performed, for example, by means of a RIE (Residual Electrode).

[0125] Next, for example, as shown in Figures 73-75, a semiconductor layer 130B containing the same material as semiconductor layer 130 is formed inside openings TH_130_2 and TH_130_2a. This step is performed, for example, by CVD, CMP, etc.

[0126] Next, for example, as shown in Figures 76-78, the sacrificial layer SC_230 is removed, exposing the upper surface of the insulating layer 111 and a portion of the upper surface and outer peripheral surface of the semiconductor layer 130B. This step is performed, for example, by wet etching.

[0127] Next, for example, as shown in Figures 79-81, an insulating layer 140_2B containing the same material as the insulating layer 140_2 is formed on a portion of the upper surface and outer peripheral surface of the semiconductor layer 130B, and on the upper surface of the insulating layer 111. This step is performed, for example, by CVD, ALD, etc.

[0128] Next, for example, as shown in Figures 82-84, a conductive layer 150_2B containing the same material as the conductive layer 150_2 is formed on the upper surface of the structure shown in Figures 79 and 80. Through this step, the conductive layer 150_2B closes the spaces between the semiconductor layers 130B arranged in the X direction (Figure 82). On the other hand, the conductive layer 150_2B does not close the spaces between the semiconductor layers 130B arranged in the Y2 direction, forming an opening TH_150_2B between the semiconductor layers 130B arranged in the Y2 direction (Figure 83). This step is performed, for example, by CVD.

[0129] Next, for example, as shown in Figures 85-87, the conductive layer 150_2B is etched back to form the conductive layer 150_2. In this step, the portion below the part of the conductive layer 150_2B where the opening TH_150_2B is formed is removed, and the opening TH_150_3B is formed in the portion between the semiconductor layers 130B arranged in the Y2 direction (Figure 86). The opening TH_150_3B extends along the X and Z directions, penetrating the conductive layer 150_2B, exposing a portion of the insulating layer 140_2B formed on the upper surface of the insulating layer 111. Through this step, a conductive layer 150_2 truncated in the Y direction is formed (Figure 87). This step is performed, for example, by means of a RIE (Reinforcing Interchange).

[0130] Next, for example, as shown in Figures 88-90, a material identical to insulating layer 113 is formed on the upper surface of the structure shown in Figures 85 and 86, and a portion of the insulating layer and insulating layer 140_2B on the upper surface are removed, thereby forming insulating layer 113, semiconductor layer 130, and insulating layer 140_2. This step is performed, for example, by CVD, CMP, etc.

[0131] Next, for example, as shown in FIG91, conductive layers 170', 171', and 172', and insulating layer 173' are formed. This step is performed in the same manner as that described with reference to FIGS. 41-46.

[0132] Next, for example, as shown in FIG91, an opening TH_C1_WL2 is formed at the position corresponding to electrode C1_WL2. The opening TH_C1_WL2 extends along the Z direction, penetrating insulating layer 173', insulating layer 113, conductive layer 150_2, and insulating layer 112, exposing electrode C1_WLP. This step is performed, for example, by means of a RIE (Radio Interchange Equipment).

[0133] Next, conductive layer 152_2 and conductive layer 150a_2 (Fig. 63) are formed at the opening TH_C1_WL2. The plug LP, bit line BL, and wiring layer LUL (Fig. 2) are formed in the same manner as the steps described with reference to FIG49 to FIG52, thereby manufacturing a semiconductor device of the second embodiment.

[0134] [Second Embodiment Manufacturing Method 2] Next, referring to FIGS. 92 to 106, the manufacturing method 2 of the semiconductor device of this embodiment will be described. FIGS. 92 to 106 are schematic cross-sectional views and plan views for illustrating the manufacturing method 2 of the semiconductor device of the second embodiment.

[0135] Furthermore, Figures 92, 95, 98, 101, and 104 are schematic cross-sectional views corresponding to the parts in Figure 63. Figures 93, 96, 99, 102, and 105 are schematic cross-sectional views corresponding to the parts observed along line E-E' when the structure shown in Figure 5 is cut through, and viewed in the direction of the arrow. Figures 94, 97, 100, 103, and 106 are plan views showing the same parts as in Figure 5. Furthermore, the following diagrams illustrating the manufacturing method are schematic; for ease of explanation, some structural elements may be omitted.

[0136] In the manufacturing method described herein, the same steps as those described with reference to Figures 67 to 72 are performed.

[0137] Next, for example, as shown in Figures 92-94, a sacrificial layer SC_130_2, such as amorphous silicon (αSi), is formed inside the openings TH_130_2 and TH_130_2a. This step is performed, for example, by CVD, CMP, etc.

[0138] Next, for example, similar to the steps described with reference to Figures 76-78, the sacrificial layer SC_230 is removed. This step exposes the upper surface of the insulating layer 111 and a portion of the upper surface and outer peripheral surface of the sacrificial layer SC_130_2.

[0139] Next, for example, as shown in Figures 95-97, an insulating layer 140_2B containing the same material as the insulating layer 140_2 is formed on the upper surface and a portion of the outer peripheral surface of the sacrificial layer SC_130_2, and on the upper surface of the insulating layer 111. This step is performed, for example, by CVD, ALD, etc.

[0140] Next, for example, as shown in Figures 95-97, a conductive layer 150_2B is formed. Through this step, the spaces between the sacrificial layers SC_130_2 arranged in the X direction are closed by the conductive layer 150_2B (Figure 95). On the other hand, the spaces between the sacrificial layers SC_130_2 arranged in the Y2 direction are not closed by the conductive layer 150_2B, and an opening TH_150_2B is formed between the sacrificial layers SC_130_2 arranged in the Y2 direction (Figure 96). This step is performed, for example, by CVD or the like.

[0141] Next, for example, as shown in Figures 98-100, the conductive layer 150_2B is etched back to form the conductive layer 150_2. In this step, the portion below the part of the conductive layer 150_2B where the opening TH_150_2B is formed is removed, and the opening TH_150_3B is formed in the portion between the sacrificial layers SC_130_2 arranged in the Y2 direction (Figure 99). Through this step, a conductive layer 150_2 truncated in the Y direction is formed. This step is performed, for example, by means of a RIE (Reverse Etching).

[0142] Next, for example, as shown in Figures 101-103, a material identical to insulating layer 113 is formed on the upper surface of the structure shown in Figures 98 and 99, and a portion of the insulating layer and insulating layer 140_2B on the upper surface is removed, thereby forming insulating layer 113 and insulating layer 140_2, exposing the upper surface of sacrificial layer SC_130_2. This step is performed, for example, by CVD, CMP, etc.

[0143] Next, for example, as shown in Figures 104-106, the sacrificial layer SC_130_2 is removed to form openings TH_130_3 and TH_130_3a. Openings TH_130_3 and TH_130_3a extend along the Z-direction, exposing a portion of the insulating layer 140_2 and the insulating layer 111 on the side surface, and exposing the conductive layer 120 and the through electrode CC_WL on the bottom surface. This step is performed, for example, by wet etching.

[0144] Next, a semiconductor layer 130 is formed inside the openings TH_130_3 and TH_130_3a, and a semiconductor layer 130D1 is formed inside the opening TH_130_3a. This step is performed, for example, by CVD or CMP.

[0145] Next, following the steps described with reference to FIG91, the semiconductor device of the second embodiment is manufactured in the same manner as manufacturing method 1 of the second embodiment.

[0146] [Effect] In the semiconductor device of this embodiment, similarly to the first embodiment (Fig. 5), the width DT10 is larger than the width DX10.

[0147] In this structure, for example in manufacturing method 1, in the steps described with reference to FIGS. 82-84, the semiconductor layers 130B ( FIGS. 82-84) arranged in the Y2 direction corresponding to the position where the semiconductor layer 130 is formed are not blocked by the conductive layer 150_2B (FIG. 83). Thereby, the conductive layer 150_2 (FIG. 85-87) formed by etching back the conductive layer 150_2B is connected in the X direction and truncated in the Y direction. In this step, the conductive layer 150_2 can be formed self-aligned along the semiconductor layers 130B arranged in the X direction.

[0148] Furthermore, for example, in manufacturing method 2, in the steps described with reference to FIGS. 95-97, the sacrificial layers SC_130_2 ( FIGS. 95-97) arranged in the Y2 direction corresponding to the position where the semiconductor layer 130 is formed are not blocked by the conductive layer 150_2B (FIG. 96). In this way, the conductive layer 150_2 (FIG. 98-100) formed by etching back the conductive layer 150_2B is connected in the X direction and truncated in the Y direction. In this step, the conductive layer 150_2 can be formed self-aligned along the sacrificial layers SC_130_2 arranged in the X direction.

[0149] This enables the fabrication of selective transistors (ST) with high density and excellent transistor characteristics (Fig. 1), as well as fine character lines (WL). Furthermore, the need for a fine photolithography step to process the conductive layer 150_2 is eliminated, thereby reducing manufacturing costs.

[0150] [Example of a variation of the second implementation] Next, a modified example of the semiconductor device according to the second embodiment will be described with reference to FIG107. FIG107 is a schematic cross-sectional view showing a portion of the structure of the semiconductor device of this modified example.

[0151] In the semiconductor device of this modified example (FIG. 107), insulating layer 140_3 is provided instead of insulating layer 140_2 (FIG. 65).

[0152] Insulating layer 140_3 (Fig. 107) is provided in essentially the same manner as insulating layer 140_2 (Fig. 65). However, insulating layer 140_3 does not have a portion corresponding to the portion PT_140_3 of insulating layer 140_2. Insulating layer 140_3 is truncated in the Y direction.

[0153] [Third Implementation Form] Next, the semiconductor device of the third embodiment will be described using Figures 108 to 110. Figures 108 to 110 are schematic cross-sectional views, plan views, and perspective views showing a portion of the structure of the semiconductor device of the third embodiment.

[0154] Furthermore, Figure 108 shows the portion corresponding to Figure 11. Figure 109 is a schematic plan view corresponding to the portion observed along the G-G' line that cuts through the structure shown in Figure 108 and in the direction of the arrow. Figure 110 shows the structure of the memory region RMC and region RPC1.

[0155] The semiconductor device of this embodiment is basically constructed in the same way as the semiconductor device of the first embodiment (FIG. 11). However, in the semiconductor device of this embodiment, a conductive layer 150_3 (FIG. 108) is provided instead of a conductive layer 150 (FIG. 11), and semiconductor layers 130D1 and 130D2 are not provided in region RPC1.

[0156] The conductive layer 150_3 (Fig. 108) is provided in essentially the same manner as the conductive layer 150 (Fig. 11). However, regarding the conductive layer 150_3, for example, as shown in Fig. 110, in the memory region RMC, a generally cylindrical portion surrounding a portion of the semiconductor layer 130 and the insulating layer 140 is provided connected in the X direction, but in the region RPC1, a generally cylindrical portion is provided connected in the X direction.

[0157] [Manufacturing method of the third embodiment] Next, the manufacturing method of the semiconductor device according to this embodiment will be described with reference to Figures 111 to 132. Figures 111 to 132 are schematic cross-sectional and plan views for illustrating the manufacturing method of the semiconductor device according to the third embodiment.

[0158] Furthermore, Figures 111, 114, 117, 119, 121, 123, 125, 127, and 130 are schematic cross-sectional views corresponding to the parts in Figure 108. Figures 112, 115, 118, 120, 122, 124, 126, 128, and 131 are schematic cross-sectional views corresponding to the parts observed along line E-E' when the structure shown in Figure 5 is cut through, and viewed in the direction of the arrow. Figures 113, 116, 129, and 132 are schematic cross-sectional views corresponding to the parts in Figure 109. Furthermore, the following diagrams of the manufacturing method are schematic diagrams; for ease of explanation, some structures may be omitted.

[0159] In the manufacturing method described herein, the same steps as those in the manufacturing method of the first embodiment are performed up to the steps described with reference to FIG14 and FIG15.

[0160] Next, for example, as shown in Figures 111 and 112, a conductive layer and a conductive layer 150a containing the same material as the conductive layer 150_3 are formed on the upper surface of the structure shown in Figures 14 and 15 and inside the opening TH_150 (Figure 14), and an insulating layer 113 is formed on the upper surface of the conductive layer. This step is performed, for example, by CVD.

[0161] Next, for example, as shown in Figures 111-113, an opening TH_130_4 is formed. The opening TH_130_4 extends along the Z-direction, penetrating the insulating layer 113, the conductive layer containing the same material as the conductive layer 150_3, and the insulating layer 111, exposing the conductive layer 120. Through this step, the conductive layer 150B is formed. This step can also be performed using the masking material HM10, for example, in the same manner as the steps described with reference to Figures 19-21.

[0162] Next, for example, as shown in Figures 114-116, an insulating layer 140 and a semiconductor layer 130 are formed inside the opening TH_130_4. In this step, the insulating layer 140 is formed by removing the portion of the insulating layer formed on the bottom surface of the opening TH_130_4 after forming an insulating layer containing the same material as the insulating layer on the inner surface and bottom surface of the opening TH_130_4. The semiconductor layer 130 is connected to the inner surface of the insulating layer 140 and is formed in a way that it is embedded in the opening TH_130_4. This step is performed, for example, by ALD, CVD, RIE, CMP, etc.

[0163] Next, for example, as shown in Figures 117 and 118, conductive layers 170'', 171'', and 172'' are sequentially formed on the upper surface of the structure shown in Figures 114 and 115. Furthermore, in the memory region RMC, at positions corresponding to conductive layers 170, 171, and 172, masking materials such as silicon oxide (SiO2) and silicon nitride (SiN) are formed using photolithography or the like. Additionally, in region RPC1, for example, masking materials such as silicon oxide (SiO2) and silicon nitride (SiN) are formed using photolithography, with the same shape and arrangement as the memory region RMC. This step is performed, for example, by CVD or RIE.

[0164] Next, for example, as shown in Figures 119 and 120, the portions of conductive layers 170'', 171'', and 172'' not covered by the masking material MS_PL are removed, thereby forming conductive layers 170', 171', and 172'. This step is performed, for example, by means of a RIE (Radio Interchange Equipment).

[0165] Next, for example, as shown in Figures 121 and 122, an insulating layer 330'', such as silicon oxide (SiO2), is formed on the upper surface of the structure shown in Figures 119 and 120. Through this step, the structures arranged in the X direction, including conductive layers 170', 171', and 172', are closed by the insulating layer 330'' (Figure 121). On the other hand, the structures arranged in the Y2 direction, including conductive layers 170', 171', and 172', are not closed by the insulating layer 330'', forming an opening TH_170B (Figure 122). This step is performed, for example, by CVD, ALD, etc.

[0166] Next, for example, as shown in Figures 123 and 124, the insulating layer 330'' is etched back to form the insulating layer 330'. In this step, the portion of the insulating layer 330'' that is in contact with the bottom surface of the opening TH_170B is removed to form the opening TH_170 (Figure 124). The opening TH_170 extends along the X and Z directions, exposing a portion of the insulating layer 113 on the bottom surface. This step is performed, for example, by means of a RIE (Reinforcing Edge Etching) or the like.

[0167] Next, for example, as shown in Figures 125 and 126, the exposed portion of the upper surface of the insulating layer 113 is removed to form an opening TH_113. The opening TH_113 extends along the X and Z directions, exposing a portion of the upper surface of the conductive layer 150B at its bottom surface. This step forms the insulating layer 330. The outer peripheral surface of the insulating layer 330 in the Y2 direction is, for example, provided outward from the outer peripheral surface of the conductive layer 172' in the Y2 direction at a distance DW30. Additionally, in this step, a portion of the upper surface of the masking material MS_PL is also removed. This step is performed, for example, by means of a RIE (Reinforcing Equipment).

[0168] Next, for example, as shown in Figures 127-129, the exposed portion of the upper surface of the conductive layer 150B is removed to form an opening TH_112B2. The opening TH_112B2 extends along the X and Z directions, penetrating the conductive layer 150B, exposing a portion of the upper surface of the insulating layer 111 at the bottom surface. This step forms the conductive layer 150_3. Furthermore, when the outer peripheral surface of the opening TH_112B2 is perpendicular to the substrate, the outer peripheral surface of the conductive layer 150_3 in the Y2 direction is, for example, provided outward from the outer peripheral surface of the conductive layer 172' in the Y2 direction by a distance DW30. This step is performed, for example, by a RIE (Radio Interchange Equipment).

[0169] Furthermore, depending on the processing conditions, when the outer peripheral surface of the opening TH_112B2 is not perpendicular to the substrate but inclined, when viewed from the Z direction, the outer peripheral surface of the conductive layer 150_3 in the Y2 direction can be positioned outward from the outer peripheral surface of the conductive layer 172' in the Y2 direction by a width smaller than the distance from DW30, or it can be positioned outward by a width larger than the distance from DW30. Additionally, the outer peripheral surface of the conductive layer 150_3 in the Y2 direction can be aligned with the outer peripheral surface of the conductive layer 172' in the Y2 direction, and the outer peripheral surface of the conductive layer 150_3 in the Y2 direction can also be located at a position a predetermined distance inward from the outer peripheral surface of the conductive layer 172' in the Y2 direction.

[0170] Next, for example, as shown in Figures 130-132, the insulating layer 330 and the masking material MS_PL are removed, and an insulating layer 112 is formed at the opening TH_112B2. Additionally, in region RPC1, conductive layers 170', 171', and 172' that are not connected to the semiconductor layer 130 are removed, and then an insulating layer 173 is formed between the structures including conductive layers 170', 171', and 172'. This step is performed, for example, by CVD.

[0171] Next, the semiconductor device of the third embodiment is manufactured by performing the steps described with reference to Figures 47 onwards, for example, in the same manner as the manufacturing method of the first embodiment.

[0172] [Positional relationship between conductive layer 172 and conductive layer 150_3] Figure 133 is a schematic plan view showing a portion of the structure of the semiconductor device according to the third embodiment. Furthermore, Figure 133 shows the portion corresponding to Figure 6. Additionally, in Figure 133, the conductive layer 150_3, which does not appear in the cross-section, is indicated by dashed lines to show positional relationships.

[0173] For example, as shown in Figure 133, in an XY cross-section including multiple conductive layers 172, the closest distance between the outer peripheral surfaces of one of two conductive layers 172 arranged in the X direction and the outer peripheral surface of the other conductive layer 172 is distance DX30. Furthermore, the closest distance between the outer peripheral surfaces of one of two conductive layers 172 arranged in the Y2 direction and the outer peripheral surface of the other conductive layer 172 is distance DT30. Distance DT30 is greater than distance DX30.

[0174] Additionally, as shown in the example of FIG133, when viewed from the Z direction, a portion of one side of the conductive layer 150_3 in the Y direction is positioned outward from a portion of one side of the conductive layer 172 in the Y direction by a distance DW31.

[0175] Furthermore, the distance DW31 can be the same as the distance DW30 (Figure 128), or it can be larger or smaller than the distance DW30.

[0176] In addition to the example shown in FIG133, when viewed from the Z direction, a portion of one side of the conductive layer 150_3 in the Y direction may be disposed inwardly by a certain width relative to a portion of one side of the conductive layer 172 in the Y direction, or it may be consistent with a portion of one side of the conductive layer 172 in the Y direction.

[0177] [Effect] In the semiconductor device of this embodiment, as shown in FIG133, the closest distance between the outer peripheral surfaces of the two conductive layers 172 arranged in the Y2 direction is DT30, which is greater than the closest distance between the outer peripheral surfaces of the two conductive layers 172 arranged in the X direction is DX30.

[0178] In this structure, during the steps described with reference to Figures 121 and 122, the conductive layers 172' arranged in the Y2 direction are not blocked by the insulating layer 330'' (Figure 122). Thus, the conductive layer 150_3 (Figures 127-129) formed by etching back the insulating layer 330'' is connected in the X direction and truncated in the Y direction. In this step, the conductive layer 150_3 can be formed self-aligned along the conductive layers 172' arranged in the X direction.

[0179] This enables the fabrication of selective transistors (ST) with high density and excellent transistor characteristics (Fig. 1), as well as fine word lines (WL). Furthermore, the need for a fine photolithography step to process the conductive layer 150_3 is eliminated, thereby reducing manufacturing costs.

[0180] [Other Implementation Forms] The semiconductor devices of the first to third embodiments have been described above. However, these semiconductor devices are merely examples, and their specific structures and operations can be appropriately adjusted.

[0181] Regarding the semiconductor devices of the first to third embodiments, for example, as shown in FIG5, an example is shown where the shape of the semiconductor layer 130 in the XY cross-section is elliptical. Additionally, FIG5 shows an example where the major axis direction of the ellipse is not aligned with the X and Y directions. However, these shapes of the semiconductor layer 130 are merely illustrative, and the specific shape can be appropriately adjusted.

[0182] The shape of the semiconductor layer 130 can be, for example, an ellipse, a circle, or an oblong. In the case of an ellipse or an oblong, the major axis direction can be the same as or different from the X, Y, X2, and Y2 directions.

[0183] For example, the above description illustrates an example of selecting transistor ST (Figure 1) to connect capacitor Cap (Figure 1). In this example, the shape, structure, etc., of capacitor Cap can be appropriately adjusted.

[0184] Furthermore, the above description illustrates an example of using a capacitor Cap (Figure 1) as a memory unit connected to a select transistor ST (Figure 1). However, the memory unit may not necessarily be a capacitor Cap. For example, the memory unit may also contain ferroelectric, ferromagnetic, chalcogenide materials such as GeSbTe, or other materials, and utilize the properties of these materials to record data. For example, in any of the structures described above, the insulating layer between the electrodes forming the capacitor Cap may contain any of these materials.

[0185] Furthermore, in the above description, the semiconductor layer 130, which functions as the channel region of the selective transistor ST (FIG. 1), is shown as an example of one that extends along the Z direction and has a generally cylindrical shape. However, the semiconductor layer 130 may also be a generally cylindrical shape extending along the Z direction. Additionally, an insulating layer containing silicon oxide (SiO2) or the like, which extends along the Z direction, may be provided inside the semiconductor layer 130.

[0186] 〔other〕 Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention described in the claims and their equivalents.

[0187] 100, 101, 111, 112, 113, 113', 132D1, 132D2, 132D3, 140, 140_2, 140_2B, 140_3, 173, 173', 183, 202, 230, 304, 330, 330', 330'', MS_113: Insulation layer 120, 121, 150, 150_1a, 150_1b, 150_2, 150_2B, 150_3, 150a, 150a_2, 150B, 150B', 152, 152_2, 153, 154, 170, 170', 170'', 171, 171'', 172, 172', 172'', 182, 182', 182a, 184, 184', 184a, 201, 203, 204, 205, 220, 221, BP: Conductive layer 130, 130B, 130D1, 130D2: Semiconductor layers 192, 210, C1_WL, C1_WL2, C1_WLP, C1_WLP2, WLP, WLP2: Electrodes 301, 302, 303: Wiring AG1: Angle BL: Bitline Cap: Capacitor CC_WL, CC_WLP: Through-electrode CP10: Capacitor Structure DRX2, DRY1, DT10, DW11, DX10: Width DT30, DW30, DW31, DX30: Distance HM10, MS_PL: Masking material LBL: Bitline Layer LCP: Capacitor Layer LLP: Insertion Layer LML: Wiring Layer LP: Plug LPC: Peripheral Circuit Layer LPT: Plate Line Layer LTr: Transistor layer LUL: Wiring Layer MC: Memory Cell MCA: Memory Cell Array OT: External Tangent PC: Peripheral Circuits PL: Board Line PT11, PT12, PT13, PT_140_1, PT_140_2, PT_140_3: Partial list R10, RPC, RPC1, RPC2: Region RM10: Photoresist RMC: Memory Region S11: Noodles SC_130, SC_130_2, SC_230: Sacrificial Layer ST: Select Transistor Sub:Substrate TH_112, TH_112B, TH_112B2, TH_113, TH_130, TH_130_1, TH_130_1a, TH_130_2, TH_130_2a, TH_130_3, T H_130_3a, TH_130_4, TH_130a, TH_150, TH_150_2B, TH_150_3B, TH_170, TH_170B, TH_C1_WL2, TH_WLP: opening TrP1: Transistor WL: Character Line X, X², Y, Y², Z: Direction

Claims

1. A semiconductor device, comprising: substrate; A first oxide semiconductor layer and a second oxide semiconductor layer extend along a first direction intersecting the surface of the substrate and are arranged in a second direction intersecting the first direction, and contain a first metal element and oxygen (O); a first conductive layer extends along the second direction and faces a portion of the outer peripheral surface of the first oxide semiconductor layer and a portion of the outer peripheral surface of the second oxide semiconductor layer; a first gate insulating layer is disposed between the first oxide semiconductor layer and the first conductive layer. And a second gate insulating layer, disposed between the second oxide semiconductor layer and the first conductive layer, in a first cross section extending along the second direction and a third direction intersecting the first direction and the second direction and including the first oxide semiconductor layer, the second oxide semiconductor layer and the first conductive layer, the first conductive layer includes: an annular first portion, disposed from the outer peripheral surface of the first oxide semiconductor layer away from a first width and surrounding the first oxide semiconductor layer; And a second annular portion, disposed away from the outer peripheral surface of the second oxide semiconductor layer at a distance from the first width and surrounding the second oxide semiconductor layer, overlapping a portion of a circle, ellipse or oblong circumscribed by the first portion and a portion of a circle, ellipse or oblong circumscribed by the second portion.

2. The semiconductor device as claimed in claim 1, comprising: A third oxide semiconductor layer extends along the first direction and is arranged in a direction that intersects the first direction and is different from the second direction relative to the first oxide semiconductor layer, and contains the first metal element and oxygen (O); a second conductive layer is arranged adjacent to the first conductive layer in the third direction and extends along the second direction, and faces a portion of the outer peripheral surface of the third oxide semiconductor layer; and a third gate insulating layer is disposed between the third oxide semiconductor layer and the second conductive layer. The first cross-section further includes the third oxide semiconductor layer and the second conductive layer. In the first cross-section, when the closest distance between the outer peripheral surface of the first oxide semiconductor layer and the outer peripheral surface of the second oxide semiconductor layer is defined as the second width, and the closest distance between the outer peripheral surface of the first oxide semiconductor layer and the outer peripheral surface of the third oxide semiconductor layer is defined as the third width, the third width is larger than the second width.

3. The semiconductor device as claimed in claim 1, comprising: A fourth oxide semiconductor layer, comprising the first metal element and oxygen (O), extends along the first direction and is aligned with the first oxide semiconductor layer in the second direction, and a portion of its outer peripheral surface faces the first conductive layer; a through electrode is disposed on one side of the first direction relative to the fourth oxide semiconductor layer and extends along the first direction; and a third conductive layer is disposed between the first conductive layer and the through electrode, and surrounds another portion of the outer peripheral surface of the fourth oxide semiconductor layer, wherein the first conductive layer and the through electrode are electrically connected via the third conductive layer.

4. The semiconductor device as claimed in claim 1, comprising: A first insulating layer extends along the first direction and is aligned with the first oxide semiconductor layer in the second direction, with a portion of its outer peripheral surface facing the first conductive layer; a through electrode is disposed on one side of the first direction relative to the first insulating layer and extends along the first direction; and a third conductive layer is disposed between the first conductive layer and the through electrode, and surrounds another portion of the outer peripheral surface of the first insulating layer, wherein the first conductive layer and the through electrode are electrically connected via the third conductive layer.

5. The semiconductor device of claim 1, comprising a fifth oxide semiconductor layer, the fifth oxide semiconductor layer comprising the first metal element and oxygen (O), extending along a first direction and aligned with the first oxide semiconductor layer in a second direction, and a portion of its outer peripheral surface facing the first conductive layer, wherein in a second cross-section extending along the second direction and the third direction and including the fifth oxide semiconductor layer and the first conductive layer, the first conductive layer includes an annular third portion disposed from the outer peripheral surface of the fifth oxide semiconductor layer away from the first width and surrounding the fifth oxide semiconductor layer, a portion of the third portion being an end of the first conductive layer in the second direction.

6. The semiconductor device of claim 1, comprising a second insulating layer extending along a first direction and aligned with a first oxide semiconductor layer in a second direction, and a portion of its outer peripheral surface facing the first conductive layer, wherein in a third cross-section extending along the second direction and the third direction and including the second insulating layer and the first conductive layer, the first conductive layer includes an annular fourth portion surrounding the outer peripheral surface of the second insulating layer, a portion of the fourth portion being an end portion of the first conductive layer in the second direction.

7. The semiconductor device of claim 1, comprising a third insulating layer disposed on one side of the first conductive layer in the first direction, the third insulating layer comprising the same material as the first gate insulating layer and the second gate insulating layer, and being continuous with the first gate insulating layer and the second gate insulating layer.

8. The semiconductor device as claimed in claim 2, comprising: A third insulating layer is disposed on one side of the first conductive layer in the first direction; A fourth insulating layer is disposed on one side of the second conductive layer in the first direction. The third insulating layer comprises the same material as the first gate insulating layer and is continuous with the first gate insulating layer. The fourth insulating layer comprises the same material as the third gate insulating layer and is continuous with the third gate insulating layer. Between the third insulating layer and the fourth insulating layer, a fifth insulating layer comprises the same material as the third insulating layer and the fourth insulating layer and is continuous with the third insulating layer and the fourth insulating layer.

9. The semiconductor device of claim 1, wherein the first metal element is selected from the group consisting of indium (In), gallium (Ga), aluminum (Al), zinc (Zn), tin (Sn), titanium (Ti), tungsten (W), and molybdenum (Mo).

10. The semiconductor device of claim 1, comprising a capacitor layer disposed on one side of the first oxide semiconductor layer and the second oxide semiconductor layer in the first direction, the capacitor layer comprising capacitor structures electrically connected to the first oxide semiconductor layer and the second oxide semiconductor layer, respectively.

11. A semiconductor device, comprising: substrate; A first oxide semiconductor layer and a second oxide semiconductor layer extend along a first direction intersecting the surface of the substrate and are arranged in a second direction intersecting the first direction, and contain a first metal element and oxygen (O); a first conductive layer extends along the second direction and faces a portion of the outer peripheral surface of the first oxide semiconductor layer and a portion of the outer peripheral surface of the second oxide semiconductor layer; a gate insulating layer is disposed between the first oxide semiconductor layer and the first conductive layer, and between the second oxide semiconductor layer and the first conductive layer; and a first electrode and a second electrode are respectively connected to one end of the first oxide semiconductor layer and the second oxide semiconductor layer in the first direction. When viewed from the first direction, a portion of the surface of the first conductive layer in a third direction intersecting the first and second directions is disposed consistent with the surface of the first electrode and the second electrode in the third direction, or is disposed away from the surface of the first electrode and the second electrode in the third direction by a first distance from the outside or inside.

12. The semiconductor device of claim 11, wherein the first electrode includes a fourth conductive layer, the fourth conductive layer being connected to one end of the first oxide semiconductor layer in the first direction and comprising a second metal element and oxygen (O), the second metal element being an element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), manganese (Mn), tin (Sn), titanium (Ti), tantalum (Ta), calcium (Ca), tungsten (W), and molybdenum (Mo).

13. The semiconductor device as claimed in claim 11, comprising: A third oxide semiconductor layer, extending along the first direction and arranged in a direction intersecting the first direction and different from the second direction relative to the first oxide semiconductor layer, and containing the first metal element and oxygen (O); a third electrode, connected to one end of the third oxide semiconductor layer in the first direction; and a second conductive layer, arranged adjacent to the first conductive layer in the third direction and extending along the second direction, and facing a portion of the outer peripheral surface of the third oxide semiconductor layer, wherein in a cross-section extending along the second direction and the third direction and including the first electrode, the second electrode, and the third electrode, when the closest distance between the outer peripheral surface of the first electrode and the outer peripheral surface of the second electrode is defined as a second distance, and the closest distance between the outer peripheral surface of the first electrode and the outer peripheral surface of the third electrode is defined as a third distance, the third distance is larger than the second distance.

14. The semiconductor device of claim 11, wherein the first metal element is selected from the group consisting of indium (In), gallium (Ga), aluminum (Al), zinc (Zn), tin (Sn), titanium (Ti), tungsten (W), and molybdenum (Mo).

15. The semiconductor device of claim 11, comprising a capacitor layer disposed on one side of the first oxide semiconductor layer and the second oxide semiconductor layer in the first direction, the capacitor layer comprising capacitor structures electrically connected to the first oxide semiconductor layer and the second oxide semiconductor layer, respectively.

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