Integrated junction silicide and selective metal capping with pullback

TW202641326APending Publication Date: 2026-10-01APPLIED MATERIALS INC
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Patent Information

Application Number
TW114136942
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2025-03-18
Filing Date
2025-09-25
Publication Date
2026-10-01

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Abstract

Methods for forming low resistivity contacts for semiconductor device formation are provided. A carbon-containing passivation layer is exposed to a first hydrogen plasma to etch a first portion of the carbon-containing passivation layer exposing at least a first portion of a metal silicide layer formed over sidewall surfaces that define an opening while a second portion of the carbon-containing passivation layer remains over a second portion of the metal silicide layer formed over a bottom surface that defines the opening. The first portion of the metal silicide layer is exposed to an etchant gas to remove the first portion of the metal silicide layer formed over the sidewall surfaces. The second portion of the carbon-containing passivation layer remaining over the bottom surface is exposed to a second hydrogen plasma to remove the second portion of the carbon-containing passivation layer exposing the second portion of the metal silicide layer.
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