Semiconductor structure and manufacturing method of semiconductor structure

Abstract

A semiconductor structure and a manufacturing method of the semiconductor structure are provided. The semiconductor structure includes a substrate, an epitaxy layer over the substrate, a diode string over the epitaxy layer, a gate structure, and a source structure. The epitaxy layer has a doped region extending from a top portion of the epitaxy layer toward the substrate. The gate structure is partially surrounded by the doped region and extends into the epitaxy layer. The gate structure includes a first polycrystalline silicon structure, a gate oxide layer, isolating layer, and a second polycrystalline silicon structure. The isolating layer is disposed over the first polycrystalline silicon structure and the gate oxide layer and extends to an area between the doped region and the diode string. The second polycrystalline silicon structure is disposed over the first polycrystalline silicon structure and the gate oxide layer and surrounded by the isolating layer. The source structure abuts the doped region and the second polycrystalline silicon structure and is electrically coupled to the diode string through a first conductive plug.

Description

Technical Field

[0001] This disclosure relates to semiconductor structures and methods for manufacturing semiconductor structures, and more specifically, to semiconductor structures having electrostatic discharge protection structures and trench gate structures, and methods for manufacturing semiconductor structures. Prior Technology

[0002] The miniaturization of semiconductor structures has significantly reduced the distance between components, but it has also increased the risk of electrostatic discharge (ESD) and leakage current. In some background technologies, trench gate structures have been used to illustrate the miniaturization of semiconductor structures, and ESD protection structures can reduce the risk of damage to semiconductor structures from instantaneous high currents. However, such configurations significantly increase the complexity and cost of manufacturing semiconductor structures. Therefore, how to efficiently arrange manufacturing processes has become an important consideration in this field. Summary of the Invention

[0003] The embodiments disclosed herein relate to a semiconductor structure. The semiconductor structure includes a substrate, an epitaxial layer, a diode string, a gate structure, and a source structure. The epitaxial layer is located above the substrate. The epitaxial layer has a doped region. The doped region extends from the top of the epitaxial layer toward the substrate. The diode string is located above the epitaxial layer. The gate structure is at least partially surrounded by the doped region and extends toward the substrate into the epitaxial layer. The gate structure includes a first polysilicon structure, a gate oxide layer, an insulating layer, and a second polysilicon structure. The gate oxide layer surrounds the polysilicon structure. The insulating layer is located above the first polysilicon structure and the gate oxide layer and extends between the doped region and the diode string. The second polysilicon structure is located above the first polysilicon structure and the gate oxide layer and is surrounded by the insulating layer. The source structure is adjacent to the doped region and the second polysilicon structure and is electrically coupled to the diode string via a first conductive plug.

[0004] The embodiments disclosed herein relate to a method for manufacturing a semiconductor structure. The method includes: providing a substrate having an epitaxial layer thereon, wherein the epitaxial layer has a first lightly doped region extending from the top of the epitaxial layer toward the substrate; forming a trench extending from the top surface of the first lightly doped region toward the substrate beyond the first lightly doped region into the epitaxial layer; forming a gate oxide layer surrounding a first polycrystalline silicon structure in the trench; forming an insulating layer above the first polycrystalline silicon structure and the gate oxide layer, extending to the top surface of the first lightly doped region; forming a polycrystalline silicon layer above the insulating layer, wherein the polycrystalline silicon layer fills the remaining space of the trench; and removing a portion of the polycrystalline silicon layer to simultaneously form... A second polycrystalline silicon structure formed in a trench and a third polycrystalline silicon structure on the top surface of a first lightly doped region; a portion of the third polycrystalline silicon structure is converted into a plurality of first doped regions having a first conductivity type, while the remaining portion of the third polycrystalline silicon structure is a plurality of second doped regions having a second conductivity type, wherein the plurality of first doped regions and the plurality of second doped regions are alternately arranged to form a diode string; an interlayer oxide layer is formed on the insulating layer and the second polycrystalline silicon structure, surrounding and covering the diode string; and a source electrode is formed adjacent to the second polycrystalline silicon structure through the interlayer oxide layer. Simple Explanation of the Diagram

[0005] The various embodiments disclosed herein can be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that the structures are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various structures may be arbitrarily enlarged or reduced.

[0006] Figure 1 is a circuit diagram of a semiconductor structure according to some embodiments of the present disclosure.

[0007] Figure 2 is a schematic diagram of a semiconductor structure according to some embodiments of the present disclosure.

[0008] Figure 3 is a top view of a semiconductor structure according to some embodiments of the present disclosure.

[0009] Figure 4 is a side view of a semiconductor structure according to some embodiments of the present disclosure.

[0010] Figures 5 to 24 are schematic diagrams of the manufacturing process of semiconductor structures according to some embodiments of the present disclosure.

[0011] Figures 25, 26 and 27 are schematic diagrams of semiconductor structures according to other embodiments of the present disclosure.

[0012] Identical or similar elements are designated using the same reference numerals in the drawings and detailed description. Several embodiments of this disclosure will be readily understood from the following detailed description in conjunction with the drawings. Implementation

[0013] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of elements and configurations are described below. Of course, these are merely examples and are not intended to be limiting. In this disclosure, references to forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, this disclosure may repeat schematic designations and / or letters in various instances. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] The embodiments of this disclosure are discussed in detail below. However, it should be understood that this disclosure provides many applicable concepts that can be embodied in a wide variety of specific environments. The specific embodiments discussed are merely illustrative and do not limit the scope of this disclosure.

[0015] This disclosure provides a semiconductor structure and its manufacturing method. The semiconductor structure utilizes a polysilicon structure to replace the capping layer on top of the gate structure, and the polysilicon structure can be formed simultaneously using the same semiconductor process as the polysilicon structure in the electrostatic discharge (ESD) structure. In other words, the step of forming the polysilicon structure to replace the capping layer can be integrated with the step of forming the ESD structure. Furthermore, because the polysilicon structure in the ESD structure requires an etching process to form the desired shape, and the polysilicon structure replacing the capping layer can simultaneously undergo the etching process to planarize its upper surface, no additional planarization process is required to planarize the upper surface of the polysilicon structure. In summary, the embodiments provided in this disclosure can reduce the complexity and cost of semiconductor manufacturing processes.

[0016] Figure 1 is a circuit diagram of a semiconductor structure 10 according to some embodiments of the present disclosure. The semiconductor structure 10 has a gate electrode G, a drain electrode D, and a source electrode S, and includes a transistor M, a gate resistor RG, and a diode string DS. The transistor M can be a semiconductor power device of different types or manufactured using different technologies. The source and drain of the transistor M are connected to the source electrode S and the drain electrode D, respectively. The gate of the transistor M is coupled to the gate electrode G via the gate resistor RG. The diode string DS is coupled between the gate electrode G and the source electrode S, and the diode string DS consists of multiple back-to-back diodes connected in series. The diode string DS serves as an electrostatic discharge protection structure for the semiconductor structure 10. It should be understood that this disclosure uses two sets of back-to-back diodes as an example; however, this disclosure is not limited to this, and various numbers of back-to-back diodes are within the scope of this disclosure.

[0017] In the embodiment shown in Figure 1, transistor M is an N-type transistor. However, this disclosure is not limited thereto; in other embodiments, transistor M may be a P-type transistor.

[0018] In some embodiments, the number of back-to-back diodes is determined by the breakdown voltage of the semiconductor structure 10, such as the breakdown voltage of the gate oxide layer 202 (shown in FIG. 2) of transistor M. More specifically, when an electrostatic discharge (ESD) event occurs, the gate resistor RG prevents the instantaneous high current caused by the ESD event from directly attacking the gate of transistor M (e.g., the gate oxide layer 202). This instantaneous high current can flow to the source electrode S via the diode string DS (ESD protection structure) to be transported away from transistor M. In some embodiments, the source electrode S is coupled to ground, so the instantaneous high current caused by the ESD event can flow to ground via the diode string DS. In other words, when an ESD event occurs, the gate resistor RG and the diode string DS provide ESD protection for transistor M. However, for the diode string DS to function, the breakdown voltage of the diode string DS must be less than the breakdown voltage of the gate oxide layer 202 of transistor M. When the voltage caused by the instantaneous large current reaches the withstand voltage of the diode string DS, the diode string DS can be turned on without flowing to the gate of the transistor M. Therefore, the number of back-to-back diodes in the diode string DS is limited by the breakdown voltage of the gate oxide layer 202 of the transistor M.

[0019] Figure 2 is a schematic diagram of a semiconductor structure 10 according to some embodiments of the present disclosure. The semiconductor structure 10 includes a substrate 100, an epitaxial layer 110, an interlayer oxide layer 150, a source electrode 160, a gate electrode 170, a diode string DS, a gate structure G1, a gate structure G2, a gate structure G3, and a gate structure G4.

[0020] An epitaxial layer 110 is disposed above a substrate 100. A diode string DS is disposed above the epitaxial layer 110. A source electrode 160 and a gate electrode 170 are disposed on the epitaxial layer 110 and the diode string DS. An interlayer oxide layer 150 is disposed on the epitaxial layer 110, surrounding the source electrode 160 and the diode string DS, and covering the diode string DS.

[0021] In some embodiments, substrate 100 may be disposed on the upper surface adjacent to a silicon wafer or other semiconductor material substrate. In some embodiments, substrate 100 is part of a silicon wafer. The material of substrate 100 may include single-crystal silicon material, epitaxial silicon material, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), or other semiconductor materials.

[0022] In some embodiments, the epitaxial layer 110 may include, for example, N-type or P-type single-crystal silicon material, epitaxial silicon material, silicon carbide (SiC), germanium (Ge), silicon-germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), or other semiconductor materials. In some embodiments, the substrate 100 and the epitaxial layer 110 are N-type (first conductivity type) epitaxial materials. For ease of explanation, the substrate 100 and the epitaxial layer 110 are exemplified as N-type, but this disclosure is not limited thereto. The N-type (first conductivity type) or P-type (second conductivity type) substrate 100 and the epitaxial layer 110 may be adjusted according to the electrical requirements of the semiconductor structure 10. In some embodiments, the doping concentration of the substrate 100 is greater than the doping concentration of the epitaxial layer 110.

[0023] The epitaxial layer 110 has a doped region. The doped region extends from the top of the epitaxial layer 110 toward the substrate 100, and the doped region includes a first lightly doped region 120 and a second lightly doped region 130. The second lightly doped region 130 is disposed within the first lightly doped region 120. The top surfaces of the first lightly doped region 120 and the second lightly doped region 130 are substantially coplanar, and the bottom surface of the first lightly doped region 120 is closer to the substrate 100 than the bottom surface of the second lightly doped region 130.

[0024] In some embodiments, the first lightly doped region 120 is P-type (second conductivity type), and the doping concentration of the first lightly doped region 120 is greater than the doping concentration of the epitaxial layer 110. In some embodiments, the first lightly doped region 120 serves as the body doped region of the transistor M. In some embodiments, the second lightly doped region 130 is N-type (first conductivity type). The doping concentration of the second lightly doped region 130 is substantially greater than the doping concentration of the first lightly doped region 120. In some embodiments, the second lightly doped region 130 serves as part of the source structure of the transistor M. For the sake of simplicity, the drain structure is not shown in FIG2.

[0025] On a plane jointly defined by the X and Z directions, gate structures G1, G2, G3, and G4 have trench profiles. The trench profiles have sidewalls SS and a bottom surface BS. In some embodiments, gate structures G1, G2, G3, and G4 have vertical sidewalls SS and an arc-shaped bottom surface BS. Gate structures G1, G2, G3, and G4 extend from the top of the epitaxial layer 110 into the substrate 100 and are at least partially surrounded by doped regions. The bottom surface BS of gate structures G1, G2, G3, and G4 protrudes from the bottom surface of the first lightly doped region 120. In some embodiments, gate structures G1, G2, G3, and G4 serve as gate structures of a transistor M.

[0026] Gate structures G1, G2, and G3 include a gate oxide layer 202, a first polysilicon structure 204, a thermal oxide layer 206, a thermal oxide layer 208, an insulating layer 210, and a second polysilicon structure 212. The gate oxide layer 202 is conformally disposed according to the trench profile and surrounds the first polysilicon structure 204. The top surfaces of the gate oxide layer 202 and the first polysilicon structure 204 are coplanar. The insulating layer 210 is disposed above the first polysilicon structure 204 and the gate oxide layer 202. The insulating layer 210 of gate structure G1 extends further between the doped region and the diode string DS. The insulating layer 210 of gate structure G3 extends further between the doped region and the interlayer oxide layer 150. The second polysilicon structure 212 is disposed on the first polysilicon structure 204 and the insulating layer 210, and is surrounded by the insulating layer 210. The top surfaces of the second polycrystalline silicon structure 212, the first lightly doped region 120, and the second lightly doped region 130 are coplanar. A thermal oxide layer 206 is disposed above the first polycrystalline silicon structure 204. A thermal oxide layer 208 extends between the doped region and the insulating layer 210. The thermal oxide layer 208 of the gate structure G1 extends further between the doped region and the diode string DS. The thermal oxide layer 208 of the gate structure G3 extends between the doped region and the interlayer oxide layer 150.

[0027] Gate structure G4 includes a gate oxide layer 202, a first polysilicon structure 204, a thermal oxide layer 206, a thermal oxide layer 208, and an insulating layer 210. Similarly, the gate oxide layer 202 is conformally disposed according to the trench profile and surrounds the polysilicon structure 204. The top surfaces of the gate oxide layer 202 and the first polysilicon structure 204 of gate structure G4 are coplanar with the top surfaces of the first lightly doped region 120 and the second lightly doped region 130. The thermal oxide layer 206 is disposed on the first polysilicon structure 204. The thermal oxide layer 208 of gate structure G4 is disposed between the doped region and the interlayer oxide layer 150, and a portion of the thermal oxide layer 208 is connected to the thermal oxide layer 208 of gate structure G3. Note that the thermal oxide layer 208 of gate structure G4 is not disposed within the trench profile of gate structure G4.

[0028] The thermal oxide layers 206 and 208 of gate structures G1, G2, G3, and G4 are formed simultaneously using a thermal oxidation process. Specifically, the thermal oxidation process converts a portion of the silicon molecules in the first polycrystalline silicon structure 204 into silicon oxide molecules to form the thermal oxide layer 206 (also known as the bottom portion), and converts a portion of the silicon molecules in the doped region into silicon oxide molecules to form the thermal oxide layer 208 (also known as the sidewall portion), wherein the thermal oxide layer 206 does not contact the thermal oxide layer 208. Although the thermal oxide layers 206 and 208 are formed simultaneously, the thickness of the thermal oxide layer 206 above the first polycrystalline silicon structure 204 is greater than the thickness of the thermal oxide layer 208 extending between the doped region and the insulating layer 210. In some embodiments, the thickness of the thermal oxide layer 208 is less than the thickness of the gate oxide layer 202, and the top surface of the gate oxide layer 202 is not completely covered by the thermal oxide layer 208. Therefore, when the insulating layer 210 is formed, the insulating layer 210 directly contacts the top surface of the gate oxide layer 202. In some embodiments, the thickness of the insulating layer 210 is greater than the thickness of the thermal oxide layer 206, and the thickness of the insulating layer 210 is also greater than the thickness of the oxide layer 208.

[0029] In some embodiments, thermal oxide layer 206 and thermal oxide layer 208 may be omitted. In other words, insulating layer 210 is disposed on gate oxide layer 202 and first polycrystalline silicon structure 204, and directly contacts gate oxide layer 202, first polycrystalline silicon structure 204, first lightly doped region 120 and second lightly doped region 130.

[0030] The second lightly doped region 130 is disposed between gate structure G1 and gate structure G2 and between gate structure G2 and gate structure G3. The bottom surface of the second lightly doped region 130 is closer to the substrate 100 than the top surface of the first polycrystalline silicon structure 204 of gate structure G1, gate structure G2 and gate structure G3.

[0031] The number of gate structures G1, G2, G3, and G4 disclosed in this disclosure is merely an example, and various numbers of gate structures G1, G2, G3, and G4 are within the scope of this disclosure. For example, in other embodiments, the semiconductor structure 10 includes more than one gate structure G2.

[0032] The diode string DS is disposed on the insulating layer 210. In the Z direction, the diode string DS does not overlap with gate structures G1, G2, G3, and G4. The diode string DS includes a plurality of first doped regions 310 having a first conductivity type and a plurality of second doped regions 320 having a second conductivity type. The first doped regions 310 and second doped regions 320 are staggered, and adjacent interfaces form a PN junction.

[0033] An interlayer oxide layer 150 is disposed on the insulating layer 210, and also on the second polysilicon structure 212 of the gate structure G1 and the second polysilicon structure 212 of the gate structure G3. The interlayer oxide layer 150 directly contacts the second polysilicon structure 212 of the gate structure G1 and the second polysilicon structure 212 of the gate structure G3. In some embodiments, the interlayer oxide layer 150 is used to define the regions of the source electrode 160 and the gate electrode 170. Specifically, the portion not covered by the interlayer oxide layer 150 can be used to form the source electrode 160 or the gate electrode 170. It should be understood that the position and shape of the interlayer oxide layer 150 are only illustrative, and this disclosure is not limited thereto. In other embodiments, the interlayer oxide layer 150 can have other suitable shapes and suitable distributions.

[0034] The source electrode 160 is adjacent to the second lightly doped region 130 in the doped region of the epitaxial layer 110, the second polycrystalline silicon structure 212 of the gate structure G1, the second polycrystalline silicon structure 212 of the gate structure G2, and the second polycrystalline silicon structure 212 of the gate structure G3. The source electrode 160 covers the interlayer oxide layer 150.

[0035] The gate electrode 170 is disposed on the interlayer oxide layer 150 and corresponds to the gate structure G4 and the diode string DS in the Z direction.

[0036] Semiconductor structure 10 further includes conductive plugs 191 and 192, a metal layer 193, and conductive plug 194. Source electrode 160 is electrically coupled to diode string DS via conductive plug 191. Gate electrode 170 is electrically coupled to diode string DS and gate structure G4 via conductive plugs 192 and 194, respectively. Specifically, conductive plug 191 is adjacent to the first end of the first doped region 310 (as shown in Figure 2, the leftmost one of the first doped region 310); conductive plug 192 is adjacent to the second end of the first doped region 310 (as shown in Figure 2, the rightmost one of the first doped region 310); conductive plug 194 is adjacent to the first polycrystalline silicon structure 204 of gate structure G4. Although not shown in this disclosure, conductive plug 194 is actually electrically coupled to the first polycrystalline silicon structure 204 of gate structures G1, G2, and G3.

[0037] A metal layer 193 is disposed between the source electrode 160 and the interlayer oxide layer 150. More specifically, the metal layer 193 is disposed between the sidewalls extending in the Z direction between the source electrode 160 and the interlayer oxide layer 150. In some embodiments, the material of the metal layer 193 is the same as the material of the conductive plugs 191, 192, and 194.

[0038] In some embodiments, the semiconductor structure 10 further includes a barrier metal layer 195. The barrier metal layer 195 surrounds the source electrode 160, metal layer 193, conductive plugs 191, 192, and 194, and is adjacent to the second lightly doped region 130, gate structures G1, G2, G3, and diode string DS. Specifically, the barrier metal layer 195 is adjacent to the second polycrystalline silicon structure 212, insulating layer 210, and thermal oxide layer 208 of gate structures G1, G2, and G3; the barrier metal layer 195 is adjacent to the first and second ends of the first doped region 310 of the diode string DS.

[0039] In some embodiments, the material of the barrier metal layer 195 may include cobalt (Co), nickel (Ni), titanium (Ti), or platinum (Pt). In some embodiments, the barrier metal layer 195 may be omitted.

[0040] Figure 3 is a top view of a semiconductor structure 10 according to some embodiments of the present disclosure. The top view of Figure 3 illustrates the plane defined by the X and Y directions. For ease of understanding, some components are omitted in the top view of Figure 3.

[0041] The semiconductor structure 10 further includes a heavily doped region 140. Gate structures G1~G3 extend along the Y direction and are surrounded by a second lightly doped region 130 and a heavily doped region 140. The second lightly doped region 130 and the heavily doped region 140 are adjacent to each other and alternately arranged in the Y direction. In other words, the heavily doped region 140 and the second lightly doped region 130 surround each other. It should be noted that the second lightly doped region 130 and the heavily doped region 140 do not overlap when viewed from above.

[0042] The first doped region 310 and the second doped region 320 extend along the Y direction and are arranged parallel to the gate structures G1~G3. The diode string DS composed of the first doped region 310 and the second doped region 320 does not overlap with the gate structures G1~G3 from a top-view perspective.

[0043] Figure 4 is a side view of a semiconductor structure 10 according to some embodiments of the present disclosure. The side view of Figure 4 illustrates a plane defined by the X and Z directions. The side view of Figure 4 is divided into two parts, with the left and right sides separated by a hyperbolic dashed line, representing the cross-sectional structures of line segment A-A' (containing the second lightly doped region 130) and line segment B-B' (containing the heavily doped region 140) in Figure 3, respectively.

[0044] A heavily doped region 140 is disposed on the first lightly doped region 120. In some embodiments, the bottom surface of the heavily doped region 140 is coplanar with the bottom surface of the second lightly doped region 130. In some embodiments, the bottom surface of the heavily doped region 140 is closer to the substrate 100 than the bottom surface of the second lightly doped region 130. The source electrode 160 is adjacent to both the second lightly doped region 130 and the heavily doped region 140. The second lightly doped region 130, the heavily doped region 140, and the source electrode 160 together constitute the source structure of the transistor M.

[0045] The heavily doped region 140 is p-type. In some embodiments, the doping concentration of the second lightly doped region 130 is less than the doping concentration of the heavily doped region 140 and greater than the doping concentration of the first lightly doped region 120.

[0046] Figures 5 to 24 are schematic diagrams of the manufacturing process of a semiconductor structure 10 according to some embodiments of the present disclosure. For ease of understanding, Figures 5 to 24 are divided into two parts, with the left and right sides separated by a hyperbolic dashed line, representing the manufacturing process of the cross-sectional structures of line segments A-A' and B-B' in Figure 3, respectively.

[0047] Referring to Figure 5, an epitaxial layer 110 is formed on the substrate 100. Next, a hard oxide mask 501 is formed on the epitaxial layer 110 using a thermal oxidation process, and a patterned photoresist layer 502 is formed on the hard oxide mask 501. The hard oxide mask 501 is etched according to the patterned photoresist layer 502 to transfer the pattern on the photoresist layer 502 onto the hard oxide mask 501. As shown in Figure 5, after the pattern on the photoresist layer 502 is transferred onto the hard oxide mask 501, a plurality of openings O1 are formed in the hard oxide mask 501. In some embodiments, after the pattern on the photoresist layer 502 is transferred to the hard oxide mask 501, the photoresist layer 502 is removed.

[0048] Referring to Figure 6, a plurality of openings O2 extending toward the substrate 100 are formed in the epitaxial layer 110 corresponding to the openings O1 of the oxide hard mask 501. After the plurality of openings O2 are formed, the oxide hard mask 501 is removed.

[0049] In some embodiments, after the oxide hard mask 501 is removed, a sacrificial oxide layer is formed on the exposed surface of the epitaxial layer 110 by an oxidation process, and then the sacrificial oxide layer is removed. The oxidation process can be performed by adding oxygen and heating to form an oxide, such as silicon dioxide, on the surface of the epitaxial layer 110. In some embodiments, the formation and removal of the sacrificial oxide layer is to optimize the exposed surface of the epitaxial layer 110.

[0050] Referring to Figure 7, a gate oxide layer 202 is formed on the surface of the epitaxial layer 110. The gate oxide layer 202 is also formed on the surface of the opening O2, reducing the opening O2 to the opening O3. In some embodiments, the thickness of the gate oxide layer 202 is substantially uniform.

[0051] Referring to Figure 8, a first polycrystalline silicon structure 204 is formed on the gate oxide layer 202 and filled with openings O3.

[0052] Referring to Figure 9, an etching process is performed to remove a portion of the first polysilicon structure 204. After the etching process, the top surface of the remaining first polysilicon structure 204 is lower than the top surface of the gate oxide layer 202. Next, a patterned photoresist layer 503 is formed on the gate oxide layer 202, and an ion implantation process is performed based on the patterned photoresist layer 503 to form a first lightly doped region 120 in the epitaxial layer 110. The photoresist layer 503 defines the region where the first lightly doped region 120 is formed.

[0053] Referring to Figure 10, a drive-in process is performed to bring the bottom surface of the first lightly doped region 120 closer to the substrate 100. After the drive-in process, the bottom surface of the first lightly doped region 120 remains higher than the bottom surface of the gate oxide layer 202 in the Z direction. After the drive-in process, the photoresist layer 503 is removed.

[0054] Referring to Figure 11, a photoresist layer 504 is formed, and an etching process is performed on the photoresist layer 504 to remove a portion of the first polycrystalline silicon structure 204. After the etching process, the top surface of the first polycrystalline silicon structure 204 is lower than the top surface of the first lightly doped region 120, thus simultaneously forming multiple openings O4. After the etching process, the photoresist layer 504 is removed.

[0055] Referring to Figure 12, an etching process is performed to remove a portion of the gate oxide layer 202. Specifically, the gate oxide layer 202 above the top surface of the first lightly doped region 120 is removed, as is the gate oxide layer 202 in the opening O4 and above the top surface of the first polycrystalline silicon structure 204. Because the first polycrystalline silicon structure 204 is removed, the opening O4 expands to become the opening O5.

[0056] Referring to Figure 13, a thermal oxidation process is performed to form thermal oxide layers 206 and 208. Thermal oxide layer 206 is formed on the exposed top surface of the first polycrystalline silicon structure 204. Thermal oxide layer 208 is formed on the exposed surface of the first lightly doped region 120. In some embodiments, thermal oxide layers 206 and 208 each have a substantially uniform thickness, and the thickness of thermal oxide layer 206 is greater than the thickness of thermal oxide layer 208. Thermal oxide layer 206 is not adjacent to gate oxide layer 202. Thermal oxide layer 208 in opening O5 is adjacent to the top surface of gate oxide layer 202, but thermal oxide layer 208 only covers a portion of the top surface of gate oxide layer 202. Opening O5 is reduced to opening O6 due to the formation of thermal oxide layers 206 and 208.

[0057] Referring to Figure 14, a deposition process is performed to form an insulating layer 210. The insulating layer 210 is conformally formed on the structure shown in Figure 13. In opening O6, since the top surface of the gate oxide layer 202 is partially exposed, the insulating layer 210 directly contacts the gate oxide layer 202 and covers the thermal oxide layer 206. Near the thermal oxide layer 206, the insulating layer 210 forms an "H"-shaped cross-sectional profile. After the insulating layer 210 is formed, opening O6 shrinks to become opening O7. In some embodiments, the thickness of the insulating layer 210 above the top surface of the first lightly doped region 120 is greater than the thickness of the insulating layer 210 in opening O7. In some embodiments, the insulating layer 210, thermal oxide layer 206, and thermal oxide layer 208 are silicon oxide. However, because the methods of forming the insulating layer 210 are different from those of forming the thermal oxide layers 206 and 208, the quality of the insulating layer 210 is different from that of the thermal oxide layers 206 and 208.

[0058] In some embodiments, the semiconductor structure 10 includes an insulating layer 210, but does not include thermal oxide layers 206 and 208. Therefore, the manufacturing steps shown in FIG13 are omitted, and the positions occupied by thermal oxide layers 206 and 208 in FIG13 are replaced by the insulating layer 210.

[0059] In other embodiments, the semiconductor structure 10 includes thermal oxide layers 206 and 208, but does not include an insulating layer 210, so the manufacturing steps shown in FIG14 are omitted.

[0060] Referring to Figure 15, a deposition process is performed to form a polycrystalline silicon layer 505I in the opening O7 and on the insulating layer 210. The polycrystalline silicon layer 505I is undoped polycrystalline silicon.

[0061] Referring to Figure 16, an ion implantation process is performed on the polycrystalline silicon layer 505I to convert the undoped polycrystalline silicon layer 505I into a p-type polycrystalline silicon layer 505D. In some embodiments, an annealing process is performed on the polycrystalline silicon layer 505D after the ion implantation process. In some embodiments, the polycrystalline silicon layer 505D may be n-type.

[0062] Referring to Figure 17, a photoresist layer 506 is formed on the polycrystalline silicon layer 505D. The photoresist layer 506 is used to define the position of the diode string DS.

[0063] Referring to Figure 18, an anisotropic etching process is performed on the photoresist layer 506 to remove a portion of the polysilicon layer 505D and a portion of the insulating layer 210. The remaining polysilicon layer 505D becomes the p-type second doped region 320 and the second polysilicon structure 212. The insulating layer 210 below the photoresist layer 506 is not etched, and the portion of the insulating layer 210 not covered by the photoresist layer 506 is partially removed, resulting in a thickness TH1 of the insulating layer 210 below the second doped region 320 being greater than the thickness TH2 of the remaining portion of the insulating layer 210. In some embodiments, the thickness TH1 is approximately between 300 angstroms and approximately 10,000 angstroms. After the etching process, the photoresist layer 506 is removed. The polysilicon layer 505D, after being partially removed, is then divided into two discontinuous portions, namely the second doped region 320 and the second polysilicon structure 212. However, as can be seen from the manufacturing process shown in Figures 15 to 18, the second doped region 320 and the second polycrystalline silicon structure 212 are formed simultaneously and essentially have the same material and the same doping concentration.

[0064] In some prior art, the upper part of the trench gate structure is filled with a capping layer, which is typically made of oxide or silicate glass. After the capping layer is formed, a planarization process is required to planarize its surface to facilitate subsequent processes. Compared to prior art, this disclosure utilizes the step of forming the second doped region 320 in the diode string DS to simultaneously form the second polysilicon structure 212, thereby replacing the capping layer and the step of forming the capping layer. This has the advantage of saving the step of forming the capping layer and the step of planarizing the capping layer. In addition, forming different components in the semiconductor structure 10 simultaneously in the same process is equivalent to integrating different steps together, reducing the complexity and cost of the manufacturing process.

[0065] Referring to Figure 19, a photoresist layer 507 is formed, and an ion implantation process is performed based on the photoresist layer 507 to form an N-type second lightly doped region 130 and an N-type first doped region 310. The area above the first lightly doped region 120 not covered by the photoresist layer 507 (i.e., the location of opening O8) is converted into the second lightly doped region 130. The area above the doped region 320 not covered by the photoresist layer 507 (i.e., the location of opening O9) is converted into the first doped region 310. Note that in the steps of Figure 19, the bottom surface of the first doped region 310 is higher than the bottom surface of the second doped region 320. After the ion implantation process, the photoresist layer 507 is removed.

[0066] Referring to Figure 20, a photoresist layer 508 is formed, and an ion implantation process is performed based on the photoresist layer 508 to form a P-type heavily doped region 140. The area above the first lightly doped region 120 not covered by the photoresist layer 508 (i.e., the location of the opening O10) is converted into the heavily doped region 140. In some embodiments, the molecular weight of the dopants in the second lightly doped region 130 is smaller than that of the dopants in the heavily doped region 140. Therefore, after the ion implantation process, the dopants in the heavily doped region 140 can be implanted to a shallower depth, making the bottom surface of the heavily doped region 140 higher than the bottom surface of the second lightly doped region 130. After the ion implantation process, the photoresist layer 508 is removed.

[0067] Referring to Figure 21, an annealing process is performed to bring the depths of the second lightly doped region 130, the heavily doped region 140, and the first doped region 310 closer to the substrate 100. After the annealing process, the depth of the first doped region 310 is brought closer to the substrate, and the first doped region 310 directly contacts the insulating layer 210, thereby forming the diode string DS. In some embodiments, after the annealing process, the bottom surface of the second lightly doped region 130 is coplanar with the bottom surface of the heavily doped region 140. In other embodiments, after the annealing process, the bottom surface of the heavily doped region 140 is closer to the substrate 100 than the bottom surface of the second lightly doped region 130.

[0068] Refer to Figure 22. An interlayer oxide layer 150 is formed to cover the structure in Figure 20.

[0069] Referring to Figure 23, a photoresist layer 509 is formed, and an etching process is performed on the photoresist layer 509 to remove a portion of the interlayer oxide layer 150. The photoresist layer 509 has openings O11, O12, O13, and O14, which define the positions of the source electrode 160, conductive plug 191, conductive plug 192, and conductive plug 194, respectively. After the etching process, the photoresist layer 509 is removed.

[0070] Referring to Figure 24, a barrier metal layer 195, conductive plugs 191 and 192, a metal layer, and conductive plugs 194 are formed. In some embodiments, before forming conductive plugs 191, 192, the metal layer, and 194, the barrier metal layer 195 is filled in openings O11, O12, O13, and O14. Next, an etching process is performed to remove a portion of the barrier metal layer 195. Since opening O11 has a smaller aspect ratio, most of the barrier metal layer 195 in opening O11 is removed, leaving only the barrier metal layer 195 on the sidewalls and bottom of opening O11. Because openings O12, O13, and O14 have larger aspect ratios, the barrier metal layer 195 in openings O12, O13, and O14 is not removed. In some embodiments, the barrier metal layer 195 in openings O12, O13 and O14 is not removed at all.

[0071] After forming the barrier metal layer 195, conductive plug 191, conductive plug 192, metal layer, and conductive plug 194, a metal layer is formed to cover the structure shown in FIG24. Next, a patterned photoresist is formed, and an etching process is performed on the patterned photoresist layer to remove a portion of the metal layer, thereby forming the semiconductor structure 10 shown in FIG2 and FIG4.

[0072] In other embodiments, the semiconductor structure 10 does not include a barrier metal layer 180.

[0073] It should be understood that the semiconductor structure 10 disclosed herein is not limited to the structure described above. For example, the second polysilicon structure 212 of the semiconductor structure 10 may be implemented in different shapes, which is also within the scope of this disclosure. Refer to Figures 25, 26, and 27. Figures 25, 26, and 27 are schematic diagrams of semiconductor structures 20, 30, and 40 according to other embodiments of this disclosure, respectively. For ease of understanding, the symbols in Figures 25, 26, and 27 are the same as those in Figures 1 to 4; however, this does not mean that elements using the same symbols must be identical.

[0074] Semiconductor structure 20 is largely similar to semiconductor structure 10, except for the second polysilicon structure 212. Specifically, the width (width along the X direction) of the gate structures G1~G4 in semiconductor structure 20 is smaller. Therefore, after the insulating layer 210 is formed, the gate structures G1~G3 are filled by the insulating layer 210, leaving no space to accommodate the second polysilicon structure 212. Thus, semiconductor structure 20 does not include the second polysilicon structure 212.

[0075] Semiconductor structure 30 is generally similar to semiconductor structure 10, except for the second polysilicon structure 212. Specifically, in semiconductor structure 30, the second polysilicon structure 212 has arc-shaped sidewalls adjacent to the insulating layer 210. Compared to semiconductor structure 10, the second polysilicon structure 212 of semiconductor structure 30 occupies a smaller volume. It should be understood that the cross-sectional profile of the second polysilicon structure 212 of semiconductor structure 30 is related to the spacing of gate structures G1~G4 and the aspect ratio of gate structures G1~G4. In some embodiments, the second polysilicon structure 212 of semiconductor structure 30 has a triangular cross-sectional profile. In some embodiments, the second polysilicon structure 212 of semiconductor structure 30 has a trapezoidal cross-sectional profile that gradually narrows towards the substrate 100. In some embodiments, the second polysilicon structure 212 of semiconductor structure 30 has a rectangular cross-sectional profile. In some embodiments, the second polysilicon structure 212 of semiconductor structure 30 has a semi-circular cross-sectional profile.

[0076] Semiconductor structure 40 is generally similar to semiconductor structure 10, except for the second polysilicon structure 212. Specifically, when forming the second polysilicon structure 212, polysilicon is filled into the openings O7 (see FIG. 14) of the gate structures G1-G3. However, the polysilicon is formed by anisotropic deposition, so after deposition, the top surface of the polysilicon has a depression that is generally similar to the opening O7. In semiconductor structure 40, the depression on the top surface of the second polysilicon structure 212 is used to accommodate a filling layer 214. In some embodiments, the filling layer 214 is an oxide, an insulator, or a barrier metal. It should be noted that although the top surface of the second polysilicon structure 212 has a filling layer 214, the second polysilicon structure 212 is still electrically coupled to and adjacent to the source electrode 160.

[0077] In this document, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “left,” and “right” may be used for ease of description to describe the relationship between one element or feature as shown in the accompanying drawings and one or more other elements or features. In addition to the orientation depicted in the accompanying drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or there may be an intermediate element present.

[0078] As used herein, the terms “approximately,” “substantially,” “basically,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation occurred precisely or instances where the event or situation was close to occurring. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. A range may be expressed herein as from one endpoint to another or between two endpoints. All ranges disclosed herein include endpoints unless otherwise specified. The term “substantially coplanar” may refer to two surfaces located along the same plane with a positional difference within several micrometers (μm), such as a positional difference within 10 μm, 5 μm, 1 μm, or 0.5 μm along the same plane. When a numerical value or characteristic is referred to as “substantially” the same, the term may refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of said values.

[0079] The foregoing summary outlines the features of several embodiments and detailed aspects of this disclosure. The embodiments described in this disclosure can readily serve as the basis for designing or modifying other processes and structures to achieve the same or similar purposes and / or realize the same or similar advantages of the embodiments described herein. Such equivalent constructions do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0080] 10: Semiconductor Structure 100: Base 110: Epitaxial layer 120: First lightly doped region 130: Second lightly doped region 140: Heavily doped region 150: Interlayer oxide layer 160: Source electrode 170: Gate electrode 180: Barrier Metal Layer 191: Conductive plug 192: Conductive plug 193: Metal layer 194: Conductive plug 195: Barrier Metal Layer 20: Semiconductor Structure 202: Gate oxide layer 204: First polycrystalline silicon structure 206: Thermal Oxidation Layer 208: Thermal Oxidation Layer 210: Insulation layer 212: Second polycrystalline silicon structure 214: Fill layer 30: Semiconductor Structure 310: First doped region 320: Second doped region 40: Semiconductor Structure 501: Oxide Hard Mask 502: Photoresist layer 503: Photoresist layer 504: Photoresist layer 505I: Polycrystalline silicon layer 505D: Polycrystalline silicon layer 506: Photoresist layer 507: Photoresist layer 508: Photoresist layer 509: Photoresist layer A-A': Line segment B-B': Line segment BS: Bottom D: Drain electrode DS: Diode string G: Gate electrode G1: Gate structure G2: Gate structure G3: Gate structure G4: Gate structure M: Transistor O1: Opening O2: Opening O3: Opening O4: Opening O5: Opening O6: Opening O7: Opening O8: Opening O9: Opening O10: Opening O11: Opening O12: Opening O13: Opening O14: Opening RG: Gate resistor S: Source electrode SS: Sidewall TH1: Thickness TH2: Thickness X: Direction Y: direction Z: Direction

Claims

1. A semiconductor structure comprising: a substrate; an epitaxial layer over the substrate, wherein the epitaxial layer has a doped region extending from the top of the epitaxial layer toward the substrate; A diode string, above the epitaxial layer, includes: A plurality of first doped regions having a first conductivity type, wherein a first conductive plug is adjacent to a first end of the plurality of first doped regions; The device comprises: a plurality of second doped regions having a second conductivity type, wherein the plurality of first doped regions and the plurality of second doped regions are alternately arranged; a gate structure, at least partially surrounded by the doped regions and extending into the epitaxial layer into the substrate, comprising: a first polysilicon structure; a gate oxide layer surrounding the polysilicon structure; an insulating layer above the first polysilicon structure and the gate oxide layer, extending between the doped regions and the diode string; a second polysilicon structure above the first polysilicon structure and the gate oxide layer and surrounded by the insulating layer, wherein the second polysilicon structure has the same doping concentration as the plurality of second doped regions; and a source structure adjacent to the doped regions and the second polysilicon structure, and electrically coupled to the diode string through a first conductive plug.

2. The semiconductor structure of claim 1, wherein the doped region comprises: a first lightly doped region; a second lightly doped region above the first lightly doped region; and a heavily doped region disposed on the first lightly doped region and surrounded by the second lightly doped region, wherein the source structure is adjacent to the second lightly doped region and the heavily doped region, and the doping concentration of the second lightly doped region is less than the doping concentration of the heavily doped region and greater than the doping concentration of the first lightly doped region.

3. The semiconductor structure as claimed in claim 2, wherein the second lightly doped region and the heavily doped region are electrically connected to a source electrode and together serve as the source structure.

4. The semiconductor structure of claim 1, wherein the gate structure further includes a thermal oxide layer, wherein the thermal oxide layer includes: a bottom portion above the first polysilicon structure; and a sidewall portion extending between the doped region and the insulating layer.

5. The semiconductor structure as claimed in claim 4, wherein the thickness of the insulating layer is greater than the thickness of the thermal oxide layer.

6. The semiconductor structure as claimed in claim 4, wherein the thickness of the bottom portion is greater than the thickness of the sidewall portion.

7. The semiconductor structure as claimed in claim 4, wherein the bottom portion does not contact the sidewall portion.

8. The semiconductor structure as claimed in claim 1, wherein the interface between each first doped region and the second doped region forms a PN junction.

9. The semiconductor structure of claim 1, wherein the second polysilicon structure has the second conductivity type.

10. The semiconductor structure as claimed in claim 1, wherein the plurality of second doped regions are composed of polysilicon.

11. The semiconductor structure as claimed in claim 1, further comprising: a gate electrode, electrically coupled to the first polysilicon structure above the diode string, and electrically coupled to a second end of the plurality of first doped regions via a second conductive plug.

12. The semiconductor structure of claim 1 further comprises: an intercalation oxide layer on the insulating layer, surrounding the source structure and the diode string, and covering the diode string.

13. The semiconductor structure of claim 1, wherein the thickness of the insulating layer on the first polysilicon structure is less than the thickness of the portion of the insulating layer extending between the doped region and the diode string.

14. The semiconductor structure of claim 13, wherein the thickness of the portion of the insulating layer extending between the doped region and the diode string is between approximately 300 angstroms and approximately 10,000 angstroms.

15. The semiconductor structure of claim 1, wherein the source structure comprises: a first conductive plug; a source electrode; a metal layer disposed on both sides of the source electrode; and a barrier metal layer surrounding the source electrode, the metal layer and the first conductive plug, and adjacent to the doped region, the second polysilicon structure and the diode string.

16. The semiconductor structure of claim 15, wherein the first conductive plug has the same material as the metal layer.

17. The semiconductor structure as claimed in claim 1, wherein the second polycrystalline silicon structure has a rectangular profile in a cross-sectional view.

18. The semiconductor structure of claim 1, wherein the second polycrystalline silicon structure has a triangular profile in a cross-sectional view.

19. The semiconductor structure of claim 1, wherein, in a cross-sectional view, the second polycrystalline silicon structure has arcuate sidewalls adjacent to the insulating layer.

20. A method of manufacturing a semiconductor structure, comprising: providing a substrate having an epitaxial layer thereon, wherein the epitaxial layer has a first lightly doped region extending from the top of the epitaxial layer toward the substrate; forming a trench extending from the top surface of the first lightly doped region toward the substrate beyond the first lightly doped region into the epitaxial layer; forming a gate oxide layer surrounding a first polysilicon structure in the trench; forming an insulating layer above the first polysilicon structure and the gate oxide layer, and extending to the top surface of the first lightly doped region; forming a polysilicon layer above the insulating layer, wherein the polysilicon layer fills the remaining space of the trench; A portion of the polycrystalline silicon layer is removed to simultaneously form a second polycrystalline silicon structure in the trench and a third polycrystalline silicon structure on the top surface of the first lightly doped region; a portion of the third polycrystalline silicon structure is converted into a plurality of first doped regions having a first conductivity type, while the remaining portion of the third polycrystalline silicon structure is a plurality of second doped regions having a second conductivity type, wherein the plurality of first doped regions and the plurality of second doped regions are alternately arranged to form a diode string, and the second polycrystalline silicon structure and the plurality of second doped regions have the same doping concentration; an interlayer oxide layer is formed on the insulating layer and the second polycrystalline silicon structure, surrounding and covering the diode string; And to form a source electrode that passes through the interlayer oxide layer and is adjacent to and electrically coupled to the second polycrystalline silicon structure.

21. The manufacturing method of claim 20, wherein the step of converting a portion of the third polycrystalline silicon structure into the plurality of first doped regions having the first conductivity type comprises performing an ion implantation process, wherein the step of performing the ion implantation process further converts a first portion of the first lightly doped region into a second lightly doped region, wherein the doping concentration of the second lightly doped region is greater than the doping concentration of the first lightly doped region.

22. The manufacturing method of claim 21 further comprises: converting a second portion of the first lightly doped region into a heavily doped region, wherein the heavily doped region is surrounded by the second lightly doped region, and the top surface of the heavily doped region is coplanar with the top surface of the second lightly doped region.

23. The manufacturing method of claim 22, wherein the doping concentration of the heavily doped region is greater than the doping concentration of the second lightly doped region, wherein the second lightly doped region has the first conductivity type, and the heavily doped region and the first lightly doped region have the second conductivity type.

24. The manufacturing method as claimed in claim 22, wherein the source electrode is adjacent to the second lightly doped region and the heavily doped region.

25. The manufacturing method of claim 20 further comprises: forming a gate electrode over the interlayer oxide layer, wherein the source electrode is electrically coupled to a first end of the plurality of first doped regions, and the gate electrode is electrically coupled to a second end of the plurality of first doped regions.

26. The manufacturing method of claim 20, wherein the step of removing a portion of the polycrystalline silicon layer includes performing an anisotropic etching process, wherein performing the anisotropic etching process further removes a portion of the insulating layer.

27. The manufacturing method as claimed in claim 26, wherein after performing the anisotropic etching process, the thickness of the insulating layer under the third polysilicon structure is greater than the thickness of the insulating layer not covered by the third polysilicon structure.

28. The manufacturing method of claim 20 further comprises: performing a thermal oxidation process prior to forming the insulating layer to form a thermal oxide layer on the first polycrystalline silicon structure and on the first lightly doped region.

29. The manufacturing method of claim 28, wherein the step of performing the thermal oxidation process includes: consuming a portion of the first polycrystalline silicon structure to form a bottom portion of the thermal oxide layer; and consuming a portion of the first lightly doped region to form a sidewall portion of the thermal oxide layer.

30. The manufacturing method as claimed in claim 29, wherein the bottom portion does not contact the sidewall portion, and the insulating layer is at least partially not covered by the thermal oxidation layer.

31. The manufacturing method as claimed in claim 28, wherein the insulating layer is formed in a manner different from the thermal oxidation process.

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