Stacked integrated circuit device including a stiffener die
TW202641363APending Publication Date: 2026-10-01QUALCOMM INC
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Patent Information
- Application Number
- TW114147315
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-05-21
- Filing Date
- 2025-12-03
- Publication Date
- 2026-10-01
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Figure TWG2TA001078648_001 
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Figure TWG2TA001078648_003
Abstract
A package includes a first die, a second die, and a third die. The first die includes first active circuitry, and a first plurality of conductive vias (CVs) that has a first pitch. The second die includes second active circuitry proximate to a first side of the second die. The second active circuitry includes metal layers and a second plurality of CVs that extends from a second side of the second die to one or more of the metal layers. The second plurality of CVs has a second pitch greater than the first pitch. The third die includes a third plurality of CVs to electrically couple the second active circuitry to a substrate. The third plurality of CVs has a third pitch greater than the first pitch. The second die is disposed between the first die and the third die.
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