Semiconductor devices and forming method thereof

TW202641379APending Publication Date: 2026-10-01TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD +1
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Patent Information

Application Number
TW114118052
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2025-03-28
Filing Date
2025-05-14
Publication Date
2026-10-01

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    Figure TWG2TA001078134_003
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Abstract

A structure has a conductive via connecting a RDL and an interconnect structure and a method of forming the structure. The structure can include a conductive line in a substrate and a dielectric layer on the conductive line. The structure can further include the conductive via through the dielectric layer and in contact with the conductive line. The conductive via can include a first barrier layer on a side surface of the dielectric layer, a seed layer on the first barrier layer, and a conductive layer surrounded by the seed layer. Top surfaces of the conductive via and the dielectric layer can be substantially coplanar. The structure can further include a second barrier layer on the conductive via and the dielectric layer and a redistribution line (RDL) on the second barrier layer. The RDL can have a substantially even top surface free from irregular concave shapes.
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