Inkjet chip structure
Patent Information
- Application Number
- TW114113624
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-04-10
- Publication Date
- 2026-10-16
- Estimated Expiration
- 2045-04-09
Smart Images
Figure TWG2TA001080249_001 
Figure TWG2TA001080249_002 
Figure TWG2TA001080249_003
Abstract
Claims
1. An inkjet chip structure, comprising: An inkjet chip includes a plurality of droplet generators, an identification circuit, and at least one ink supply channel. The at least one ink supply channel and the identification circuit are disposed on the top surface of the inkjet chip. The plurality of droplet generators are disposed on the inkjet chip adjacent to the at least one ink supply channel. An orifice plate has a light-transmitting area made of a light-transmitting material and an opaque area made of an opaque material, wherein the opaque material includes an opaque plastic material. The orifice plate is disposed on the top surface of the inkjet chip and has a plurality of orifices. The plurality of orifices are formed on the orifice plate and are opposite to the droplet generators. The light-transmitting area of the orifice plate is correspondingly disposed on the orifice plate without the identification circuit, and the opaque area of the orifice plate is correspondingly disposed above the identification circuit of the inkjet chip to prevent external light sources from illuminating the identification circuit. Each orifice has an opaque orifice inner side.
2. The inkjet wafer structure as described in claim 1, wherein the nozzle sheet has an opaque upper side and an opaque lower side opposite to the opaque upper side, the opaque lower side of the nozzle sheet being attached to the top surface of the inkjet wafer to block light from passing through the nozzle sheet.
3. The inkjet chip structure as described in claim 2, wherein the identification circuit includes multiple memory units, the opaque area of the nozzle sheet is disposed above the identification circuit and the multiple memory units of the inkjet chip, and the multiple memory units have a transistor, which is an erasable and programmable unique memory (EPROM).
4. The inkjet chip structure as described in claim 3, wherein the multiple memory cells have a fuse, the fuse and the transistor are disposed in the identification circuit, and the transistor is an erasable and programmable unique memory (EPROM).
5. The inkjet chip structure as described in claim 3, wherein the plurality of memory cells has an antifuse, the antifuse and the transistor are disposed in the identification circuit, and the transistor is an erasable and programmable unique memory (EPROM).
6. The inkjet chip structure as described in claim 4, wherein the plurality of memory cells further comprises an antifuse, the antifuse, the fuse and the transistor are disposed in the identification circuit, and the transistor is an erasable and programmable unique memory (EPROM).
7. The inkjet chip structure as described in claim 1, wherein the opaque material comprises an opaque metallic material.
8. The inkjet wafer structure as claimed in claim 1, wherein each nozzle has an opaque nozzle inner side formed on the inner peripheral surface of the nozzle.
9. The inkjet chip structure as described in claim 1, wherein each ink droplet generator comprises a chip substrate, a thermal barrier layer, a heating resistor layer, a conductive layer, a protective layer and a barrier layer, wherein the chip substrate, the thermal barrier layer, the heating resistor layer, the conductive layer, the protective layer and the barrier layer are stacked, and the barrier layer has an ink supply chamber therein, the ink supply chamber being respectively connected to the nozzle and the ink supply channel of the opposite nozzle plate.