Circuit testing method and circuit testing system

Abstract

A circuit testing method including: obtaining a test data of an integrated circuit, wherein the test data is configured to record at least one test feature of multiple logic circuits and multiple memory circuits when performing a scan test; analyzing the test data to cluster each of the memory circuits into one of multiple test groups, wherein multiple first memory circuits of the memory circuits is clustered into a first test group of the test groups; and generating a test signal and multiple control signals according to a clustering result of the memory circuits and the test data. The test signal is configured to perform the scan test on the integrated circuit. The control signals are comfigured to control the first memory circuits, so that when performing the scan test, the number of the first memory circuits enabled simultaneously is limited to be lower than a first enabling upper limit.

Description

[Technical Field]

[0001] This disclosure relates to the testing of integrated circuits, and in particular to a circuit testing method and a circuit testing system. [Previous Technology]

[0002] Scan test is a testing technique applied to integrated circuits (ICs) to detect whether there are abnormal or damaged logic circuits in the integrated circuit. As the complexity of chip design increases, the detection process of identifying potential defects in integrated circuits through scan test is becoming increasingly important and has become a necessary step to ensure circuit reliability and performance. [Summary of the Invention]

[0003] This disclosure relates to a circuit testing method, comprising: acquiring test data of an integrated circuit, wherein the integrated circuit includes a plurality of logic circuits and a plurality of memory circuits, and the test data is used to record at least one test characteristic of the logic circuits and the memory circuits during scan testing; analyzing the test data to classify each of the memory circuits into one of a plurality of test groups, wherein a plurality of first memory circuits of the memory circuits are classified into a first test group among the test groups; and generating test signals and a plurality of control signals based on the classification results of the memory circuits and the test data. The test signals are used to perform scan testing on the integrated circuit. The control signals are used to control the first memory circuits so that, during scan testing, the number of first memory circuits simultaneously enabled is limited to below a first enable limit.

[0004] This disclosure also relates to a circuit testing system comprising a plurality of memory circuits, a plurality of logic circuits, and a plurality of control circuits. The memory circuits are categorized into one of a plurality of test groups, wherein a plurality of first memory circuits of the memory circuits are categorized into a first test group within the test groups. The logic circuits are coupled to the memory circuits. The control circuits are coupled to the memory circuits, wherein each of the control circuits selectively enables or disables a corresponding one of the memory circuits. During a scan test, the control circuits receive multiple control signals to control the number of first memory circuits simultaneously enabled to be below a first enable limit.

[0005] This disclosure also relates to a circuit testing method, comprising: acquiring test data of an integrated circuit, wherein the integrated circuit includes a plurality of logic circuits and a plurality of memory circuits, and the test data is used to record at least one test feature of the integrated circuit during scan testing; classifying each of the memory circuits into one of a plurality of test categories according to the test data, wherein a portion of the memory circuits belonging to the same time domain is classified into the same category of the test categories; classifying each of the memory circuits into one of a plurality of test groups according to the test data and the test categories; and generating control signals corresponding to the memory circuits according to the test data and the test groups, so as to selectively control the operating state of the memory circuits according to the control signals during scan testing.

[0006] Accordingly, by analyzing the test characteristics of integrated circuits and scanning tests, and classifying memory circuits to control the number of memory circuits that are enabled at the same time, the test results can be retrieved using the existing memory circuits in the integrated circuits.

Implementation Method

[0007] Several embodiments of the present invention will be disclosed below with reference to the drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details are not intended to limit the present invention. That is, in some embodiments of the present invention, these practical details are not essential. In addition, for the sake of simplicity, some conventional structures and elements will be shown in the drawings in a simple schematic manner.

[0008] In this document, when an element is referred to as a "connection" or "coupled," it may mean an "electrical connection" or "electrical coupling." "Connection" or "coupled" may also be used to indicate that two or more elements operate or interact with each other. Furthermore, although terms such as "first," "second," etc., are used herein to describe different elements, these terms are only used to distinguish elements or operations described using the same technical terms. Unless the context clearly indicates otherwise, these terms do not specifically refer to or imply order or sequence, nor are they intended to limit the invention.

[0009] This disclosure relates to a circuit testing system and method for integrated circuits, used to perform scan tests on integrated circuits. To facilitate understanding of the application of this disclosure, the operation of the scan test will be explained below using the integrated circuit 100 shown in Figure 1 as an example.

[0010] Please refer to Figure 1. The integrated circuit 100 includes a plurality of logic circuits and a plurality of memory circuits. The logic circuits, as shown in Figure 1 (110A to 110D), include one or more logic elements. Depending on the function of different circuits, the composition and circuit architecture of the logic circuits will also be different. Since those skilled in the art can understand the meaning of the logic circuits here, they will not be described in detail here.

[0011] The memory circuits RG11-RG13 and 120, as shown in Figure 1, can be implemented using flip-flops (such as D-type flip-flops). For the purpose of describing the implementation of this disclosure in subsequent paragraphs, they are referred to by different numbers here. Taking memory circuit 120 as an example, it has an input terminal D, an input terminal WE, an enable control terminal CE, and a read / write control terminal RWM (read / write margin). The input terminal D, the input terminal WE, and the read / write control terminal RWM are coupled to logic circuits 110A, 110C, and 110D, respectively, and the output terminal of memory circuit 120 is coupled to logic circuit 110B.

[0012] Scan test is a technique used to test whether there are circuit abnormalities in integrated circuits. In one embodiment, a test signal Spt (Pattern) is generated by a processing circuit 140 as input data during the scan test. The processing circuit 140 can generate the test signal Spt using Automatic Test Pattern Generation (ATPG) technology. Here, "processing circuit" can be a test machine, a signal processor, or a computer device used to generate signals, and this disclosure is not limited thereto.

[0013] For ease of understanding, the scanning test process is described below. Taking Figure 1 as an example, if the target of the scanning test is logic circuit 110A, during the scanning test, a corresponding bypass logic RG14 (such as a temporary register) needs to be configured between logic circuit 110A and memory circuit 120 to read the scanning test results.

[0014] The scanning test process includes shift mode and capture mode. In shift mode, the test signal Spt is input to the logic circuit 110A one by one through a register according to the clock signal. This process of inputting data with pulses is called "shift". In capture mode, the clock signal is stopped, and after the logic circuit 110A completes the corresponding logic operation, the clock signal is restored so that the operation result of the logic circuit 110A is output to the bypass logic RG14. This process of outputting the result to the bypass logic RG14 after operation is called "capture".

[0015] However, in some integrated circuit products, bypass logic may not be possible due to design reasons (e.g., insufficient space), making it impossible to execute scan tests smoothly. Referring to Figure 1, although there is a memory circuit 120 between logic circuits 110A and 110B that is not used during scan testing, the memory circuit 120 is not suitable for recording the scan test results. This is because if multiple memory circuits 120 within the integrated circuit 100 are simultaneously enabled to record test results during scan testing, the current will increase significantly, leading to a corresponding increase in the voltage across the electronic components within the integrated circuit 100. As a result, unstable power supply may cause some electronic components to malfunction or become abnormal, a phenomenon known as the "IR-drop problem."

[0016] This disclosure describes the configuration of a control circuit 130 (e.g., an enable control terminal CE coupled to the memory circuit 120) in the integrated circuit 100 to control the memory circuit 120. By controlling the enable or disable time of the memory circuit 120, the memory circuit 120 can be used to record the results of the scan test. Accordingly, not only is there no need to configure additional bypass logic, but there is also no need to worry about IR-drop problems.

[0017] Specifically, when the processing circuit 140 generates the test signal Spt, it also generates a corresponding control signal Sctr for each control circuit 130 based on the limitation data Scon, so as to set the operating state (i.e., enable or disable) of the memory circuit 120 by changing the logic level of the enable control terminal CE. The definition and generation method of the limitation data Scon will be described in detail in subsequent paragraphs.

[0018] Figure 2 is a schematic diagram of a circuit test system 200 according to some embodiments of the present disclosure. The circuit test system 200 can be applied to the integrated circuit shown in Figure 1. Since the embodiment described in Figure 2 does not change the operation of "logic circuits 110A and 110C receiving test signal Spt to perform scan test" in Figure 1, the logic circuits coupled to input terminal D, input terminal WE and corresponding logic circuits in Figure 1 are omitted in Figure 2 to keep the diagram simple for explanation. The memory circuit 220 can be the memory circuit 120 shown in Figure 1. The control circuit 230 can be the control circuit 130 shown in Figure 1.

[0019] The circuit testing system 200 includes a plurality of logic circuits (only 110D and 110E are shown in Figure 2), a memory circuit (only 220 is shown in Figure 2), and a control circuit (only 230 is shown in Figure 2). In this embodiment, the read / write control terminal RWM of the memory circuit 220 is coupled to the logic circuit 110D and the setting circuit 211 respectively through the multiplexer MUX 21. The setting circuit 211 is used to provide read / write setting signals to set the speed at which the memory circuit 220 operates in the read or write state.

[0020] The control circuit 230 includes a temporary register 231, a multiplexer MUX 22, and multiple logic gates LG21 to LG23 (such as AND gates and inverters as shown in Figure 2). Logic gates LG21 to LG23 are used to receive the enable signal Scan (scan_enable) and the mode signals Sm1 / Sm2 respectively, so as to selectively change the level of the output signal of the control circuit 230, thereby controlling the enable or disable of the memory circuit 220. The "enable signal Scan" and the "mode signals Sm1 / Sm2" can be the aforementioned "control signal Sctr" or at least a part thereof.

[0021] Please refer to the table below for the signal status of the circuit test system 200 in different modes ("X" represents "irrelevant condition"). The "functional mode" refers to the normal operation of the integrated circuit, rather than the operation state when performing a scan test. model Signal Sm1 Signal Sm2 Signal Scen Functional mode X 0 0 Displacement mode X 1 1 Extraction mode 1 1 0

[0022] As shown in the table above, in functional mode, the multiplexer MUX22 selects the signal of logic circuit 110E as the output signal. Therefore, the circuit test system 200 is not performing a scan test at this time. In shift mode, since the enable signal Scen is "1", after being inverted by logic gate LG21, the level of the output signal of logic gate LG22 is "0", and the memory circuit 220 will be disabled at this time. On the other hand, in fetch mode, the level of the output signal of logic gate LG22 is "1", and the memory circuit 220 will be enabled at this time. It should be noted that the circuit of control circuit 230 is not limited to this, and the circuit shown in Figure 2 is only one embodiment.

[0023] This disclosure generates a test signal Spt and multiple control signals Sctr corresponding to multiple memory circuits based on the test data of the integrated circuit. The control circuit 230 selectively controls the operating state of the memory circuit 220 during scan testing based on the corresponding control signal Sctr, such as: read / write disabled, read state, or write state. The aforementioned "test data" includes records of at least one test characteristic during scan testing, which reflects the circuit characteristics or configuration of the integrated circuit (e.g., logic circuit or memory circuit). In some embodiments, the "test data" may include one or more of the following four:

[0024] (1) Netlist data: Netlist data is used to record the connection relationships between multiple logic circuits and multiple memory circuits in an integrated circuit. Specifically, netlist data records the electrical connection relationships between circuit elements in a specific format, such as including the identifiers of electronic components.

[0025] (2)Constraint Data (Synopsys Design Constraints, SDC): Constraint data is used to record the clock speed of the integrated circuit. Specifically, constraint data uses a special data format to record the operating characteristics of each logic circuit in the integrated circuit to ensure that the circuit can achieve the expected performance when it is running.

[0026] (3) Library: The library is used to record the logic characteristics and / or power consumption of these memory circuits and various logic circuits, such as the circuit composition and operating characteristics of a variety of different logic elements.

[0027] (4)Design Exchange Format (DEF): Used to record the layout structure of the integrated circuit. Specifically, the format data uses a special format to describe the physical design of the integrated circuit, to record the layout design, component positions, connection paths, etc. of the integrated circuit.

[0028] In this embodiment, the circuit testing system 200 includes a processing circuit 240 for acquiring test data (e.g., coupled to integrated circuits for detection, or input by testers), and classifying each memory circuit 220 into one of a plurality of "test categories" and / or grouping it into one of a plurality of "test groups" based on the test data. Based on the analysis results of the classification and grouping, the processing circuit 240 first generates constraint data Scon, and then generates the test signal Spt required for the scan test, as well as the control signal Sctr provided to each control circuit 230. In other embodiments, the test data can also be acquired by another processor first, and the constraint data Scon can be generated before being input to the processing circuit 240 to generate the test signal Spt and the control signal Sctr.

[0029] As mentioned above, the aforementioned "classification" and "grouping" actions are based on whether multiple memory circuits need to operate simultaneously during scan testing. For example, it determines whether the operation of the logic circuits corresponding to multiple memory circuits is related, whether they belong to the same scan chain, or whether they use the same clock domain signal. Therefore, memory cells that need to operate simultaneously during scan testing (e.g., belonging to the same clock domain) to record test results will be assigned to the same test category.

[0030] Conversely, memory cells that do not need to operate simultaneously to record test results during scan testing will be grouped into the same test group. It should be noted that, in one embodiment, the same test group may contain a certain number of memory circuits that "operate simultaneously," this number is referred to herein as the "enabling limit." In other words, the number of memory circuits simultaneously enabled in the same test group will be controlled to be below the enabling limit. For example, the first test group contains 30 first memory circuits, and the first enabling limit of the first test group is "2." During scan testing, the control circuit will control that at most 2 of these first memory circuits will be enabled simultaneously according to the control signal Sctr. The "enabling limit" will be determined based on the power supply capacity or power consumption limitations of the integrated circuit, for example, it may be one, two, or five, but this disclosure is not limited to these numbers.

[0031] The control signal generated in the aforementioned manner can control the number of memory circuits that are enabled simultaneously during the scan test, thus avoiding the IR-drop problem caused by the current increase due to the simultaneous enabling of multiple memory circuits. Accordingly, the memory already configured in the integrated circuit can be used as a temporary register during the scan test without the need to configure bypass logic separately.

[0032] Figure 3 shows a flowchart of a circuit testing method according to a partial embodiment of the present disclosure, which can be applied to the integrated circuit 100 in Figure 1 or the circuit testing system 200 shown in Figure 2. The operational concept of the present disclosure is explained here using a flowchart as an example. In step S301, the processing circuit 240 first obtains the test data of the integrated circuit. As mentioned above, the test data may include one or more of the following: netlist data, constraint data, cell library data, and format data of the integrated circuit.

[0033] In step S302, the processing circuit 240 analyzes the test characteristics in the test data to classify the multiple memory circuits into one of the multiple test categories. As mentioned above, memory cells that need to operate simultaneously during the scan test (e.g., belonging to the same time domain) to record test results will be assigned to the same test category.

[0034] In step S303, the processing circuit 240 analyzes the test characteristics in the test data and, based on the classification results in step S302, further groups the multiple memory circuits into one of the multiple test groups. In one embodiment, the memory circuits in the same test group may all be "not required to operate simultaneously during scan testing," for example, multiple memory circuits belonging to different time domains (i.e., a portion of all memory circuits) may be grouped into the same test group. In another embodiment, the memory circuits in the same test group must meet the requirement that "the number of circuits simultaneously enabled during scan testing is less than the enable limit."

[0035] In step S304, based on the test data and analysis results (i.e., classification results and / or grouping results), the processing circuit 240 will generate restriction data Scon. Specifically, the processing circuit 240 can analyze the memory enable limit of each test group according to the physical region corresponding to the test group (i.e., the layout position in the integrated circuit), and then generate restriction data Scon based on the test data, analysis results, and / or memory enable limit.

[0036] In step S305, the processing circuit 240 generates a test signal Spt for performing a scan test and a control signal Sctr provided to each control circuit according to the restriction data Scon.

[0037] In step S306, the integrated circuit performs a scan test according to the test signal Spt and the control signal Sctr. For example, the test signal Spt is provided to the logic circuit 110A shown in Figure 1, and the control signal Sctr is provided to the control circuit 130 shown in Figure 1. Specifically, in the shift mode of the scan test, the control circuit disables the corresponding memory circuit according to the clock signal corresponding to each memory circuit. In the retrieval mode of the scan test, the control circuit enables the corresponding memory circuit according to the clock signal corresponding to each memory circuit to obtain the scan test result.

[0038] It should be noted that, in the flowchart of Figure 3, the actions performed by the processing circuit can be performed by different devices; that is, the processing circuit 140 is not limited to a single circuit device. For example, the processing circuit 140 includes a first device and a second device. The first device generates limit data Scon, and the second device generates a test signal Spt and a control signal Sctr based on the limit data Scon.

[0039] The operation of this disclosure is explained from different perspectives. Please refer to Figure 4A, which is a schematic diagram of the operation of the processing circuit 400 according to a partial embodiment of this disclosure. The processing circuit 400 can be used to implement the processing circuit 140 of Figure 1 or the processing circuit 240 of Figure 2. The processing circuit 400 is used to execute the data creation procedure 410 to generate analysis results and execute the memory classification procedure 420 to generate restriction data Scon.

[0040] As shown in Figure 4A, the data creation program 410 includes clock analysis 411 and memory feature analysis 412. During clock analysis 411, the processing circuit 400 receives netlist data Dde and constraint data Dsdc to analyze the test modes corresponding to multiple memory circuits, or to analyze the time domain of multiple clock signals corresponding to memory circuits.

[0041] During memory feature analysis 412, the processing circuit 400 receives cell library data Dlib and format data Ddef to obtain the circuit characteristics of the integrated circuit. Specifically, the processing circuit 400 can analyze the layout design, component positions, and connection paths of the integrated circuit as a basis for subsequent classification or grouping. The processing circuit 400 records the analysis data generated by clock analysis 411 and memory feature analysis 412 into the database DB.

[0042] The memory classification program 420 includes memory classification 421, memory grouping 422, and restriction data generation 423. During memory classification 421, the processing circuit 400 classifies the memory circuits based on the analysis data obtained by the data creation program 410. Specifically, the processing circuit 400 classifies the memory circuits into various test categories based on the time domain or test mode of the clock signal corresponding to the memory circuit. For example, memory circuits belonging to the same time domain (i.e., a portion of the memory circuits) are classified into the same test category.

[0043] During memory clustering 422, the processing circuit 400 clusters the memory circuits based on test data, analysis data obtained from the data creation procedure 410, and classification results. Specifically, in one embodiment, the processing circuit 400 classifies the memory circuits into various test groups based on their physical location within the integrated circuit. In another embodiment, the processing circuit 400 classifies memory circuits belonging to different time domains (i.e., another portion of the memory circuits) into the same test group based on the classification results (i.e., test categories) from memory classification 421. The aforementioned classification and clustering results can be recorded in the regression model RM in the processing circuit 400 to record and update the analysis results each time.

[0044] During the restriction data generation 423, the processing circuit 400 generates restriction data based on the aforementioned classification and grouping results. This restriction data will then be used to generate test signals and control signals. In other words, the test signals and control signals used in the scan test can be generated based on characteristics such as the physical location, time domain, or test mode of the memory circuit.

[0045] For ease of understanding, the classification and grouping method is illustrated here with a schematic diagram of Figure 4B. In one embodiment, the integrated circuit includes multiple memory circuits M41 to M45. During the aforementioned "memory classification 421", the processing circuit 400 classifies the memory circuits M41 to M45 into multiple test categories C41 to C43 according to the time domain or test mode of the clock signal. For example, the clock signals corresponding to memory circuits M41 and M42 are in the same time domain, so they will be classified into the same test category C41.

[0046] Continuing from the above, during the aforementioned "memory grouping 422", the processing circuit 400 further groups the memory circuits M41 to M45 according to the classification results. That is, it controls the number of memory circuits that are enabled simultaneously in the same test group. As shown in Figure 4B, the memory circuits M41 to M45 will be grouped into multiple test groups G41 to G42, and in each test group, no multiple memory circuits will be enabled simultaneously.

[0047] The control circuit of this disclosure can be adjusted according to design requirements and is not limited to the circuit architecture in Figure 2 above. Please refer to Figure 5, which is a schematic diagram of a circuit test system 500 according to another embodiment of this disclosure. The circuit test system 500 includes a logic circuit 510, a memory circuit 520, and a control circuit 530. The logic circuit and the control circuit 530 are respectively coupled to different input terminals or control terminals of the memory circuit 520. Similar to Figure 2, the circuit test system 500 in Figure 5 can be applied to the integrated circuit shown in Figure 1. Since the embodiment in Figure 5 does not change the operation mode and circuit of "the logic circuit 110A under test receiving the test signal Spt", some circuits are omitted in Figure 5, and the focus is on the relative relationship of the enable control terminal CE of the control circuit 530 and the memory circuit 520.

[0048] As shown in Figure 5, the control circuit 530 includes a mode control circuit 530A and an enable control circuit 530B. The mode control circuit 530A is coupled to the enable control terminal CE of the memory circuit via the enable control circuit 530B, and is used to selectively enable or disable a corresponding memory circuit (i.e., memory circuit 520). Specifically, the mode control circuit 530A includes at least one logic element (e.g., a gate) and is used to receive multiple control signals, such as mode signals Sm1 / Sm2 and enable signals Scen, to generate an enable control signal.

[0049] The enable control circuit 530B is coupled to the enable control terminal CE of the mode control circuit 530A and the memory circuit 520, and includes a register 531, a logic element 532, and a multiplexer 533. The register 531 receives the input signal SI and the enable signal SE, and outputs the stored data according to the clock signal CK. The logic element 532 receives the stored data output by the register 531 and the enable control signal generated by the mode control circuit 530A. The multiplexer 533 is coupled to the logic circuit 510 and the logic element 532, and outputs the signal provided by the logic circuit 510 or the logic element 532 according to the scan mode signal Smd, so as to selectively set the memory circuit 520 to read mode or write mode.

[0050] In one embodiment, the logic circuit architecture within the control circuit can be determined according to the type of memory circuit. For example, the logic elements required for the control circuit can be determined based on the analysis results of the aforementioned data creation program 410.

[0051] In some embodiments, by using the existing memory circuitry within the integrated circuit as the memory for reading the test results of the scan test, the coverage of the scan test can be improved, and the problem of voltage drop (IR-drop) affecting the circuit performance can be effectively avoided. Accordingly, not only can the coverage of the scan test be improved, but the circuit layout cost during the scan test can also be reduced.

[0052] The various elements, method steps or technical features in the foregoing embodiments can be combined with each other, and are not limited to the order of textual description or graphical presentation in this disclosure.

[0053] Although the present disclosure has been disclosed above with reference to embodiments, it is not intended to limit the present disclosure. Anyone skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the claims defined in the appended patent application. [Simplified Explanation of the Diagram]

[0054] Figure 1 is a schematic diagram of an integrated circuit according to some embodiments of the present disclosure. Figure 2 is a schematic diagram of a circuit testing system according to some embodiments of the present disclosure. Figure 3 is a flowchart of a circuit testing method according to some embodiments of the present disclosure. Figure 4A is a schematic diagram of the operation mode of a processing circuit according to some embodiments of the present disclosure. Figure 4B is a schematic diagram of the classification and grouping method according to some embodiments of the present disclosure. Figure 5 is a schematic diagram of a circuit testing system according to some embodiments of the present disclosure. [Biomaterial Storage]

[0056] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A circuit testing method, comprising: acquiring test data of an integrated circuit, wherein the integrated circuit includes a plurality of logic circuits and a plurality of memory circuits, and the test data is used to record at least one test characteristic of the logic circuits and the memory circuits during a scan test; analyzing the test data to classify each of the memory circuits into one of a plurality of test groups, wherein a plurality of first memory circuits of the memory circuits are classified into a first test group among the test groups; and generating a test signal and a plurality of control signals based on a classification result of the memory circuits and the test data, wherein the test signal is used to perform the scan test on the integrated circuit, and the control signals are used to control the first memory circuits such that, during the scan test, the number of first memory circuits simultaneously enabled is limited to below a first enable limit.

2. The circuit testing method as claimed in claim 1, wherein the method of analyzing the test data to classify each of the memory circuits into one of the test groups further comprises: classifying each of the memory circuits into one of the test groups based on a plurality of physical locations of the memory circuits.

3. The circuit testing method as described in claim 1, wherein the method of analyzing the test data to classify each of the memory circuits into one of the test groups further comprises: analyzing a plurality of time-domain or a plurality of test modes corresponding to the memory circuits based on a netlist or a constraint data.

4. The circuit testing method as described in claim 3, wherein the method of analyzing the test data to classify each of the memory circuits into one of the test groups further comprises: classifying a portion of the memory circuits belonging to the same time domain into the same one of a plurality of test categories.

5. The circuit testing method as described in claim 4, wherein the method of analyzing the test data to classify each of the memory circuits into one of the test groups further comprises: classifying another portion of the different memory circuits belonging to the time domains into the same portion of the test groups according to the test categories.

6. The circuit testing method as described in claim 1, wherein the method for obtaining the test data of the integrated circuit comprises: obtaining one or more of a netlist, constraint, cell library, and format data of the integrated circuit; wherein the netlist is used to record the connection relationships between the logic circuits and the memory circuits; wherein the constraint is used to record the clock of the integrated circuit; wherein the cell library is used to record the logic characteristics or power consumption of the memory circuits; and wherein the format data is used to record the layout structure of the integrated circuit.

7. The circuit testing method as described in claim 1 further comprises: analyzing a plurality of memory enable limits for the plurality of physical regions corresponding to the test groups, wherein the memory enable limits include the first enable limit; and generating a restriction data based on the memory enable limits, the classification result, and the test data to generate the control signals.

8. The circuit testing method as described in claim 1 further comprises: disabling the memory circuits according to a plurality of clock signals corresponding to the memory circuits in a shift mode of the scan test; and enabling the memory circuits according to the clock signals corresponding to the memory circuits in a capture mode of the scan test.

9. A circuit testing system comprising: a plurality of memory circuits classified into one of a plurality of test groups, wherein a plurality of first memory circuits of the memory circuits are classified into a first test group of the test groups; a plurality of logic circuits coupled to the memory circuits; and a plurality of control circuits coupled to the memory circuits, wherein each of the control circuits selectively enables or disables a corresponding one of the memory circuits; wherein during a scan test, the control circuits are configured to receive a plurality of control signals to control the number of first memory circuits simultaneously enabled to be less than a first enable limit.

10. The circuit testing system as claimed in claim 9 further includes a processing circuit that generates the control signals based on a plurality of physical locations of the memory circuits.

11. The circuit testing system as described in claim 9 further includes a processing circuit for generating the control signals and for analyzing, based on a netlist or constraint data, a plurality of time-domain or a plurality of test modes corresponding to the memory circuits.

12. The circuit test system as claimed in claim 11, wherein the processing circuit is further configured to: classify portions of the memory circuits belonging to the same time domain into the same of a plurality of test categories.

13. The circuit testing system as claimed in claim 12, wherein the processing circuitry is further configured to: classify another portion of the memory circuits belonging to the different time domains into the same group of tests, based on the test categories.

14. The circuit testing system as claimed in claim 9 further includes a processing circuit for: analyzing a plurality of memory enable limits for the plurality of physical regions corresponding to the test groups, wherein the memory enable limits include the first enable limit; and generating a restriction data based on the memory enable limits to generate the control signals.

15. The circuit testing system as claimed in claim 9 further comprises: a processing circuit for acquiring one or more of a netlist data, a constraint data, a cell library data, and a format data of the logic circuits and the memory circuits to generate the control signals; wherein the netlist data is used to record the connection relationships between the logic circuits and the memory circuits; wherein the constraint data is used to record the clock speeds of the logic circuits and the memory circuits; wherein the cell library data is used to record the logic characteristics or power consumption of the memory circuits; and wherein the format data is used to record the layout structure of the logic circuits and the memory circuits.

16. The circuit testing system as claimed in claim 9, wherein in a displacement mode of the scan test, the control circuit is configured to disable the memory circuits according to a plurality of clock signals corresponding to the memory circuits; and in a capture mode of the scan test, the control circuit is configured to enable the memory circuits according to the clock signals corresponding to the memory circuits.

17. The circuit testing system as claimed in claim 9, wherein each of the control circuits comprises: an enable control circuit coupled to a corresponding one of the memory circuits for selectively enabling or disabling a corresponding one of the memory circuits; and a mode control circuit coupled to a corresponding one of the memory circuits for selectively setting the corresponding one of the memory circuits to a read mode or a write mode.

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