Circuit testing method and circuit testing system

Abstract

A circuit testing method including: obtaining a test data of an integrated circuit, wherein the test data is configured to record at least one test feature of multiple logic circuits and multiple memory circuits when performing a scan test; analyzing the test data to cluster each of the memory circuits into one of multiple test groups, wherein multiple first memory circuits of the memory circuits is clustered into a first test group of the test groups; and generating a test signal and multiple control signals according to a clustering result of the memory circuits and the test data. The test signal is configured to perform the scan test on the integrated circuit. The control signals are configured to control the first memory circuits, so that when performing the scan test, the number of the first memory circuits enabled simultaneously is limited to be lower than a first enabling upper limit.

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