Random code generator, fabricating method thereof and device applying the same

Abstract

A random code generator includes: at least one resistive switch element, a control circuit and a logic circuit. The control circuit is electrically connected to the at least one resistive switch element and is used to perform a forming step on the at least one resistive switch element; perform a writing step on the at least one resistive switch element with a preset voltage; and perform two resistance reading steps on the at least one resistive switch element to obtain a first read data and a second read data respectively. The logic circuit is electrically connected to the control circuit, and is used to perform logical operations to compare the first read data and the second read data, thereby generating a random code.

Description

Technical Field

[0001] This specification relates to a semiconductor device, a method of manufacturing the same, and its applications, particularly to a random code generator, a method of manufacturing the same, and its applications. Prior Technology

[0002] With the popularization of Internet of Things (IoT) technology, internet-connected devices (such as mobile communication devices, sensors installed on the devices, and their built-in software) can be interconnected via networks, enabling more and more data to be stored and shared in digital form. However, while providing convenience for information integration, it also brings higher cybersecurity risks. Therefore, the security of internet devices and the networks they are connected to is receiving increasing attention.

[0003] Physically Unclonable Function (PUF) technology is a new method for protecting data in semiconductor devices (or semiconductor wafers). Generally, PUF technology uses variations in the semiconductor device's manufacturing process to obtain a unique random code. Because this random code cannot be copied, it serves as a unique identifier (ID code) for the semiconductor device (or semiconductor wafer), preventing data theft and providing a high level of information security. Summary of the Invention

[0004] One embodiment of this specification discloses a random code generator, comprising: at least one resistive switch element, a control circuit, and a logic circuit. The control circuit is electrically connected to the resistive switch element and is used to perform an initialization (forming) step on the resistive switch element; a writing step on the resistive switch element with a preset voltage; and a secondary resistance value reading step on the resistive switch element to obtain first read data and second read data. The logic circuit is electrically connected to the control circuit and is used to perform logical operations to compare the first read data and the second read data, thereby generating a random code.

[0005] Another embodiment of this specification discloses a method for manufacturing a random code generator, comprising the following steps: providing at least one resistor switching unit; providing a control circuit electrically connected to the resistor switching unit for: initializing the resistor switching unit; writing a preset voltage to the resistor switching unit; and performing a secondary resistance value reading step on the resistor switching unit to obtain a first read data and a second read data. A logic circuit is also provided for performing logical operations to compare the first read data and the second read data, thereby generating a random code.

[0006] Another embodiment of this specification discloses a physically non-replicable functional element, including a random code generator as described above, wherein the random code generator includes a plurality of resistor switching units.

[0007] According to the above embodiments, this specification provides a random code generator, its manufacturing method, and application elements. The random code generator includes at least one resistor switching unit, a control circuit, and a logic circuit. The resistor switching unit is initialized; a writing step is performed with a preset voltage; and a second resistance value reading step is performed to obtain first and second read data. The preset writing voltage causes subsequent repeated readings of the first and second read data by the resistor switching unit to mutate, and a unique random code is generated by comparing the first and second read data through logical operations. In some embodiments, this can be used as a physically uncopyable functional element of a semiconductor chip to prevent data theft from the semiconductor chip. Simple Explanation of the Diagram

[0008] To provide a better understanding of the above and other aspects of this specification, specific embodiments are described below in conjunction with the accompanying drawings: Figure 1A is a schematic diagram illustrating the component configuration for fabricating a random code generator according to an embodiment of this specification; Figure 1B is a schematic diagram of the partial structural configuration of the random code generator, based on Figure 1A; Figure 2A is a circuit configuration diagram of a logic circuit according to an embodiment of this specification; and Figure 2B illustrates the clock diagram of the control circuit's write and read steps and the logic circuit's logic operations for the random code generator. Implementation

[0009] This specification provides a random code generator, its manufacturing method, and application elements to provide unique random codes for preventing data theft from semiconductor wafers. To make the above embodiments and other objects, features, and advantages of this specification more apparent, several embodiments are described below in detail with reference to the accompanying drawings.

[0010] However, it must be noted that these specific embodiments and methods are not intended to limit the present invention. The proposed preferred embodiments are merely illustrative of the technical features of the present invention and are not intended to limit the scope of the patent application. These embodiments can still be implemented using other features, elements, methods, and parameters. Those skilled in the art will be able to make equivalent modifications and variations based on the description in the following specification without departing from the spirit and scope of the present invention. In different embodiments and drawings, the same elements will be represented by the same element symbols.

[0011] Please refer to Figures 1A and 1B. Figure 1A is a schematic diagram illustrating the component configuration of a random code generator 100 according to one embodiment of this specification. Figure 1B is a schematic diagram illustrating a partial structural configuration of the random code generator 100 according to Figure 1A. In some embodiments of this specification, the random code generator 100 includes at least one resistor switching unit 101, a control circuit 102, and a logic circuit 103. The control circuit 102 is electrically connected to the resistor switching unit 101, and the logic circuit 103 is electrically connected to the control circuit 102.

[0012] In some embodiments of this specification, the random code generator 100 may be formed on a semiconductor substrate 110 using a semiconductor process. The semiconductor substrate 110 may be, for example, a silicon-containing substrate, such as a silicon wafer, a silicon-on-insulator (SOI) substrate, or other semiconductor substrates. In this embodiment, the semiconductor substrate 101 may be a silicon wafer. The resistor switching unit 101, the control circuit 102, and the logic circuit 103 are respectively formed on the silicon wafer using a semiconductor process and other integrated circuit elements.

[0013] In this embodiment, the random code generator 100 may include a plurality of resistor switching units 101. In some embodiments of this specification, the resistor switching unit 101 may be a resistive random-access memory (ReRAM or RRAM) unit.

[0014] As illustrated in Figure 1B, each resistance switching unit 101 includes an upper electrode layer 101T, a resistance switching layer 101R, and a lower electrode layer 101B. The materials constituting the upper electrode layer 101T and the lower electrode layer 101B can be the same or different. For example, in some embodiments of this specification, the materials constituting the upper electrode layer 101T and the lower electrode layer 101B can be selected from a group consisting of tungsten, titanium nitride (TiN), tantalum nitride (TaN), copper (Cu), aluminum (Al), gold (Au), silver (Ag), platinum (Pt), titanium (Ti), iridium (Ir), and any combination thereof. In this embodiment, the materials constituting the upper electrode layer 101T and the lower electrode layer 101B can be a composite metal layer composed of titanium nitride / tantalum nitride / platinum / iridium.

[0015] The material constituting the resistance switching layer 101R can be a transition metal oxide (TMO) or a phase change material. The transition metal oxide can be, for example, tantalum oxide (TaOx), titanium oxide, nickel oxide, hafnium oxide (HfOx), zirconium oxide (ZrOx), tungsten oxide (WOx), zinc oxide (ZnOx), aluminum oxide (AlOx), molybdenum oxide (MnOx), copper oxide (CuOx), or any combination thereof. The phase change material can be, for example, a chalcogenide compound such as germanium antimony tellurium (GST), where x, y, and z can be integers. Silver indium antimony tellurium (AgInSbTe) or a combination thereof. In this embodiment, the resistance switching layer 101R may include tantalum pentoxide (Ta2O5).

[0016] The control circuit 102 includes: a write driver 102W, a row decoder 102A, a column decoder 102B, a plurality of bit lines BL, a plurality of control transistors 102D, a plurality of word lines WL, and a plurality of power lines SL. Each control transistor 102D corresponds to a resistor switching unit (resistive memory cell) 101. The source of each control transistor 102D is electrically connected to a corresponding bit line BL; the drain of each control transistor 102D is electrically connected to the upper electrode layer 101T of the corresponding resistor switching unit 101; the gate of each control transistor 102D is electrically connected to a corresponding word line WL; and the lower electrode layer 101B of the resistor switching unit 101 is electrically connected to a corresponding power line SL, thus forming a resistive memory cell 111C with a one-transistor and one-resistor (1T1R) architecture.

[0017] A plurality of bit lines BL and a plurality of word lines WL intersect each other perpendicularly; one end of each bit line BL is electrically connected to the row decoder 102A, and the other end is electrically connected to the source of the control transistor 102D in a plurality of resistive memory cells 111C arranged in the same row; one end of each word line WL is electrically connected to the column decoder 102B, and the other end is electrically connected to the gate of a plurality of control transistors 102D in a plurality of resistive memory cells 111C arranged in the same column, thereby constructing a resistive memory cell array 111.

[0018] It is worth noting that although the random code generator 100 includes a resistive memory cell array 111 in this embodiment, the architecture and arrangement of the random code generator 100 are not limited thereto. Any architecture and arrangement in which at least one resistive switching unit 101 can be addressed, initialized, written to, and read from by the control circuit 102 does not exceed the spirit and scope of the embodiments described in this specification.

[0019] In the embodiments of this specification, the control circuit 102 is used to perform an initialization step on the selected (addressed) resistor switching unit (resistive memory unit) 101; then, a write step is performed on the selected resistor switching unit (resistive memory unit) 101 with a preset voltage. Afterwards, a second resistance value read step is performed on this resistive memory unit 101 to obtain first read data and second read data. The logic circuit 103, electrically connected to the control circuit 102, is used to perform logical operations to compare the first read data 1stRD and the second read data 2ndRD of the selected resistor switching unit (resistive memory unit) 101, thereby generating a random code DOUT.

[0020] In some embodiments of this specification, an initialization step is performed on the selected resistor switching unit (resistive memory unit) 101, including using the row decoder 102A and column decoder 102B in the control circuit 102 to row address a plurality of resistor switching units (resistive memory units) 101 in the resistive memory cell array 111 through the bit line BL, word line WL and control transistor 102D, selecting one of the resistor switching units 101, and applying at least one initialization pulse to the selected resistor switching unit (resistive memory unit) 101 to switch the resistor switching unit (resistive memory unit) 101 from the original high-resistance state (HRS) to a lower-resistance state (LRS) that is easier to energize, so that it has voltage.

[0021] For example, in this embodiment, a positive voltage (e.g., between +3V and +5V) can be applied to the resistor switching unit (resistive memory unit) 101 to form a conductive filament in the resistance switching layer 101R of the selected resistor switching unit (resistive memory unit) 101, so that the upper electrode layer 101T and the lower electrode layer 101B of the initialized resistor switching unit (resistive memory unit) 101 have a lower conductivity than before initialization.

[0022] In some embodiments of this specification, a writing step is performed on the selected resistor switching unit (resistive memory unit) 101, including applying at least one write pulse VBL (e.g., voltage between 2V and 3V) to the selected resistor switching unit (resistive memory unit) 101 via the write driver 102W of the control circuit 102 through the corresponding bit line BL, which is opposite in electrical polarity to the initialization pulse and whose absolute voltage value is substantially less than that of the initialization pulse, so that the resistor switching unit (resistive memory unit) 101 changes from the low resistance state after initialization to the high resistance state again.

[0023] In the embodiments of this specification, the voltage of the write pulse VBL is a preset value that can make the resistance value variation probability of the selected resistor switching unit (resistive memory unit) 101 greater than or equal to 50%. The resistance value variation probability refers to the probability that the first read data 1stRD and the second read data 2ndRD differ between two consecutive read steps when the selected resistor switching unit (resistive memory unit) 101 is repeatedly read.

[0024] For example, in this embodiment, the control circuit 102 further includes a sensing amplifier circuit 102S, electrically connected to the resistive memory cell array 111, used to read (sensor) the resistance value of the selected resistance switching unit (resistive memory cell) 101 during the resistance reading step, and output a read data. During the read operation of the selected resistance switching unit (resistive memory cell) 101, the power line SL of the control circuit 102 provides a ground voltage (e.g., 0.0V) to the selected resistance switching unit (resistive memory cell) 101, and the sensing amplifier circuit 102S provides a reference current (reference resistance) IREF. Since the read voltage (e.g., between VDD / 2 and VDD) is set to be lower than the write pulse VBL, the resistance state of the selected resistance switching unit (resistive memory cell) 101 remains unchanged during the read step, while a read current is generated. By inputting the read current and the reference current (reference resistance) IREF into the comparator 102SC of the sensing amplifier circuit 102S, a read data representing the resistance state of the selected resistor switching unit (resistive memory unit) 101 can be obtained.

[0025] If the read current from the selected resistor switching unit (resistive memory cell) 101 is higher than the reference current (or reference resistance) IREF, then the resistor switching unit (resistive memory cell) 101 is in a low-resistance state. Comparator 102SC will output a read data representing the low-resistance state, such as "0". Conversely, if the read current from the selected resistor switching unit (resistive memory cell) 101 is lower than the reference current (reference resistance) IREF, then the resistor switching unit (resistive memory cell) 101 is in a high-resistance state. Comparator 102SC will output a read data representing the high-resistance state, such as "1".

[0026] The reference current (reference resistance) IREF of the selected resistor switching cell (resistive memory cell) 101 and the voltage of the applied write pulse VBL can be determined by simulation or experiment using a reference resistor switching cell (resistive memory cell) made of the same or similar materials, dimensions (e.g., thickness, area, etc.) and / or manufacturing parameters as the selected resistor switching cell (resistive memory cell) 101, after applying different write pulse VBL voltages, and by reading the resistance state obtained by the operation measurement.

[0027] For example, in this embodiment, after a preset write pulse is applied to the reference resistor switching unit (resistive memory unit), performing at least two repeated reads may produce the six states described in Table 1: Table 1 Read status first Reading current The second Reading current first Reading data The second Reading data probability I > IREF > IREF 1 1 ~12.5% II <IREF> IREF 0 1 ~25.0% III < IREF < IREF 0 0 ~12.5% IV > IREF > IREF 1 1 ~12.5% V > IREF < IREF 1 0 ~25.0% VI < IREF < IREF 0 0 ~12.5%

[0028] The probability of occurrence of the above six repeated read states can be obtained through multiple simulations or experiments. States II and IVV, in which multiple read data states are inconsistent (i.e., the first read data and the second read data are greater than and less than the reference current IREF, respectively), and the sum of the probabilities of occurrence of the two states is greater than 50%, are selected as the reference current (reference resistance) IREF and the applied write pulse VBL of the selected resistor switching unit (resistive memory unit) 101.

[0029] When the selected resistor switching unit (resistive memory unit) 101 is written to using the aforementioned write pulse VBL, and the resistor switching unit (resistive memory unit) 101 is read twice, the first read data 1stRD and the second read data 2ndRD from the previous two reads can be obtained. In this embodiment, the voltage of the write pulse VBL applied to the selected resistor switching unit (resistive memory unit) 101 is less than +2V, preferably +1.8V.

[0030] Please refer to Figures 2A and 2B. Figure 2A illustrates a circuit configuration diagram of a logic circuit 103 according to an embodiment of this specification. Figure 2B illustrates a clock diagram of the write-read steps of the control circuit 102 of the random code generator 100 and the logic operation of the logic circuit 103. In this embodiment, the logic circuit 103 includes three flip-flops (FF) 103A, 103B, and 103C, and an exclusive-OR gate (XOR gate) 103D.

[0031] Three flip-flops 103A, 103B, and 103C receive the scan enable signal SE. The D input IN of flip-flop 103A is electrically connected to the output SA_OUT of comparator 102SC in control circuit 102. The Q output of flip-flop 103A is electrically connected to the A input of mutex gate 103D and the D input of flip-flop 103B. The Q output of flip-flop 103B is electrically connected to the B input of mutex gate 103D. The D input of flip-flop 103C is electrically connected to the output of mutex gate 103D. The first read data 1stRD and the second read data 2ndRD of the selected resistor switching unit (resistive memory unit) 101, through logic operations in logic circuit 103, can generate a random code DOUT, which is output from the Q output of flip-flop 103C.

[0032] However, it is worth noting that the configuration of logic circuit 103 is not limited thereto. Any circuit configuration that can perform logical operations to compare the first read data 1stRD and the second read data 2ndRD of the selected resistor switching unit (resistive memory unit) 101 to generate an encoding does not exceed the scope of the invention of logic circuit 103 described in this specification.

[0033] Since the selected resistor switching unit (resistive memory unit) 101 has a resistance value variation probability of more than 50% after being written with a preset voltage, the relationship between the first read data 1stRD and the second read data 2ndRD that are read twice becomes random. After logical operation by logic circuit 103, a random code DOUT can be generated by comparing the first read data 1stRD and the second read data 2ndRD.

[0034] By repeating the above steps in a predetermined sequence through the control circuit 102 and logic circuit 103 on multiple resistor switching units (resistive memory cells) 101 in the resistive memory cell array 111, a unique set of random codes can be obtained. Using this set (at least two) of unique random codes, challenge response pairs (CRPs) or fingerprints are formed, providing a Physically Unclonable Function (PUF). In some embodiments of this specification, the manufacturing process of the random code generator 100 can be integrated into the semiconductor wafer manufacturing process, serving as a physically unclonable functional element of the semiconductor wafer to prevent data theft from the semiconductor wafer.

[0035] According to the above embodiments, this specification provides a random code generator, its manufacturing method, and application elements. The random code generator includes at least one resistor switching unit, a control circuit, and a logic circuit. The resistor switching unit is initialized; a writing step is performed with a preset voltage; and a second resistance value reading step is performed to obtain first and second read data. The preset writing voltage causes subsequent repeated readings of the first and second read data by the resistor switching unit to mutate, and a unique random code is generated by comparing the first and second read data through logical operations. In some embodiments, this can be used as a physically uncopyable functional element of a semiconductor chip to prevent data theft from the semiconductor chip.

[0036] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0037] 100: Random Code Generator 101: Resistor Switching Unit 101T: Upper Electrode Layer 101R: Resistance Switching Layer 101B: Lower electrode layer 102: Control Circuit 102W: Write drive 102A: Line Decoder 102B: Column Decoder 102D: Control Transistor 102S: Sensing Amplifier Circuit 102SC: Comparator 103: Logic Circuits 103A: Flip-Flipper 103B: Flip-Flipper 103C: Flip-Flipper 103D: Mutual Exclusion or Gate 110: Semiconductor substrate 111: Resistive Memory Cell Array 111C: Resistive Memory Cell BL: Bitline WL: Character Line SL: Power cord 1stRD: First data read 2ndRD: Second Data Reading DOUT: Random Encoding VBL: Write Pulse IREF: Reference Current IN: Input terminal SA_OUT: Output terminal SE: Scanning Enable Signal

[0038] none.

Claims

1. A random code generator, comprising: at least one resistive switch element; a control circuit electrically connected to the at least one resistive switch element, configured to: perform an initialization step on the at least one resistive switch element; perform a writing step on the at least one resistive switch element with a preset voltage; and perform a two-stage resistance value reading step on the at least one resistive switch element to obtain a first read data and a second read data; and a logic circuit electrically connected to the control circuit, configured to perform a logic operation to compare the first read data and the second read data, thereby generating a random code.

2. The random code generator as claimed in claim 1, wherein the at least one resistor switching unit includes at least one resistive random-access memory (ReRAM or RRAM) unit.

3. The random code generator as described in claim 2, wherein the preset voltage can make the probability of a resistance value variation of the at least one resistive memory cell greater than or equal to 50%.

4. The random code generator as described in claim 2, wherein the at least one resistive memory cell includes a dielectric layer comprising tantalum oxide (TaOx), and the preset voltage is less than 2V.

5. The random code generator as claimed in claim 2, wherein the control circuitry includes: a bit line connected to the at least one resistive memory cell; a control transistor connected to the at least one resistive memory cell; and a word line connected to the control transistor.

6. The random code generator as described in claim 1, wherein the logic circuitry includes an exclusive-OR gate (XOR gate).

7. A method for manufacturing a random code generator, comprising: providing at least one resistor switching unit; providing a control circuit electrically connected to the at least one resistor switching unit, for: performing an initialization step on the at least one resistor switching unit; performing a writing step on the at least one resistor switching unit with a preset voltage; and performing a two-stage resistance value reading step on the at least one resistor switching unit to obtain a first read data and a second read data; and providing a logic circuit for performing a logic operation to compare the first read data and the second read data, thereby generating a random code.

8. A method for manufacturing a random code generator as described in claim 7, wherein the at least one resistor switching unit includes at least one resistive memory unit.

9. A method for manufacturing a random code generator as described in claim 8, wherein the control circuit includes: a bit line connected to the at least one resistive memory cell; a control transistor connected to the at least one resistive memory cell; and a word line connected to the control transistor.

10. A method of manufacturing a random code generator as described in claim 8, wherein the logic circuit includes a mutex OR gate.

11. A method of manufacturing a random code generator as described in claim 8, wherein the at least one resistive memory cell includes a dielectric layer comprising tantalum oxide.

12. A physically unclonable function (PUF) element comprising a random code generator as described in any one of claims 1 to 5, wherein the random code generator comprises a plurality of resistor switching units.

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