Techniques for processing alias instructions in graphics processing units (GPUS)
TW202642335APending Publication Date: 2026-10-16QUALCOMM INC
View PDF 0 Cites 0 Cited by
Patent Information
- Application Number
- TW115101559
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-02-11
- Filing Date
- 2026-01-15
- Publication Date
- 2026-10-16
Smart Images

Figure TWG2TA001080952_001 
Figure TWG2TA001080952_002 
Figure TWG2TA001080952_003
Abstract
Aspects described herein relate to associating aliases with registers in an alias table for processing graphics processing unit (GPU) instructions. An aliasing instruction indicating associations between multiple alias registers and one or more alias values can be received. An alias corresponding to one of the one or more alias values for each of the multiple alias registers can be stored in the alias table and based on the aliasing instruction.
Need to check novelty before this filing date? Find Prior Art
