Multistable Display

Abstract

This invention is a multistable display, comprising a timing control circuit unit, a driving circuit unit, and a panel unit. The timing control circuit unit generates timing control signals. The driving circuit unit stores a voltage configuration truth table. The first data signal of the timing control signal sequentially includes header setting data and voltage waveform data. The driving circuit unit sets the voltage configuration truth table according to the header setting data. Furthermore, the driving circuit unit determines the driving voltage waveform output to the panel unit based on the voltage waveform data and the voltage configuration truth table. Since the voltage waveform data only needs to transmit 1 bit of data, only a smaller number of bits are needed to achieve the same amount of data transmission. Therefore, under the condition of transmitting the same total amount of data in the same amount of time, a lower clock frequency can be used, thereby reducing power consumption.

Description

Technical Field

[0001] A display, particularly a multistable display driven by a low-frequency driving method. Prior Technology

[0002] A conventional multistable display, such as a cholesterol liquid crystal display (ChLCD), exhibits bistable liquid crystal display characteristics. Therefore, when displaying an image, this multistable display requires multiple voltage configurations for driving. For example, this multistable display has a panel unit, and each pixel of the panel unit is composed of a plurality of scan electrodes and a plurality of data electrodes, with a liquid crystal layer disposed between the scan electrodes and the data electrodes. When driving the panel unit, a voltage is applied to the scan electrodes and the data electrodes, so that a specific voltage is applied at the position of the corresponding pixel, causing the liquid crystal in the liquid crystal layer to rotate to a specific angle.

[0003] However, this multi-stable display requires multiple voltage configurations to drive it. Therefore, in the control signals, the data used to control the voltage configuration of each pixel needs to be transmitted through multiple bits, making it impossible to represent multiple voltage configurations with a single bit. For example, currently, the data used to control the voltage configuration is transmitted through 3 bits of data. That is, every time the voltage configuration of a pixel is changed, 3 bits of data need to be transmitted.

[0004] Furthermore, the multistable display will have a timing controller (TCON) and a driver IC. The timing controller generates a timing control signal to the driver IC, and the driver IC outputs a drive voltage to the scan electrodes and the data electrodes according to the control signal, thereby driving the multistable display to display a specific image.

[0005] Generally, the timing control circuit unit (TCON) has a clock output terminal (clk), a display output enable control terminal (doe), a display output ground control terminal (dog), a digital-to-analog conversion control terminal (d2a), a display start signal control terminal (dsp), and a complex data output terminal (data). The clock output terminal (clk), display output enable control terminal (doe), display output ground control terminal (dog), digital-to-analog conversion control terminal (d2a), display start signal control terminal (dsp), and these data output terminals of the timing control circuit unit (TCON) are connected to the driver circuit unit (Driver IC) to output the control signal. The frequency of the clock signal output by the clock output terminal (clk) greatly affects the overall power consumption. The higher the frequency of the clock signal, the greater the overall power consumption.

[0006] For example, taking a multistable display with Full HD resolution as an example, the resolution is... When transmitting at Single Data Rate (SDR), 2 pixels of data are transmitted per clock cycle, meaning the number of pixels transmitted per clock cycle is 2. Furthermore, the transmission time for each frame is set... The time complexity is 5 milliseconds (ms). Each pixel of this multistable multi-state display requires 3 bits of data to transmit. Furthermore, since each pixel requires 3 bits of data to transmit, and the number of pixels transmitted per clock cycle is 2, the number of data output terminals is the number of bits required for each pixel's data multiplied by the number of pixels transmitted per clock cycle. In other words, there are 6 data output ports.

[0007] The clock rate of this multistable display can be calculated using the following formula:

[0008] The resolution is 1920. The number of pixels transmitted per clock cycle is 2 in SDR mode. The hold time is set to 1. The duty count is adjustable as needed and can be set to 64, usually in powers of 2 units. Transmission time ( The value is 5 milliseconds (ms). Substituting these figures into the formula yields Table 1, which shows the clock rate under various conditions.

[0009] Resolution (Resolution) Transmission mode (Mode) Pixel Per Clock Duty Count Clock Rate Full HD ( ) SDR 2 64 5 (ms) 12.314 (MHz) Table 1

[0010] As shown in Table 1, under Full HD resolution, the clock rate of this multistable display is quite high, resulting in high power consumption and rapid power consumption. Summary of the Invention

[0011] In view of the fact that the clock rate of existing multistable displays is quite high, resulting in high power consumption and rapid power consumption, the present invention provides a cholesteric liquid crystal device to reduce the clock rate of multistable displays, thereby reducing power consumption.

[0012] The multi-stable display includes a timing control circuit unit (TCON), a driver circuit unit (Driver IC), and a panel unit.

[0013] The timing control circuit unit generates a timing control signal. The drive circuit unit stores a voltage configuration truth table, is connected to the timing control circuit unit, and receives the timing control signal. The panel unit is connected to the drive circuit unit.

[0014] The timing control signal includes a first data signal, which sequentially includes at least one header setting data and at least one voltage waveform data. When the drive circuit unit receives the header setting data, it sets the voltage configuration truth table according to the header setting data. When the drive circuit unit receives the voltage waveform data, it determines a drive voltage waveform to be output to the panel unit according to the voltage waveform data and the voltage configuration truth table.

[0015] When the drive circuit unit receives the voltage waveform data, it determines the drive voltage waveform to be output to the panel unit based on the voltage waveform data and the voltage configuration truth table. Therefore, the voltage waveform data can transmit 1 bit of data, allowing the drive circuit unit to look up the voltage configuration truth table based on this 1 bit of data to confirm the voltage value of the drive voltage waveform input to the panel unit, without directly transmitting the voltage value. Generally, the voltage value of the drive voltage waveform is used to control the voltage configuration and requires 3 bits to transmit, while the voltage waveform data only requires 1 bit to complete the data transmission. Furthermore, the voltage configuration truth table is set according to the header setting data and can change the output voltage value as needed, achieving the goal of transmitting the same amount of data with fewer bits. Since the same amount of data can be transmitted using fewer bits, a lower clock rate can be used to reduce power consumption when transmitting the same amount of data in the same amount of time. Simple Explanation of the Diagram

[0016] Figure 1 is a block diagram of the multistable display of the present invention. Figure 2A is a waveform diagram of the header setting signal output by the header setting control terminal (dsh) of the multistable display of the present invention. Figure 2B is a schematic diagram of the first data signal output by the first data output terminal (data 0) of the multistable display of the present invention. Figure 3A is a schematic diagram of the waveforms of the positive and negative signals output by the voltage positive and negative control terminal (dpn) of the multi-stable display of the present invention. Figure 3B is a schematic diagram of the brush voltage waveform of the first data signal output from the first data output terminal (data) of the multistable display of the present invention. Figure 4A is a schematic diagram of the waveforms of the positive and negative signals output by the voltage positive and negative control terminal (dpn) of the multi-stable display of the present invention. Figure 4B is a schematic diagram of the voltage waveform of the first data signal output by the first data output terminal (data 0) of the multistable display of the present invention. Figure 5A is a first schematic diagram of the brush white header setting data of the first data signal output from the first data output terminal (data 0) of the multi-stable display of the present invention. Figure 5B is a second schematic diagram of the brush white header setting data of the first data signal output from the first data output terminal (data 0) of the multi-stable display of the present invention. Figure 5C is a third schematic diagram of the brush white header setting data of the first data signal output by the first data output terminal (data 0) of the multi-stable display of the present invention. Figure 6A is a first schematic diagram of the brush voltage waveform data of the first data signal output from the first data output terminal (data 0) of the multi-stable display of the present invention. Figure 6B is a second schematic diagram of the brush voltage waveform of the first data signal output from the first data output terminal (data 0) of the multistable display of the present invention. Figure 6C is a third schematic diagram of the brush voltage waveform data of the first data signal output from the first data output terminal (data 0) of the multi-stable display of the present invention. Figure 6D is a schematic diagram of the positive and negative signals output by the voltage positive and negative control terminal (dpn) of the multi-stable display of the present invention. Figure 7A is a first schematic diagram of the content header setting data of the first data signal output by the first data output terminal (data 0) of the multi-stable display of the present invention. Figure 7B is a second schematic diagram showing the content header setting data of the first data signal output from the first data output terminal (data) of the multi-stable display of the present invention. Figure 7C is a third schematic diagram showing the content header setting data of the first data signal output by the first data output terminal (data 0) of the multistable display of the present invention. Figure 8A is a first schematic diagram of the content voltage waveform data of the first data signal output by the first data output terminal (data 0) of the multi-stable display of the present invention. Figure 8B is a second schematic diagram of the content voltage waveform data of the first data signal output by the first data output terminal (data 0) of the multi-stable display of the present invention. Figure 8C is a third schematic diagram of the content voltage waveform data of the first data signal output by the first data output terminal (data 0) of the multi-stable display of the present invention. Figure 8D is a schematic diagram of the positive and negative signals output by the voltage positive and negative control terminal (dpn) of the multi-stable display of the present invention. Figure 9A is a waveform diagram of the driving voltage waveform output from the driving circuit unit of the multi-stable display of the present invention to the first pixel. Figure 9B is a waveform diagram of the driving voltage waveform output from the driving circuit unit of the multistable display of the present invention to the second pixel. Implementation

[0017] Please refer to Figure 1. The multistable display of the present invention includes a timing control circuit unit 10, a driving circuit unit 20 and a panel unit 30.

[0018] The timing control circuit unit 10 generates a timing control signal. The drive circuit unit 20 stores a voltage configuration truth table, is connected to the timing control circuit unit 10, and receives the timing control signal. The panel unit 30 is connected to the drive circuit unit 20.

[0019] Please refer to Figures 2A and 2B. The timing control signal includes a first data signal 11, which sequentially includes at least one header setting data 111 and at least one voltage waveform data 112. When the drive circuit unit 20 receives the header setting data 111, the drive circuit unit 20 sets the voltage configuration truth table according to the header setting data 111. When the drive circuit unit 20 receives the voltage waveform data 112, the drive circuit unit 20 determines a drive voltage waveform to be output to the panel unit 30 according to the voltage waveform data 112 and the voltage configuration truth table.

[0020] Since the driving circuit unit 20 determines the driving voltage waveform output to the panel unit based on the voltage waveform data 112 and the voltage configuration truth table, the voltage waveform data 112 can transmit 1 bit of data, allowing the driving circuit unit to look up the voltage value of the driving voltage waveform input to the panel unit 30 based on this 1 bit of data, without directly transmitting the entire voltage value. Generally, the entire voltage value is transmitted using 3 bits, while the voltage waveform data only needs 1 bit to complete the voltage value transmission. Furthermore, the voltage configuration truth table is set according to the header setting data, and the output voltage value can be changed as needed to achieve the purpose of transmitting the same amount of data with fewer bits. Since the same amount of data can be transmitted using fewer bits, a lower clock rate can be used to reduce power consumption when transmitting the same amount of data in the same amount of time.

[0021] Furthermore, the at least one header setting data 111 includes a brush white header setting data 1111 and a content header setting data 1112, and the at least one voltage waveform data 112 includes a brush white voltage waveform data 1121 and a content voltage waveform data 1122. The first data signal 11 is composed of the brush white header setting data 1111, the brush white voltage waveform data 1121, the content header setting data 1112, and the content voltage waveform data 1122 arranged in sequence.

[0022] In this embodiment, the first data signal 11 further includes a hold time data 113 in sequence, and the hold time data 113 is located between the brush white voltage waveform data 1121 and the content header setting data 1112. That is, the first data signal 11 can be composed of the brush white header setting data 1111, the brush white voltage waveform data 1121, the hold time data 113, the content header setting data 1112, and the content voltage waveform data 1122 arranged in sequence.

[0023] In detail, as shown in Figure 1, the timing control circuit unit 10 includes a clock output terminal (clk), a display output enable control terminal (doe), a display output ground control terminal (dog), a digital-to-analog conversion control terminal (d2a), and a display start signal control terminal (dsp). The functions of the clock output terminal (clk), the display output enable control terminal (doe), the display output ground control terminal (dog), the digital-to-analog conversion control terminal (d2a), and the display start signal control terminal (dsp) of this timing control circuit unit (TCON) are the same as those of the timing control circuit units of conventional multi-stable displays, and will not be described in detail here.

[0024] Furthermore, the timing control circuit unit 10 includes a header setting control terminal (dsh), a voltage positive / negative control terminal (dpn), and a first data output terminal (data 0). In other embodiments, the timing control circuit unit 10 may include a plurality of data output terminals (data 0~data n), for example, the first to the (n+1)th data output terminals (data 0~data n). In this embodiment, the first data output terminal (data 0) is used as an example, but it is not limited thereto.

[0025] The header setting control terminal (dsh) is connected to the drive circuit unit 20 and outputs a header setting signal 101 to the drive circuit unit 20. The voltage positive / negative control terminal (dpn) is connected to the drive circuit unit 20 and outputs a positive / negative signal 102 to the drive circuit unit 20. The first data output terminal (data 0) is connected to the drive circuit unit 20 and outputs the first data signal 11 to the drive circuit unit 20.

[0026] As shown in Figures 2A and 2B, when the first data signal 11 output by the first data output terminal (data 0) is the white header setting data 1111, the header setting control terminal (dsh) outputs the header setting signal 101 at a high voltage level. When the first data signal 11 output by the first data output terminal (data 0) is the content header setting data 1112, the header setting control terminal (dsh) outputs the header setting signal 101 at a high voltage level. When the first data signal 11 output by the first data output terminal (data 0) is neither the white header setting data 1111 nor the content header setting data 1112, the header setting control terminal (dsh) outputs the header setting signal 101 at a low voltage level.

[0027] When the header setting signal 101 output by the header setting control terminal (dsh) is at the high voltage level, it means that the first data signal 11 output by the first data output terminal (data 0) is either the white header setting data 1111 or the content header setting data 1112. At this time, the drive circuit unit 20 can determine that the currently received first data signal 11 is the header setting data 111, and then set the voltage configuration truth table according to the header setting data 111.

[0028] Please refer to Figures 3A and 3B. The brush white voltage waveform data 1121 sequentially includes a positive brush white voltage waveform data 1121+ and a negative brush white voltage waveform data 1121-. When the first data signal 11 output by the first data output terminal (data 0) is the positive brush white voltage waveform data 1121+, the positive / negative signal 102 output by the voltage positive / negative control terminal (dpn) is the high voltage level. Furthermore, since the first data signal 11 output by the first data output terminal (data 0) at this time does not belong to the brush white header setting data 1111 or the content header setting data 1112, the header setting control terminal (dsh) outputs the header setting signal 101 as the low voltage level.

[0029] When the first data signal 11 output by the first data output terminal (data 0) is the negative brush white voltage waveform data 1121-, the positive and negative signal 102 output by the voltage positive and negative control terminal (dpn) is the low voltage level. Similarly, since the first data signal 11 output by the first data output terminal (data 0) at this time does not belong to the brush white header setting data 1111 or the content header setting data 1112, the header setting control terminal (dsh) outputs the header setting signal 101 as the low voltage level.

[0030] Please refer to Figures 4A and 4B. The content voltage waveform data 1122 sequentially includes a positive content voltage waveform data 1122+ and a negative content voltage waveform data 1122-. When the first data signal 11 output by the first data output terminal (data 0) is the positive content voltage waveform data 1122+, the positive / negative signal 102 output by the voltage positive / negative control terminal (dpn) is the high voltage level. Furthermore, since the first data signal 11 output by the first data output terminal (data 0) at this time does not belong to the white label setting data 1111 or the content label setting data 1112, the label setting control terminal (dsh) outputs the label setting signal 101 as the low voltage level.

[0031] When the first data signal 11 output by the first data output terminal (data 0) is the negative content voltage waveform data 1122-, the positive and negative signal 102 output by the voltage positive and negative control terminal (dpn) is the low voltage level. Similarly, since the first data signal 11 output by the first data output terminal (data 0) at this time does not belong to the white header setting data 1111 or the content header setting data 1112, the header setting control terminal (dsh) outputs the header setting signal 101 as the low voltage level.

[0032] Furthermore, in this embodiment, the voltage configuration truth table uses the first data signal 11 output from the first data output terminal (data 0) and the positive and negative signals 102 output from the voltage positive and negative control terminal (dpn) as inputs. And when the drive circuit unit 20 sets the voltage configuration truth table according to the header setting data 111, the header setting data 111 is set as the output of the voltage configuration truth table.

[0033] For example, taking a multistable display with Full HD resolution as an example, its resolution is... When transmitting at Single Data Rate (SDR), 2 pixels of data are transmitted per clock cycle, meaning the number of pixels transmitted per clock cycle is 2. Furthermore, the transmission time for each frame is set... The time is 5 milliseconds (ms).

[0034] Since the driving circuit unit 20 determines the driving voltage waveform output to the panel unit through the voltage waveform data 112 and the voltage configuration truth table, the voltage waveform data 112 can transmit 1 bit of data. That is, the data of each pixel of the multistable display only needs 1 bit to be transmitted. Furthermore, the timing control circuit unit 10 has one clock output terminal (clk) and six control terminals (doe, dog, d2a, dsp, dsh, dpn). If the same number of output terminals (Pin Count) is maintained, that is, a total of 11 output terminals are set, the number of data output terminals (data) can be set to 4, that is, the first to fourth data output terminals (data 0~data4).

[0035] Furthermore, since each pixel only requires 1 bit of data to be transmitted, and there are 4 data outputs, the number of pixels transmitted per clock clock can be calculated to be 4. The parameter 'a' represents the number of pixels transmitted per clock cycle.

[0036] Furthermore, the clock rate of this multistable display is calculated using the same formula, as shown below:

[0037] The resolution is 1920. The number of pixels transmitted per clock clock is 4 at Single Data Rate (SDR). The hold time is set to 1. The duty count can be adjusted as needed, and can be set to 4, 8, 16, 32, 64… in powers of 2. Transmission time ( The value is 5 milliseconds (ms). Substituting these figures into the formula yields Table 2, which shows the clock rate under various conditions.

[0038] Resolution (Resolution) Transmission mode (Mode) Pixel Per Clock Duty Count Clock Rate Full HD ( ) SDR 4 64 5 (ms) 6.157 (MHz) Table 2

[0039] As can be seen from the comparison in Tables 1 and 2, the clock rate of the multistable display of the present invention can be directly reduced by half under the same conditions. In this way, the multistable display can adopt a low-frequency driving scheme, thereby effectively reducing power consumption.

[0040] In detail, please refer to Figures 5A to 5C. Since the header setting data 111 is set as the output of the voltage configuration truth table, the white header setting data 1111 contains four output values ​​output(1) to output(4). Since the voltage value of a typical multi-stable display is transmitted through three bits, each output value output(1) to output(4) is three bits of data. For example, as shown in Figures 5B and 5C, a first output value output(1) has three bits of data, namely V1(0), V1(1), and V1(2), which are used to represent the first voltage V1, and so on. In addition, the voltage configuration truth table takes the first data signal 11 output from the first data output terminal (data 0) and the positive and negative signal 102 output from the voltage positive and negative control terminal (dpn) as inputs, so the voltage configuration truth table shown in Table 3 below can be obtained. First data output terminal (data 0) Voltage positive and negative control terminals (dpn) Output values ​​(output(1)~(4)) 1 1 V1(0)(1)(2) 0 1 V1(0)(1)(2) 1 0 V4(0)(1)(2) 0 0 V4(0)(1)(2) Table 3

[0041] Furthermore, the voltage used for whitening in this multi-stable display will be the maximum positive voltage and the maximum negative voltage. For example, the maximum positive voltage is the first voltage V1, and the maximum negative voltage is the fourth voltage V4. Therefore, the output of the voltage configuration truth table set in the whitening head setting data 1111 only requires the first voltage V1 and the fourth voltage V4. Thus, the four output values ​​output(1) to output(4) in the whitening head setting data 1111 are the first and second output values ​​output(1) and (2) set to the first voltage V1, and the third and fourth output values ​​output(3) and (4) set to the fourth voltage V4.

[0042] Furthermore, referring to Figures 6A to 6D, the white-brush voltage waveform data 1121 includes the positive white-brush voltage waveform data 1121+ and the negative white-brush voltage waveform data 1121-. In addition, the positive white-brush voltage waveform data 1121+ and the negative white-brush voltage waveform data 1121- also each have a first pixel data 1121a and a second pixel data 1121b. The first pixel data 1121a is used to drive a first pixel of the panel unit 30, and the second pixel data 1121b is used to drive a second pixel of the panel unit 30.

[0043] However, according to the voltage configuration truth table in Table 3, since the first and second output values ​​output(1) and (2) are set to the first voltage V1, and the third and fourth output values ​​output(3) and (4) are set to the fourth voltage V4, as shown in Figure 6D, regardless of what the first data signal 11 output by the first data output terminal (data 0) is, as long as the positive and negative signal 102 output by the voltage positive and negative control terminal (dpn) is set to the high voltage level, i.e., bit 1, the driving voltage waveform output by the driving circuit unit 20 to the panel unit 30 can be controlled to be the first voltage V1. Similarly, as shown in Figure 6D, when the positive and negative signal 102 output by the voltage positive and negative control terminal (dpn) is set to the low voltage level, i.e., bit 0, the driving voltage waveform output by the driving circuit unit 20 to the panel unit 30 can be controlled to be the first voltage V1.

[0044] Therefore, regardless of how the first data signal 11, represented by X in Figure 6C, is set, it will not affect the driving voltage waveform output by the driving circuit unit 20 to the panel unit 30.

[0045] Furthermore, as shown in Figures 7A to 7C, the header setting data 1112 also contains four output values, output(1) to output(4). Similarly, since the voltage value is transmitted using three bits, each output value, output(1) to output(4), is a three-bit data. For example, as shown in Figures 7B and 7C, the first output value, output(1), has three bits of data, V2(0), V2(1), and V2(2), used to represent the second voltage, V2. The others follow the same pattern, representing the third voltage, V3, the fifth voltage, V5, and the sixth voltage, V6, respectively. In addition, the voltage configuration truth table uses the first data signal 11 output from the first data output terminal (data 0) and the positive and negative signal 102 output from the voltage positive and negative control terminal (dpn) as inputs, thus yielding the voltage configuration truth table shown in Table 4 below. First data output terminal (data 0) Voltage positive and negative control terminals (dpn) Output values ​​(output(1)~(4)) 1 1 V2(0)(1)(2) 0 1 V3(0)(1)(2) 1 0 V5(0)(1)(2) 0 0 V6(0)(1)(2) Table 4

[0046] Furthermore, the driving voltage used by the multi-stable display to display content has four voltage configurations, such as the second voltage V2, the third voltage V3, the fifth voltage V5, and the sixth voltage V6. Therefore, the output of the voltage configuration truth table set in the content header setting data 1112 has the second voltage V2, the third voltage V3, the fifth voltage V5, and the sixth voltage V6. Thus, the four output values ​​output(1) to output(4) in the content header setting data 1112 are: the first output value output(1) is set to the second voltage V2, the second output value output(2) is set to the third voltage V3, the third output value output(3) is set to the fifth voltage V5, and the fourth output value output(4) is set to the sixth voltage V6.

[0047] Furthermore, referring to Figures 8A to 8D, the content voltage waveform data 1122 includes the positive content voltage waveform data 1122+ and the negative content voltage waveform data 1122-. In addition, the positive content voltage waveform data 1122+ and the negative content voltage waveform data 1122- also each have a first pixel data 1122a and a second pixel data 1122b. The first pixel data 1122a is used to drive the first pixel of the panel unit 30, and the second pixel data 1122b is used to drive the second pixel of the panel unit 30.

[0048] For example, according to the voltage configuration truth table in Table 4, as shown in Figures 8C and 8D, when the first pixel data 1122a of the first data signal 11 output by the first data output terminal (data 0) is at the high voltage level, i.e., bit 1, and when the positive and negative signal 102 output by the voltage positive and negative control terminal (dpn) is also at the high voltage level, i.e. bit 1, the driving voltage waveform output by the driving circuit unit 20 to the panel unit 30 is the second voltage V2. Similarly, when the second pixel data 1122b of the first data signal 11 output by the first data output terminal (data 0) is at the low voltage level, i.e., bit 0, and when the positive and negative signal 102 output by the voltage positive and negative control terminal (dpn) is at the high voltage level, i.e. bit 1, the driving voltage waveform output by the driving circuit unit 20 to the panel unit 30 is the third voltage V3.

[0049] In this way, the drive circuit unit 20 can set the voltage configuration truth table, such as Table 3 and Table 4, according to the white header setting data 1111 and the content header setting data 1112, respectively. Furthermore, the drive circuit unit 20 can also determine the drive voltage waveform output to the panel unit 30 based on the white header voltage waveform data 1121, the content voltage waveform data 1122, and the voltage configuration truth table, such as Table 3 and Table 4. As shown in Figures 9A and 9B, Figure 9A is a waveform diagram of the drive voltage waveform 201 output by the drive circuit unit 20 to the first pixel, and Figure 9B is a waveform diagram of the drive voltage waveform 202 output by the drive circuit unit 20 to the second pixel.

[0050] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

[0051] 10: Timing control circuit unit 101: Header Setting Signal 102: Positive and negative signals 11: First Data Signal 111: Header Setting Data 1111: White Label Head Setting Data 1112: Content Header Setting Data 112: Voltage waveform data 1121: White voltage waveform data 1121+: Positive brush white voltage waveform data 1121-: Negative brush white voltage waveform data 1121a: First pixel data 1121b: Second pixel data 1122: Content Voltage Waveform Data 1122+: Positive Content Voltage Waveform Data 1122-: Negative Content Voltage Waveform Data 1122a: First pixel data 1122b: Second pixel data 113: Duration data clk: Clock output terminal doe: Display output enable control terminal dog: Display output ground control terminal d2a: Digital-to-Analog Conversion Control Terminal DSP: Display Start Signal Control Terminal dsh: Header setting control terminal DPN: Voltage positive and negative control terminal data 0~data n: First to n+1 data output terminals 20: Drive circuit unit 201: Driving voltage waveform of the first pixel 202: Driving voltage waveform of the second pixel 30: Panel unit

Claims

1. A multistable display, comprising: a timing control circuit unit for generating a timing control signal; a driving circuit unit for storing a voltage configuration truth table, connected to the timing control circuit unit, and receiving the timing control signal; and a panel unit connected to the driving circuit unit; wherein, The timing control signal includes a first data signal, and the first data signal sequentially includes at least one header setting data and at least one voltage waveform data; wherein, when the drive circuit unit receives the header setting data, the drive circuit unit sets the voltage configuration truth table according to the header setting data; wherein, when the drive circuit unit receives the voltage waveform data, the drive circuit unit determines a drive voltage waveform to be output to the panel unit according to the voltage waveform data and the voltage configuration truth table; wherein, the at least one header setting data includes a white-brush header setting data and a content header setting data, and the at least one voltage waveform data includes a white-brush voltage waveform data and a content voltage waveform data; wherein, the first data signal is composed of the white-brush header setting data, the white-brush voltage waveform data, the content header setting data, and the content voltage waveform data arranged sequentially.

2. The multistable display as described in claim 1, wherein, The first data signal also includes a duration data in sequence, and the duration data is between the brush voltage waveform data and the content header setting data.

3. The multistable display as described in claim 1, wherein, The timing control circuit unit includes: a header setting control terminal, connected to the drive circuit unit, which outputs a header setting signal to the drive circuit unit; a voltage positive / negative control terminal, connected to the drive circuit unit, which outputs a positive / negative signal to the drive circuit unit; and a first data output terminal, connected to the drive circuit unit, which outputs the first data signal to the drive circuit unit; wherein, when the first data signal output by the first data output terminal is the white header setting data, the header setting signal output by the header setting control terminal is a high voltage level.

4. The multistable display as described in claim 3, wherein, The brush white voltage waveform data sequentially includes a positive brush white voltage waveform data and a negative brush white voltage waveform data; wherein, when the first data signal output by the first data output terminal is the positive brush white voltage waveform data, the header setting signal output by the header setting control terminal is a low voltage level, and the positive and negative signals output by the voltage positive and negative control terminal are the high voltage level.

5. The multistable display as described in claim 4, wherein, When the first data signal output by the first data output terminal is the negative brush white voltage waveform data, the header setting signal output by the header setting control terminal is the low voltage level, and the positive and negative signals output by the voltage positive and negative control terminal are the low voltage level.

6. The multistable display as described in claim 3, wherein, When the first data signal output by the first data output terminal is the content header setting data, the header setting signal output by the header setting control terminal is the high voltage level.

7. The multistable display as described in claim 6, wherein, The content voltage waveform data sequentially includes a positive content voltage waveform data and a negative content voltage waveform data; wherein, when the first data signal output by the first data output terminal is the positive content voltage waveform data, the header setting signal output by the header setting control terminal is a low voltage level, and the positive and negative signals output by the voltage positive and negative control terminal are the high voltage level.

8. The multistable display as described in claim 7, wherein, When the first data signal output by the first data output terminal is the negative content voltage waveform data, the header setting signal output by the header setting control terminal is the low voltage level, and the positive and negative signals output by the voltage positive and negative control terminal are the low voltage level.

9. The multistable display as described in claim 3, wherein, The voltage configuration truth table takes the first data signal output from the first data output terminal and the positive and negative signals output from the voltage positive and negative control terminal as inputs; wherein, when the drive circuit unit sets the voltage configuration truth table according to the header setting data, the header setting data is set as the output of the voltage configuration truth table.

Images