Bit line sense amplifier and a memory apparatus using the same

Abstract

A memory apparatus includes a bit line sense amplifier. The bit line sense amplifier includes an input circuit, a latch circuit, and an isolation switching circuit. The input circuit is configured to change the voltage levels of first and second nodes based on the voltage levels of a first bit line and a second bit line. The latch circuit is configured to change the voltage levels of the first and second nodes based on the voltage levels of the second and first nodes, respectively. The isolation switching circuit is configured to couple the first bit line to the second node based on a first isolation switching signal and to couple the second bit line to the first node based on a second isolation switching signal.

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