Memory device and operating method of the same

Abstract

An example memory device includes a repair cell in a repair column having a repair local bit line, a repair local input / output (LIO) circuit having an input connected to the repair local bit line and an output connected to a repair global bit line, and a plurality of memory cells arranged in a first plurality of columns. The memory device further includes a memory LIO circuit and a first global input / output (GIO) circuit having a first multiplexer with a first input connected to the memory global bit line, a second input connected to receive the output of the repair LIO circuit, an output terminal, and a select signal terminal. The first GIO circuit further includes a first compare circuit.

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