Memory device and accessing method of the same

Abstract

A memory device for increasing access speeds by dividing memory subarrays with input / output (IO) control systems and address decoders to shorten the length of the subarray word lines and bit lines. The memory device can comprise a plurality of macros with four memory subarrays comprising word lines and bit lines, a first address decoder located between two upper memory subarrays and connected to the word lines of the two upper memory subarrays, a second address decoder located between two lower memory subarrays and connected to the word lines of the two lower memory subarrays, and an IO control system located so the two upper memory subarrays and the first address decoder are on a first side of the IO control system and the two lower memory subarrays and the second address decoder are on a second side of the IO control system opposite the first side.

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