Read method of memory device and memory device therefore

Abstract

A read method of a memory device and a memory device therefore are provided. The memory device may be a 3D NAND flash memory with high capacity and high performance. The read method comprises: performing a neighboring data repairing operation while an error correction operation according to first data of a first page is failed. The neighboring data repairing operation comprises: performing a first read operation on a first word line to obtain a first threshold voltage state of the first page; performing a second read operation on at least one second word line to obtain at least one second threshold voltage state of at least one second page; and, correcting the first data corresponding to the first page according to the first threshold voltage state of the first page and the at least one second threshold voltage state of the at least one second page.

Description

[Technical Field]

[0001] This invention relates to data processing technology for a memory device (e.g., stereoscopic and gate-type flash memory), and more particularly to a method for reading a memory device and the memory device thereof. [Previous Technology]

[0002] High-capacity and high-performance integrated circuit memory, including 3D NAND flash memory, is under continuous development. The aim is to increase data storage density by reducing the size of memory cells using 3D stacking technology and triple-level cells (TLC).

[0003] With advancements in semiconductor manufacturing processes, the spacing between memory cells in memory devices has become closer, making lateral charge loss effects (e.g., charge movement between word lines) and longitudinal charge loss effects (e.g., charge movement between multiple memory cells coupled to a single word line) more likely to occur. This results in data in the memory cells being less likely to be retained for extended periods. In other words, long-time data retention in memory cells has become poor. Although error correction codes (ECCs) can be used to recover the data stored in the memory cells to a certain extent, if the error rate of the data stored in the memory cells is too high, the success rate of ECC data recovery will drop significantly. Alternatively, the failure bit count (FBC) for reading memory cells can be reduced by appropriately adjusting the read voltage, but adjusting the read voltage may correct data and then correct it to an error. Therefore, improving long-time data retention in memory cells and reducing the read failure rate is one of the research directions. [Summary of the Invention]

[0004] The present invention provides a method for reading a memory device and a memory device thereof, which corrects the data in the memory cell on the target character line by reading the data of the target character line and adjacent character lines, thereby improving the long-term data retention of the memory cell and reducing the read failure rate.

[0005] This invention provides a method for reading a memory device. The memory device includes at least one memory cell string. The at least one memory cell string includes a plurality of memory cells. The plurality of memory cells are divided into multiple pages. The multiple pages correspond to a plurality of character lines. The reading method includes: when an error correction operation based on first data of a first page fails, performing an adjacent data repair operation. The adjacent data repair operation includes: performing a first read operation on a first character line to obtain a first threshold voltage state of the first page, wherein the first page corresponds to the first character line; performing a second read operation on at least one second character line to obtain at least one second threshold voltage state of at least one second page, wherein the at least one second page corresponds to the at least one second character line and the at least one second page is adjacent to the first page; and correcting the first data corresponding to the first page based on the first threshold voltage state of the first page and the at least one second threshold voltage state of the at least one second page.

[0006] The memory device proposed in this embodiment of the invention includes a memory array, a memory controller, and an error correction code (ECC) circuit. The memory array includes memory blocks. The memory blocks include at least one memory cell string. The at least one memory cell string includes a plurality of memory cells. The plurality of memory cells are divided into multiple pages. The multiple pages correspond to a plurality of word lines. The memory controller controls the memory array. The ECC circuit is coupled to the memory controller to perform an error correction operation. The memory controller is configured to perform: when an error correction operation based on first data of a first page fails, to perform an adjacent data repair operation. The adjacent data repair operation includes: performing a first read operation on a first word line to obtain a first threshold voltage state of the first page, wherein the first page corresponds to the first word line; performing a second read operation on at least one second word line to obtain at least one second threshold voltage state of at least one second page, wherein the at least one second page corresponds to the at least one second word line and the at least one second page is adjacent to the first page; and correcting the first data corresponding to the first page based on the first threshold voltage state of the first page and the at least one second threshold voltage state of the at least one second page.

[0007] Based on the above, in the memory device of the present invention, if the read correction operation based on the ECC circuit fails during a read operation of a specific memory region (e.g., a specific page), an adjacent data repair operation is performed. The adjacent data repair operation uses the threshold voltage state of the adjacent word lines adjacent to the target word line to attempt to correct the data of the memory cell on the target word line, thereby improving the long-term data retention of the memory cell and reducing the read failure rate.

Implementation Method

[0008] Figure 1 is a schematic diagram of a memory controller 110, an error correction code (ECC) circuit 120, and a memory block 150 in a three-dimensional (3D) inverse gate (NAND) memory device according to an embodiment of the present invention. The memory block 150 is part of a memory array in the memory device. Memory cells (e.g., memory cells CMn-1, CMn, CMn+1) are arranged in a three-dimensional manner in the memory block 150, for example, in an XYZ coordinate system. This does not mean that the circuitry of the 3D NAND memory device is limited to a three-dimensional manner. In one example, the memory block 150 may be divided into four sub-blocks (e.g., sub-blocks Sub0 to Sub3), each of which may be controlled independently.

[0009] A memory cell string (e.g., memory cell string 161) comprises multiple memory cells (e.g., memory cells CMn-1, CMn, CMn+1) connected in series along the Z direction. Each memory cell in memory cell string 161 corresponds to a word line; for example, memory cells CMn-1, CMn, CMn+1 correspond to word lines WLn-1, WLn, WLn+1, respectively. A word line (e.g., word line WLn) may correspond to a layer in the XY plane. Transistor M may be configured as a string select transistor coupled to the string select line SSL, and another memory cell may be configured as a ground select transistor coupled to the ground select line GSL.

[0010] The string select transistor and the ground select transistor are located on opposite sides of a memory cell string (e.g., memory cell string 161). In this example, multiple memory cell strings coupled to the same string select line SSL on the same plane (e.g., the plane defined by the Y and Z directions) can be defined as a sub-block.

[0011] Each memory cell string (e.g., memory cell string 161) is connected to the corresponding bit line (e.g., bit line BL1) via a corresponding string selection transistor (e.g., transistor M) on the string selection line SSL. Memory cell strings in the same column in different sub-blocks (e.g., sub-blocks Sub0, Sub1, etc.) along the Y direction are connected to the corresponding bit line (e.g., bit line BL1). The string selection line SSL can be a conductive line or conductive layer formed above the topmost character line layer (e.g., character line WL1).

[0012] Each memory cell string (e.g., memory cell string 161) can be connected to the same common source line CSL via a corresponding ground selection transistor on the ground selection line GSL. The ground selection line GSL can be a conductive line or conductive layer formed below the bottommost character line layer (e.g., character line WLm). The common source line CSL can be a conductive layer formed above the substrate of the 3D memory device. Multiple string selection lines SSL in memory block 150 can be on the same conductive layer, but divided into independent lines. Each independent line (string selection line SSL) can independently control the operation of the corresponding sub-block (e.g., sub-block Sub0, Sub1, etc.) in memory block 150.

[0013] In one example, multiple memory cells (including memory cell CMn) coupled to the same character line or character line layer (e.g., character line WLn) in a sub-region (e.g., sub-region Sub0) can be defined as a page (e.g., page Pn). In other words, multiple memory cells of the same character line or character line layer (e.g., character line WLn) are divided into a page (e.g., page Pn). In this embodiment, pages Pn-1, Pn, and Pn+1 respectively include memory cells CMn-1, CMn, and CMn+1, and pages Pn-1, Pn, and Pn+1 correspond to character lines WLn-1, WLn, and WLn+1 respectively.

[0014] The memory cell in this embodiment can be a single-level type (e.g., a single-level memory cell (SLC)) or a multi-level type (e.g., a multi-level memory cell (MLC), a three-level memory cell (TLC), and a four-level memory cell (QLC), etc.). A single-level memory cell (SLC) stores one bit of data (e.g., logic "0" and logic "1") through multiple critical voltage distribution intervals. A multi-level memory cell can store multiple bits of data through multiple critical voltage distribution intervals.

[0015] The same voltage is applied to the memory cell CMn on the same character line (e.g., character line WLn). Each character line (e.g., character line WLn) can be connected to a driver circuit, such as an X decoder (or scan driver). In one example, one or more dummy lines or layers (not shown) can be set between the serial select line SSL and the character line layer (e.g., character line WL1), and between the ground select line GSL and the bottommost character line layer (e.g., character line WLm).

[0016] The memory device also includes a memory controller 110 and an ECC circuit 120 for implementing corresponding operations on memory cells. The memory controller 110 is used to control memory blocks 150 in the memory array. The ECC circuit 120 is coupled to the memory controller 110 to perform error correction operations.

[0017] Figure 2 is a schematic diagram illustrating multiple critical voltage distributions in programming operations and data retention, using a three-level memory cell (TLC) as an example, according to an embodiment of the present invention. The X-axis of Figure 2 represents the voltage value of the critical voltage Vt. Part (A) in Figure 2 shows the critical voltage distributions DP0~DP7 presented by the memory cells on the word line (e.g., word line WLn) after programming operations. The critical voltage distributions DP0~DP7 can be distinguished into erase state eR and potential states A~G by reference voltages VrA~VrG.

[0018] Figure 2 (B) shows the critical voltage distribution DP0'~DP7' that memory cells on word lines (e.g., word line WLn) may exhibit after data retention. Over a long period of data retention, the critical voltage distribution DP0'~DP7' will gradually flatten and diffuse due to charge loss effects (e.g., lateral charge loss effect (charge movement between word lines), longitudinal charge loss effect (charge movement between multiple memory cells coupled to a single word line)... etc.). If word lines adjacent to word line WLn are all at low critical voltages, but word line WLn is at a high critical voltage, the charge on word line WLn will more easily move to adjacent word lines, resulting in charge loss.

[0019] Figure 3 is a waveform diagram illustrating a read operation on memory cells on a character line WLn according to an embodiment of the present invention. In this embodiment, the 'read operation' is performed on a unit of one page (e.g., page Pn in Figure 1) corresponding to the character line WLn. In other words, when performing a read operation on memory cells on the character line WLn, waveforms 310 of the low page Lpage, middle page Mpage, and high page Hpage are sequentially provided to the character line WLn, and these waveforms are compared with the threshold voltages of the memory cells on the character line WLn to obtain comparison values ​​for the low page Lpage, middle page Mpage, and high page Hpage. Based on these comparison values, data for all memory cells on page Pn of the corresponding character line WLn is obtained. For other character lines (Non-WLn), a pass voltage Vpass is provided.

[0020] In detail, the waveform of the low page Lpage includes reference voltages VrE and VrA in sequence; the waveform of the middle page Mpage includes reference voltages VrF, VrD, and VrB in sequence; and the waveform of the high page Hpage includes reference voltages VrG and VrC in sequence. The relationship between the aforementioned comparison values ​​and potential states can be referred to Table (1) for reference. Users of this embodiment can adjust the relationship between waveform 310 and the corresponding comparison values ​​in Table (1) and each potential state (e.g., erased state eR, potential states A~G) of the critical voltage Vt according to their needs.

[0021] Table (1) Compare values TLC form potential state Hpage Mpage Low page (Lpage) 1 1 1 eR 1 1 0 A 1 0 0 B 0 0 0 C 0 1 0 D 0 1 1 E 0 0 1 F 1 0 1 G

[0022] Figure 4 is a schematic diagram of the lateral charge loss effect according to an embodiment of the present invention. Part (A) of Figure 4 exemplarily presents potential states F~G, and part (B) of Figure 4 presents the potential states on exemplary word lines WLn-1, WLn, WLn+1 and the corresponding memory cells. Regarding mark 410 in Figure 4, the memory cell on word line WLn is in potential state G with a high critical voltage, but the memory cells on adjacent word lines WLn-1 and WLn+1 are in erased state eR with a low critical voltage. Therefore, the critical voltage distribution DP41 of the memory cell on word line WLn is mostly located to the left of the reference voltage VrG, making it highly likely that the memory cell on word line WLn will be read as potential state F during a read operation. In other words, due to the lateral charge loss effect, the memory cell on word line WLn in mark 410 is more likely to have errors in the data stored in the memory cell.

[0023] On the other hand, regarding mark 420 in Figure 4, the memory cells on word lines WLn-1, WLn, and WLn+1 are all potential states G exhibiting high critical voltages. Therefore, the critical voltage distribution DP42 of the memory cells on word line WLn is mostly located to the right of the reference voltage VrG, so the memory cells on word line WLn are very likely to be read as the correct potential state G during a read operation.

[0024] FIG5 is a flowchart of a method for reading a memory device according to an embodiment of the present invention. The reading method of FIG5 can be implemented by the memory device of FIG1. ​​Furthermore, the reading method of FIG5 can be applied to memory devices with different memory cell forms. The multiple memory cells in the memory cell block 150 of FIG1 can be single-level or multi-level memory cells. The aforementioned single-level form can be a single-level memory cell (SLC) type. The aforementioned multi-level form can be one of a multi-level memory cell (MLC) type, a three-level memory cell (TLC) type, and a four-level memory cell (QLC) type.

[0025] Please refer to Figures 1 and 5 simultaneously. In step S505, the memory controller 110 begins a read operation. In step S510, the memory controller 110 performs a read operation on the first page (e.g., page Pn) in the memory device to obtain first data corresponding to page Pn. In step S520, the memory controller 110 controls the ECC circuit 120 to perform an error correction operation based on the first data of page Pn.

[0026] In step S530, the memory controller 110 determines whether the error correction operation in step S520 has failed. The error correction operation in this embodiment is based on ECC technology to correct the first data. When the data error rate in the first data is lower than a preset value, the ECC circuit 120 can correct the errors in the first data using ECC technology, thereby restoring the first data to its correct content. If step S530 is negative (i.e., the error correction operation is successful), the first data has been successfully read from page Pn, so the process proceeds to step S560 to end the reading operation or to read the next page.

[0027] However, when the error rate in the first data is higher than the preset value, for example, when 450 or more bits in 4kB data are erroneous, the ECC circuit 120 can know that there are erroneous bits in the first data, but cannot perform error correction, thus causing the error correction operation in step S530 to fail.

[0028] In this embodiment of the invention, when step S530 is yes (i.e., the error correction operation fails), the memory controller 110 performs the adjacent data repair operation in step S540. The adjacent data repair operation uses the threshold voltage state of the adjacent character line adjacent to the target character line to attempt to correct the data of the memory cell on the target character line, thereby improving the long-term data retention of the memory cell and reducing the read failure rate. In step S550, the memory controller 110 determines whether the adjacent data repair operation has failed. When step S530 is yes (i.e., the adjacent data repair operation fails), step S540 can be repeated. On the other hand, when step S530 is no (i.e., the adjacent data repair operation succeeds), the first data has been successfully read from page Pn and the first data has been repaired through the adjacent data repair operation, so the process proceeds to step S560 to end the read operation or to perform a read operation on the next page.

[0029] Details of the adjacent data repair operation in step S540 are shown in Figure 6. Figure 6 is a detailed flowchart of step S540 in Figure 5. Figure 7 is a schematic diagram of steps S610 and S620 of Figure 6 according to the first embodiment of the present invention. Referring to Figures 6 and 7, in step S610 of Figure 6, the memory controller 110 performs a first read operation on the first word line (e.g., word line WLn) corresponding to page Pn to obtain the first threshold voltage state of the first page (page Pn). In steps S610-11 of Figure 7, the memory controller 110 provides a waveform 310-1 similar to waveform 310 in Figure 3 to word line WLn to obtain the potential state of the memory cell on word line WLn, and provides a pass voltage Vpass to adjacent word lines WLn-1 and WLn+1.

[0030] In step S620 of FIG6, the memory controller 110 performs a second read operation on at least one second word line (e.g., pages Pn-1 and Pn+1 corresponding to word lines WLn-1 and WLn+1 adjacent to word line WLn) to obtain at least one second threshold voltage state of the second page (e.g., pages Pn-1 and Pn+1 corresponding to adjacent word lines WLn-1 and WLn+1). The second page (pages Pn-1 and Pn+1) corresponds to the second word line (e.g., word line WLn-1 and WLn+1), and the second page (pages Pn-1 and Pn+1) is adjacent to the first page (page Pn).

[0031] In detail, in step S620-11 of FIG7, the memory controller 110 performs a second read operation on the first adjacent word line (word line WLn-1) to obtain the first adjacent threshold voltage state of the first adjacent page (page Pn-1). The first adjacent page (page Pn-1) is adjacent to the first page (page Pn) and located on one side of the first page (page Pn). The memory controller 110 provides a waveform 310-2, similar to waveform 310 in FIG3, to the word line WLn-1 to obtain the potential state of the memory cell on the word line WLn-1. Furthermore, a pass voltage Vpass is provided to multiple word lines (word lines WLn and WLn+1) other than the first adjacent word line (word line WLn-1).

[0032] In step S620-12 of FIG7, the memory controller 110 performs a second read operation on the second adjacent word line (word line WLn+1) to obtain the second adjacent threshold voltage state of the second adjacent page (page Pn+1). The second adjacent page (page Pn+1) is adjacent to the first page (page Pn) and located on the other side of the first page (page Pn). The memory controller 110 provides a waveform 310-3 similar to waveform 310 in FIG3 to the word line WLn+1 to obtain the potential state of the memory cell on the word line WLn+1. Furthermore, a pass voltage Vpass is provided to multiple word lines (word lines WLn-1 and WLn) other than the second adjacent word line (word line WLn+1).

[0033] FIG8 is a schematic diagram of step S630 of FIG6 according to the first embodiment of the present invention. Referring to FIG6 and FIG8 simultaneously, in step S630 of FIG6, the memory controller 110 corrects the first data corresponding to the first page (page Pn) according to the first threshold voltage state of the first page (page Pn) and the second threshold voltage state of the second page (page Pn-1 and Pn+1). For example, for reference to 820 in FIG8, assuming that the memory cell of the first page (page Pn) on the corresponding word line WLn is in a potential state F with a high critical voltage, and the memory cells of pages Pn-1 and Pn+1 on the corresponding word lines WLn-1 and WLn+1 are in an erased state eR with a low critical voltage, as can be seen from FIG4 above, the memory cells on the word line WLn are greatly affected by the charge loss effect at this time, so the memory cells on the word line WLn may originally be in a potential state G.

[0034] In this embodiment of the invention, the potential state that may be altered due to charge loss effects is recorded or stored in lookup table 810. The memory controller 110 consults lookup table 810 based on the first threshold voltage state of the first page corresponding to character line WLn and the second threshold voltage state of the second pages corresponding to character lines WLn-1 and WLn+1 to obtain inferred data, and uses or replaces this inferred data as the first data of the first page. For example, regarding FIG8 mark 820, the memory controller 110 consults a portion 825 of lookup table 810 and finds that the potential state F of the memory cell on the first page corresponding to character line WLn should be the potential state G. Therefore, the 'potential state G' in the portion 825 of lookup table 810 is the inferred data (or, referred to as, the corrected potential state). Regarding FIG8 mark 830, the memory controller 110 consults a portion 835 of lookup table 810 and finds that the potential state G of the memory cell on the first page corresponding to character line WLn is the same as the inferred data (potential state G), therefore no correction is required.

[0035] Based on the inferred data from step S630 in Figure 6, the data in the target memory cell can be tentatively corrected, thereby improving the long-term data retention of the memory cell and reducing the read failure rate. Circuit verification and corresponding experiments have confirmed that, without implementing step S540 in Figure 5, the first data in the read method of Figure 5 may have a bit error rate of 7.45%. Conversely, by implementing step S540 in Figure 5, the bit error rate of the first data in the read method of Figure 5 can be significantly reduced from 7.45% to 0.74%.

[0036] In some embodiments, users of this embodiment can decide whether to perform the adjacent data repair operation of S540 on character lines located at the edge (e.g., character lines WL1 and WLm) according to their needs. Alternatively, users of this embodiment can provide a corresponding lookup table for character lines located at the edge (e.g., character lines WL1 and WLm) to realize the adjacent data repair operation of S540.

[0037] The first embodiment, including Figures 7 and 8, exemplifies a memory cell in the memory device of Figure 1 that is in a multi-level form (e.g., TLC form), and the read operations in steps S610-11, S620-11, and S620-12 in Figure 7 are all performed based on multiple reference voltages VrA~VrG. To save the time consumed in performing the read operation, in the second embodiment of the present invention, the read operation can be performed on adjacent word lines (e.g., word lines WLn-1 and WLn+1) based on a single-level form (e.g., SLC form) reference voltage (e.g., reference voltage VrSLC). In other words, the read operation is performed on the page Pn-1 and Pn+1 of adjacent word lines (e.g., word lines WLn-1 and WLn+1) using a single-level form (e.g., SLC form) read operation and the corresponding reference voltage VrSLC, thereby reducing the time consumed in the read operation of adjacent word lines.

[0038] Figure 9 is a schematic diagram of steps S610 and S620 of Figure 6 according to the second embodiment of the present invention. Steps S610-21 in Figure 9 are the same as steps S610-11 in Figure 7, but steps S620-21 and S620-22 in Figure 9 are different from steps S620-11 and S620-12 in Figure 7. In step S620-21 in Figure 9, a single-stage reference voltage VrSLC is provided to the word line WLn-1 to determine whether the threshold voltage state of the page Pn-1 corresponding to the word line WLn-1 is logic "1" or logic "0", and an on-state voltage Vpass is provided to the word lines WLn and WLn+1. In steps S620-22 of Figure 9, a single-stage reference voltage VrSLC is provided to word line WLn+1 to determine whether the threshold voltage state of page Pn+1 corresponding to word line WLn+1 is logic "1" or logic "0", and a conduction voltage Vpass is provided to word lines WLn-1 and WLn. Users of this embodiment can construct the lookup table required for the second embodiment according to the construction method of lookup table 810 in Figure 8, and implement step S630 of Figure 6 based on this lookup table.

[0039] In the third embodiment, the memory cells in the memory device of FIG1 are implemented in a single-level form (e.g., SLC form). FIG10 is a schematic diagram of step S630 of FIG6 according to the present invention. In the third embodiment, the situation that the latent state may be changed due to charge loss effect is recorded or stored in lookup table 1010. The memory controller 110 consults lookup table 1010 according to the first threshold voltage state of the first page corresponding to the word line WLn and the second threshold voltage state of the second page corresponding to the word lines WLn-1 and WLn+1 to obtain inferred data, and uses this inferred data as or replaces the first data of the first page. For example, for reference to 1020 in FIG10, the memory controller 110 consults a portion 1025 of lookup table 1010 to find that the logic "0" of the memory cell on the first page corresponding to the word line WLn should be logic "1". Therefore, the "logic "1" in the portion 1025 of lookup table 1010 is the inferred data (or, the corrected latent state).

[0040] In summary, during a read operation on a specific memory region (e.g., a specific page) of the present invention, if the read correction operation based on the ECC circuit fails, the memory device of the present invention will perform an adjacent data repair operation. The adjacent data repair operation uses the threshold voltage state on the adjacent word lines adjacent to the target word line to attempt to correct the data of the memory cell on the target word line, thereby improving the long-term data retention of the memory cell and reducing the read failure rate.

[0041] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0042] Figure 1 is a schematic diagram of a memory controller, error correction code (ECC) circuit, and memory block in a three-dimensional (3D) inverse gate (NAND) memory device according to an embodiment of the present invention. Figure 2 is a schematic diagram illustrating, using a three-level cell (TLC) as an example, the distribution of multiple critical voltages in programmed operation and data retention in an embodiment of the present invention. Figure 3 is a waveform diagram of a read operation on a memory cell on a word line according to an embodiment of the present invention. Figure 4 is a schematic diagram of the lateral charge loss effect according to an embodiment of the present invention. Figure 5 is a flowchart of a read method for a memory device according to an embodiment of the present invention. Figure 6 is a detailed flowchart of step S540 in Figure 5. Figure 7 is a schematic diagram of steps S610 and S620 of Figure 6 according to a first embodiment of the present invention. Figure 8 is a schematic diagram of step S630 of Figure 6 according to a first embodiment of the present invention. Figure 9 is a schematic diagram of steps S610 and S620 of Figure 6 according to a second embodiment of the present invention. Figure 10 is a schematic diagram of step S630 of Figure 6 according to the present invention.

Claims

1. A method for reading a memory device, wherein the memory device includes at least one memory cell string, wherein the at least one memory cell string includes a plurality of memory cells, the plurality of memory cells are divided into multiple pages, the multiple pages corresponding to a plurality of character lines, the reading method comprising: When an error correction operation based on the first data of the first page fails, an adjacent data repair operation is performed, wherein the adjacent data repair operation includes: performing a first read operation on a first character line to obtain a first threshold voltage state of the first page, wherein the first page corresponds to the first character line; performing a second read operation on at least one second character line to obtain at least one second threshold voltage state of at least one second page, wherein the at least one second page corresponds to the at least one second character line and the at least one second page is adjacent to the first page; and correcting the first data corresponding to the first page based on the first threshold voltage state of the first page and the at least one second threshold voltage state of the at least one second page.

2. The reading method as described in request item 1, further comprising: Perform a read operation on the first page to obtain the first data corresponding to the first page; Perform the error correction operation based on the first data; And if the error correction operation performed based on the first data fails, the adjacent data repair operation is performed.

3. The reading method as described in request item 1, wherein, The step of correcting the first data corresponding to the first page based on the first threshold voltage state of the first page and the at least one second threshold voltage state of the at least one second page includes: consulting a lookup table based on the first threshold voltage state of the first page and the at least one second threshold voltage state of the at least one second page to obtain inferred data; and using the inferred data as the first data corresponding to the first page.

4. The reading method as described in request item 1, wherein, The step of performing the second read operation on the at least one second character line to obtain the at least one second threshold voltage state of the at least one second page includes: performing the second read operation on a first adjacent character line to obtain a first adjacent threshold voltage state of a first adjacent page, wherein the first adjacent page is adjacent to the first page and located on one side of the first page, and providing a through voltage to the plurality of character lines other than the first adjacent character line; performing the second read operation on a second adjacent character line to obtain a second adjacent threshold voltage state of a second adjacent page, wherein the second adjacent page is adjacent to the first page and located on the other side of the first page, and providing the through voltage to the plurality of character lines other than the second adjacent character line.

5. The reading method as described in claim 1, wherein the plurality of memory cells are constituted in a multi-level form.

6. The read method as claimed in claim 5, wherein the first read operation is performed based on a plurality of reference voltages corresponding to the multi-level form of the plurality of memory cells, and the second read operation is performed based on the plurality of reference voltages corresponding to the multi-level form of the plurality of memory cells.

7. The read method as claimed in claim 5, wherein the first read operation is performed based on a plurality of reference voltages corresponding to the multi-level form of the plurality of memory cells, and the second read operation is performed based on a single reference voltage corresponding to the single-level form of the plurality of memory cells.

8. The reading method as described in claim 1, wherein the plurality of memory cells are constituted in a single-level form.

9. A memory device, comprising: A memory array including memory blocks, wherein the memory blocks include at least one memory cell string, wherein the at least one memory cell string includes a plurality of memory cells divided into multiple pages, the multiple pages corresponding to a plurality of word lines; a memory controller for controlling the memory array; and an error correction code (ECC) circuit coupled to the memory controller to perform an error correction operation, wherein the memory controller is configured to perform: when an error correction operation based on first data of a first page fails, performing an adjacent data repair operation, wherein the adjacent data repair operation includes: performing a first read operation on a first word line to obtain a first threshold voltage state of the first page, wherein the first page corresponds to the first word line; performing a second read operation on at least one second word line to obtain at least one second threshold voltage state of the at least one second page, wherein the at least one second page corresponds to at least one second word line and the at least one second page is adjacent to the first page; and correcting the first data corresponding to the first page based on the first threshold voltage state of the first page and the at least one second threshold voltage state of the at least one second page.

10. The memory device of claim 9, wherein the memory controller is further configured to perform: performing a read operation on the first page to obtain the first data corresponding to the first page; performing the error correction operation based on the first data; and performing the adjacent data repair operation if the error correction operation performed based on the first data fails.

11. The memory device of claim 9, wherein the memory controller consults a lookup table to obtain inferred data based on the first threshold voltage state of the first page and the at least one second threshold voltage state of the at least one second page, and the memory controller uses the inferred data as the first data corresponding to the first page.

12. The memory device of claim 9, wherein the memory controller performs the second read operation on a first adjacent character line to obtain a first adjacent threshold voltage state of a first adjacent page, wherein the first adjacent page is adjacent to and located on one side of the first page, and provides a pass voltage to the plurality of character lines other than the first adjacent character line; and the memory controller performs the second read operation on a second adjacent character line to obtain a second adjacent threshold voltage state of a second adjacent page, wherein the second adjacent page is adjacent to and located on the other side of the first page, and provides the pass voltage to the plurality of character lines other than the second adjacent character line.

13. The memory device as claimed in claim 9, wherein the plurality of memory cells are configured in a multi-level manner.

14. The memory device of claim 13, wherein the first read operation is performed based on a plurality of reference voltages corresponding to the multi-level form of the plurality of memory cells, and the second read operation is performed based on the plurality of reference voltages corresponding to the multi-level form of the plurality of memory cells.

15. The memory device of claim 13, wherein the first read operation is performed based on a plurality of reference voltages corresponding to the multi-level form of the plurality of memory cells, and the second read operation is performed based on a single reference voltage corresponding to the single-level form of the plurality of memory cells.

16. The memory device as claimed in claim 9, wherein the plurality of memory cells are configured in a single-level manner.

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