arithmetic unit

Abstract

A computing device is provided. The computing device includes an arithmetic circuit section having a plurality of arithmetic units that hold first data, a drive circuit that outputs second data to the arithmetic circuit section, a first sample-and-hold circuit section, a switching section, and a second sample-and-hold circuit section. The arithmetic circuit section supplies a first current corresponding to the sum of currents flowing through the arithmetic units to which the second data is supplied to the first sample-and-hold circuit section. The first sample-and-hold circuit section holds a plurality of third data corresponding to the first current by switching the second data. The switching section supplies a second current corresponding to the sum of currents flowing through the switches from the plurality of first sample-and-hold units to the second sample-and-hold circuit section. The second sample-and-hold circuit section holds a plurality of fourth data corresponding to the second current by switching the paths of the switches.

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