Systems and methods for high performance read with on-die circuits

Abstract

The present disclosure relates to a flash memory system including a controller and one or more memory integrated circuits. Each of the one or more memory integrated circuits may include a circuit and a non-volatile memory comprising one or more blocks. Each block may include a plurality of rows of cells. The circuit may perform a read operation on a page of the non-volatile memory. The circuit may decode data of the page. In response to determining that decoding of the data fails, the controller may read the data from the non-volatile memory. The controller may decode the data.

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