Clock and data recovery for high-speed serial communication applications

Abstract

or 4-quadrant phase detector driving an analog loop filter, low-speed digital control loop, and phase interpolator. The phase interpolator may rotate the reference clock to be centered within the data eye for a low bit error rate. The CDR may track out frequency errors between the reference clock and incoming data stream without losing lock or loss of data. In integrated circuit implementations, the CDR consumes low die area due to the lack of VCOs.

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