Time-to-digital converter and phase-locked loop circuit

Abstract

The present disclosure provides a time-to-digital converter and a phase-locked loop circuit for converting a time difference between a first signal and a second signal into a digital code, including a time-to-voltage conversion module and an analog-to-digital conversion module. The time-to-voltage conversion module includes a current source, a control switch, and a capacitor bank, wherein the control switch is configured to control the current source to charge and discharge the capacitor bank to generate a voltage proportional to the time difference, in response to the first signal, and the analog-to-digital conversion module is configured to sample a voltage on the capacitor bank and convert the voltage into a multi-bit digital code, in response to the second signal.

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