Receiving device, equalizer module and signal processing method

Abstract

The present disclosure provides a receiving device comprising: an equalizer configured to encode a multistage pulse amplitude modulated signal sample into an intermediate mapping symbol, wherein the LSB of the intermediate mapping symbol represents positive or negative, and at least one MSB of the intermediate mapping symbol represents an absolute value of signal amplitude; and a demapper configured to demap the intermediate mapping symbol and output a restoring encoding symbol.

Description

Technical Field

[0001] This invention relates to a receiving device, an equalizer module, and a signal processing method. Prior Technology

[0002] Electronic transmission systems can be used in wired or wireless communication systems. They consist of a transmitter, a receiver, and a communication channel. The signal transmitted by the transmitter is received by the receiver via the communication channel. However, the characteristics of the communication channel can affect the signal transmission quality. To compensate for this, the receiver can be configured with an equalizer. For example, a decision feedback equalizer (DFE) can be configured in the receiver of a serializer / deserializer (SerDes). However, for high-speed transmission applications, such as signals with multi-stage pulse amplitude modulation, a larger area must be allocated within the receiver circuitry to accommodate the equalizer and related processing circuitry in order to maintain signal transmission quality. Summary of the Invention

[0003] This disclosure provides a receiving apparatus comprising: an equalizer for encoding a multi-order pulse amplitude modulated signal sample into an intermediate mapping symbol, wherein the LSB (Least Significant Bit) of the intermediate mapping symbol represents the sign, and at least one MSB (Most Significant Bit) of the intermediate mapping symbol represents the absolute value of the signal amplitude; and a demapper for demapping the intermediate mapping symbol and outputting a restored encoded symbol.

[0004] This disclosure provides a signal processing method, comprising: encoding a multi-order pulse amplitude modulated signal sample into an intermediate mapping symbol, wherein the LSB of the intermediate mapping symbol represents the sign, and at least one MSB of the intermediate mapping symbol represents the absolute value of the signal amplitude; and demapping the intermediate mapping symbol to output a restored encoded symbol.

[0005] This disclosure provides an equalizer module comprising: a plurality of decision units for encoding a multi-order pulse amplitude modulated signal sample into an intermediate mapping symbol, wherein the LSB of the intermediate mapping symbol represents the sign and at least one MSB of the intermediate mapping symbol represents the absolute value of the signal amplitude; and a demapper for demapping the intermediate mapping symbol and outputting a restored encoded symbol.

[0006] In some embodiments, the multi-order pulse amplitude modulation system is a fourth-order pulse amplitude modulation system. In some embodiments, when the potential of the signal sample is greater than a first threshold, the intermediate mapping symbol is 11; when the potential of the signal sample is greater than a second threshold and less than the first threshold, the intermediate mapping symbol is 01; when the potential of the signal sample is greater than the third threshold and less than the second threshold, the intermediate mapping symbol is 00; and when the potential of the signal sample is less than the third threshold, the intermediate mapping symbol is 10. In some embodiments, the demapping includes: when the intermediate mapping symbol is 11, outputting the restored encoding symbol as 11; when the intermediate mapping symbol is 01, outputting the restored encoding symbol as 10; when the intermediate mapping symbol is 00, outputting the restored encoding symbol as 01; and when the intermediate mapping symbol is 10, outputting the restored encoding symbol as 00. In some embodiments, the LSB of the intermediate mapping symbol is 1 when the potential of the signal sample is greater than an intermediate reference value; and the LSB of the intermediate mapping symbol is 0 when the potential of the signal sample is less than the intermediate reference value. In some embodiments, the at least one MSB of the intermediate mapping symbol represents the absolute value of the potential of the signal sample relative to the intermediate reference value.

[0007] In some embodiments, the equalizer is a decision feedback equalizer (DFE), and the receiving device further includes: a continuous time linear equalizer (CTLE) coupled to the decision feedback equalizer; a deserializer for deserializing the restored encoded symbol; and a clock data recovery circuit coupled to the decision feedback equalizer, the demapping unit, and the deserializer.

[0008] In some embodiments, the encoding step is performed using a decision feedback equalizer (DFE). In some embodiments, the signal processing method further includes: processing the multi-stage pulse amplitude modulated signal sample using a continuous time linear equalizer (CTLE); and deserializing the restored encoded symbol. Simple Explanation of the Diagram

[0009] To fully understand the nature, advantages, and preferred embodiments of the present invention, the following description is provided in conjunction with the accompanying drawings for a clearer understanding.

[0010] Figure 1 shows a block diagram illustrating a SerDes communication system according to some embodiments.

[0011] Figure 2 shows a block diagram illustrating a decision feedback equalizer according to some embodiments.

[0012] Figure 3 shows a signal eye diagram, illustrating a signal sample and encoding of fourth-order pulse amplitude modulation according to some embodiments.

[0013] Figure 4 shows a table displaying a demapping lookup table according to some embodiments.

[0014] Figures 5A to 5C show schematic diagrams illustrating the decision-making of a data decision-maker according to some embodiments.

[0015] Figure 5D shows a schematic diagram illustrating the potential mapping relationship between a reference DL and a reference DH according to some embodiments. Implementation

[0016] The following description illustrates preferred embodiments of the invention. The invention is described in detail below with reference to embodiments and accompanying drawings. Therefore, the invention is not intended to be limited to the embodiments shown, but rather to conform to the principles disclosed herein. Furthermore, various modifications or alterations suggested by those skilled in the art are welcome and will be incorporated into the spirit and scope of this application and the appended claims.

[0017] The embodiments disclosed herein can be used in a serializer / deserializer (SerDes) architecture. SerDes are a pair of functional blocks commonly used in high-speed communication to provide data transmission and convert data between parallel and serial interfaces.

[0018] In high-speed communication, the characteristics of the communication channel affect the quality of signal transmission. Signal distortion causes inter-symbol interference (ISI) and degrades signal transmission quality, such as increasing the bit error rate (BER). SerDes architecture receivers may include equalizers to compensate for the effects of the communication channel. SerDes architecture transmitters may also include equalizers to prevent the receiver from misinterpreting or failing to interpret damaged signals.

[0019] The Decision Feedback Equalizer (DFE) is an equalizer used in the SerDes architecture receiver to compensate for inter-symbol interference. The DFE is used for post-label ISI correction and does not amplify noise during the process, thus avoiding the drawback of error amplification.

[0020] Figure 1 shows a block diagram illustrating a SerDes communication system according to some embodiments. In the SerDes communication system of Figure 1, a transmitting device 1 is communicatively coupled to a receiving device 3 via a communication channel 2. The transmitting device 1 is used to transmit one or more signals to the receiving device 3 via the communication channel 2. The receiving device 3 may include one or more finite impulse response filters for conditioning data before transmission to the communication channel 2. The communication channel 2 may be a physical transmission medium, such as an optical fiber, cable, or wire, etc., or the communication channel 2 may include a wireless channel, such as a radio frequency (RF) channel, etc.

[0021] The transmitting device 1 includes a serializer 11, a transmitter equalizer 12, and a transmitter clock generator 13. The transmitter clock generator 13 provides clock signals to the serializer 11 and the transmitter equalizer 12. The serializer 11 is used to convert the input parallel signals into sequential signals. For example, the serializer 11 can sequentially output the parallel signals DTX[N-1:0] into a plurality of continuous data according to the clock signal. The transmitter clock generator 13 can be a phase-locked loop (PLL), which can generate a clock signal according to a reference clock.

[0022] The output of serializer 11 is output to communication channel 2 after passing through transmitter equalizer 12 to provide pre-equalization of the signal to compensate for (e.g., cancel) unexpected signal distortion. Transmitter equalizer 12 may include, for example, a finite impulse response (FIR) equalizer or a feed forward equalizer (FFE), etc.

[0023] The signal transmitted from the transmitting device 1 to the receiving device 3 via the communication channel 2 can be a multi-level pulse amplitude modulation (PAM) signal, such as a four-level pulse amplitude modulation (PAM4) signal.

[0024] The receiving device 3 includes an equalizer 32, a demapper 33, a deserializer 34, and a receiving clock generator 35. The signal received by the receiving device 3 from the communication channel 2 is processed by the equalizer 32, which encodes a multi-order pulse amplitude modulated signal sample into an intermediate mapping symbol. The demapper 33 demaps the intermediate mapping symbol and outputs a restored encoded symbol. The LSB (Least Significant Bit) of the intermediate mapping symbol represents the sign (Sgn), and at least one MSB of the intermediate mapping symbol represents the absolute value of the signal amplitude. The deserializer 34 converts the input sequence signal into parallel signals and can be used to deserialize the restored encoded symbol. For example, the deserializer 34 can output the restored encoded symbol as parallel signals DRX[N-1:0].

[0025] In some embodiments, equalizer 32 may include a plurality of decision units for encoding signal samples of multi-order pulse amplitude modulation into intermediate mapping symbols. The plurality of decision units and demapping unit 33 may be included in an equalizer module. For example, equalizer 32 and demapping unit 33 may be regarded together as an equalizer module.

[0026] The receiver clock generator 35 is, for example, a clock data recovery circuit. The receiver clock generator 35 is coupled to equalizer 32, demapping unit 33 and deserializer 34, and provides clock signals to equalizer 32, demapping unit 33 and deserializer 34.

[0027] The receiving device 3 may include an equalizer 31, such as a continuous time linear equalizer (CTLE). The signal received by the receiving device 3 from the communication channel 2 may be processed by the equalizer 31 first, and then by the equalizer 32. The equalizer 32 may be, for example, a decision feedback equalizer.

[0028] The multi-stage pulse amplitude modulation (MPLM) signal transmitted by the transmitting device 1 has an original encoding method. The receiving device 3 must restore the received MPLM signal sample to obtain the data code corresponding to the original encoding method, thereby obtaining the data code that the transmitting device 1 wants to transmit. The receiving device 3 does not restore the data code directly to the original encoding method in one stage, but adopts a two-stage process. The first stage is to encode the MPLM signal sample into an intermediate mapping symbol. The encoding method of the intermediate mapping symbol does not correspond to the original encoding method. Then, in the second stage, the intermediate mapping symbol is demapped to obtain the restored encoding symbol. The restored encoding symbol is the data code corresponding to the original encoding method. The mapping encoding in the first stage and the demapping in the second stage, as a whole, correspond to the original encoding method.

[0029] In some embodiments, the intermediate mapping symbols may contain Gray code properties, which has the advantage of avoiding signal transmission errors. In some embodiments, the above architecture and encoding allow for a simpler implementation of the decision feedback equalizer (e.g., equalizer 32) and the clock data recovery circuit (receiver clock generator 35). Furthermore, in some embodiments, the decision for the major transition (Mjr) only requires checking the absolute oscillation (power), which can reduce the circuit area for data decision-making by one-third.

[0030] Figure 2 shows a block diagram illustrating a decision feedback equalizer according to some embodiments. In Figure 2, the equalizer 32 includes a slicer 321, a plurality of delay units 322, and a plurality of feedback blocks 323. The output of the slicer 321 is fed back to the corresponding feedback block 323 at each tap point after passing through the delay units 322. Each feedback block 323 corresponds to the output of the slicer 321 with a different delay time.

[0031] Figure 3 shows a signal eye diagram illustrating a fourth-order pulse amplitude modulation (PAM4) signal sample and its encoding according to some embodiments. In Figure 3, the PAM4 signal sample is encoded with an intermediate mapping symbol based on the sign and absolute value of the potential. The intermediate mapping symbol can be represented by (Mjr, Sgn), where the LSB of the intermediate mapping symbol represents the sign, and the MSB represents the absolute value of the signal amplitude. The sign is based on an intermediate reference value; a signal sample with a potential greater than the intermediate reference value is positive, and the LSB of the intermediate mapping symbol can be set to 1 (Sgn=1); a signal sample with a potential less than the intermediate reference value is negative, and the LSB of the intermediate mapping symbol can be set to 0 (Sgn=0). The absolute value can be a quantized value, such as the quantized difference between the potential of the signal sample and the intermediate reference value. At least one MSB of the intermediate mapping symbol represents the absolute value of the potential of the signal sample relative to the intermediate reference value.

[0032] If we consider the potentials from low to high, the corresponding intermediate mapping symbols are 10, 00, 01, and 11. For example, when the potential of a signal sample is greater than a first threshold, the intermediate mapping symbol is 11; when the potential of a signal sample is greater than a second threshold and less than the first threshold, the intermediate mapping symbol is 01; when the potential of a signal sample is greater than a third threshold and less than the second threshold, the intermediate mapping symbol is 00; and when the potential of a signal sample is less than the third threshold, the intermediate mapping symbol is 10. The second threshold can be an intermediate reference value, and the first and third thresholds are used for quantization to generate codes representing absolute values. The first, second, and third thresholds correspond to the potentials referenced by DH, DZ, and DL in Figure 3.

[0033] In some embodiments, a plurality of decision units can be used to process fourth-order pulse amplitude modulation signal samples. For example, a plurality of decision units can be used to encode multi-order pulse amplitude modulation signal samples into an intermediate mapping symbol. The plurality of decision units may include a data slicer, an error slicer, and a crossing slicer. In Figure 3, DH, DZ, and DL represent the potentials referenced by the data slicers, EHP, ELP, ELN, and EHN represent the potentials referenced by the error slicers, and CH, CZ, and CL represent the crossings referenced by the crossing slicers. If vertical symmetry is assumed, then DH = -DL, EHP = -EHN, and ELP = -ELN (=h0). If linearity is assumed, then DH = 2*ELP (=2*h0), EHP = 3*ELP (=3*h0), DL = 2*ELN (=-2*h0), and EHN = 3*ELN (=-3*h0).

[0034] In the case of fourth-order pulse amplitude modulation signal samples, the difference between the previous data code and the next data code is only 1 bit. The encoding of the intermediate mapping symbol has the property of Gray code, which has the advantage of avoiding signal transmission errors. This encoding method also allows for a simpler implementation of the decision feedback equalizer (e.g., equalizer 32) and the clock data recovery circuit (receiver clock generator 35).

[0035] In the signal eye diagram of Figure 3, if the traditional encoding of the PAM4 signal is adopted, the data code is generated in the order of low to high potential. For example, the data codes 00, 01, 10, and 11 are generated in the order of low to high potential. However, this encoding is not Gray code.

[0036] In some embodiments, the encoding method of the intermediate mapping symbol is different from the original encoding method of the multi-order pulse amplitude modulation signal transmitted by the transmitting device 1. For example, the transmitting device 1 uses the above-mentioned conventional encoding method for PAM4 signals to represent the data code, while the encoding method of the intermediate mapping symbol in the aforementioned embodiments is different.

[0037] Figure 4 shows a table illustrating a demapping lookup table according to some embodiments. Demapping is the process of restoring intermediate mapped symbols to data codes in the original encoding method of the multi-pulse amplitude modulation signal samples in the transmitting device 1. Demapping is the process of restoring intermediate mapped symbols to data codes represented in the conventional encoding method for multi-pulse amplitude modulation signals.

[0038] In Figure 4, multi-order pulse amplitude modulation (MPAM) is used as an example of PAM4. Demapping involves restoring the intermediate mapped symbols to data codes represented by the traditional encoding method for PAM4 signals. For example, when the intermediate mapped symbol is 11, the output restored encoded symbol is 11; when the intermediate mapped symbol is 01, the output restored encoded symbol is 10; when the intermediate mapped symbol is 00, the output restored encoded symbol is 01; and when the intermediate mapped symbol is 10, the output restored encoded symbol is 00.

[0039] Figures 5A to 5C show schematic diagrams illustrating the decision-making of a data decision unit according to some embodiments. In Figure 5A, the potential DZ referenced by the data decision unit is used for sign determination, and the judgment interval is vertically symmetrical. In Figures 5B and 5C, the potentials DH and DL referenced by the data decision unit are used for signal amplitude absolute value determination. When the absolute value of the signal amplitude is large (or the absolute value of the signal potential is large), Mjr is set to 1, and otherwise to 0. Figure 5D shows a schematic diagram illustrating the potential mapping relationship between the reference DL and the reference DH according to some embodiments. The horizontal axis V is the voltage before mapping, and the vertical axis V' is the voltage after mapping. In Figures 5B and 5D, the absolute value decision made with DH does not require sign mapping, or it is a mapping with the same positive and negative directions. In Figures 5C and 5D, the absolute value decision made with DL requires a mapping with opposite positive and negative directions. After mapping, the method of making the absolute value decision with DL is the same as with DH, for example, Mjr is set to 1 when the potential V' is large, and 0 otherwise. Since DH and DL only need to check the absolute oscillation (power) for the major transition (Mjr) decision, this method can reduce the circuit area by one-third for data decision making.

[0040] Furthermore, this disclosure provides a receiving apparatus comprising: an equalizer for encoding a multi-order pulse amplitude modulated signal sample into an intermediate mapping symbol, wherein the LSB of the intermediate mapping symbol represents the sign, and at least one MSB of the intermediate mapping symbol represents the absolute value of the signal amplitude; and a demapper for demapping the intermediate mapping symbol and outputting a restored encoded symbol. The receiving apparatus of this disclosure can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0041] Furthermore, this disclosure also provides a signal processing method, comprising: encoding a multi-order pulse amplitude modulated signal sample into an intermediate mapping symbol, wherein the LSB of the intermediate mapping symbol represents the sign, and at least one MSB of the intermediate mapping symbol represents the absolute value of the signal amplitude; and demapping the intermediate mapping symbol to output a restored encoded symbol. The signal processing method of this disclosure can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0042] Furthermore, this disclosure also provides an equalizer module, comprising: a plurality of decision units for encoding a multi-order pulse amplitude modulated signal sample into an intermediate mapping symbol, wherein the LSB of the intermediate mapping symbol represents the sign, and at least one MSB of the intermediate mapping symbol represents the absolute value of the signal amplitude; and a demapper for demapping the intermediate mapping symbol and outputting a restored encoded symbol. The equalizer module of this disclosure can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0043] Without further detailed description, it is believed that those skilled in the art will be able to utilize the invention to its fullest extent based on the foregoing description. Therefore, the specific embodiments should be interpreted as illustrative only and not as limiting the remainder of this disclosure in any way.

[0044] 1: Launching device

[0045] 2: Communication Channel

[0046] 3: Receiving device

[0047] 11: Serializer

[0048] 12: Transmitter equalizer

[0049] 13: Transmitter clock generator

[0050] 32: Isostat

[0051] 33: Demapping

[0052] 34: Deserializer

[0053] 35: Receiver clock generator

[0054] 31: Irradiator

[0055] 321: Decision Maker

[0056] 322: Delay Unit

[0057] 323: Feedback Block

[0058] DH, DZ, DL: The reference potentials of the data decision unit

[0059] EHP, ELP, ELN, EHN: The potentials referenced by the error decision unit.

[0060] CH, CZ, CL: Cross-connectors referenced by the cross-connect decision mechanism

Claims

1. A receiving device, comprising: an equalizer for encoding a multi-order pulse amplitude modulated signal sample into an intermediate mapping symbol, wherein, The intermediate mapping symbol has an LSB representing the positive or negative polarity of the signal sample, and at least one MSB representing the absolute value range of the amplitude of the signal sample; and a demapper for demapping the intermediate mapping symbol to output a restored coded symbol.

2. The receiving apparatus as claimed in claim 1, wherein the multi-order pulse amplitude modulation system is a fourth-order pulse amplitude modulation system.

3. The receiving device as described in claim 2, wherein, When the potential of the signal sample is greater than a first threshold, the intermediate mapping symbol is 11; when the potential of the signal sample is greater than a second threshold and less than the first threshold, the intermediate mapping symbol is 01; when the potential of the signal sample is greater than the third threshold and less than the second threshold, the intermediate mapping symbol is 00; and when the potential of the signal sample is less than the third threshold, the intermediate mapping symbol is 10.

4. The receiving apparatus as claimed in claim 2, wherein the demapping performed by the demapping unit comprises: outputting the restored encoding symbol as 11 when the intermediate mapping symbol is 11; outputting the restored encoding symbol as 10 when the intermediate mapping symbol is 01; outputting the restored encoding symbol as 01 when the intermediate mapping symbol is 00; and outputting the restored encoding symbol as 00 when the intermediate mapping symbol is 10.

5. The receiving device as claimed in claim 1, wherein, When the potential of the signal sample is greater than an intermediate reference value, the LSB of the intermediate mapped symbol is 1; and when the potential of the signal sample is less than the intermediate reference value, the LSB of the intermediate mapped symbol is 0.

6. The receiving device as described in claim 5, wherein, The at least one MSB of the intermediate mapping symbol represents the absolute value of the potential of the signal sample relative to the intermediate reference value.

7. The receiving apparatus as claimed in claim 1, wherein the equalizer is a decision feedback equalizer (DFE), the receiving apparatus further comprising: a continuous time linear equalizer (CTLE) coupled to the decision feedback equalizer; a deserializer for deserializing the restored encoded symbol; and a clock data recovery circuit coupled to the decision feedback equalizer, the demapping unit and the deserializer.

8. An equalizer module, comprising: a plurality of decision units for encoding a multi-order pulse amplitude modulated signal sample into an intermediate mapping symbol, wherein, The intermediate mapping symbol has an LSB representing the positive or negative polarity of the signal sample, and at least one MSB representing the absolute value range of the amplitude of the signal sample; and a demapper for demapping the intermediate mapping symbol to output a restored coded symbol.

9. The equalizer module as claimed in claim 8, wherein the multi-order pulse amplitude modulation system is a fourth-order pulse amplitude modulation system.

10. The equalizer module as described in claim 9, wherein, When the potential of the signal sample is greater than a first threshold, the intermediate mapping symbol is 11; when the potential of the signal sample is greater than a second threshold and less than the first threshold, the intermediate mapping symbol is 01; when the potential of the signal sample is greater than the third threshold and less than the second threshold, the intermediate mapping symbol is 00; and when the potential of the signal sample is less than the third threshold, the intermediate mapping symbol is 10.

11. The equalizer module as claimed in claim 9, wherein the demapping performed by the demapping includes: outputting the restored encoding symbol as 11 when the intermediate mapping symbol is 11; outputting the restored encoding symbol as 10 when the intermediate mapping symbol is 01; outputting the restored encoding symbol as 01 when the intermediate mapping symbol is 00; and outputting the restored encoding symbol as 00 when the intermediate mapping symbol is 10.

12. The equalizer module as described in claim 8, wherein, When the potential of the signal sample is greater than an intermediate reference value, the LSB of the intermediate mapped symbol is 1; and when the potential of the signal sample is less than the intermediate reference value, the LSB of the intermediate mapped symbol is 0.

13. The equalizer module as described in claim 12, wherein, The at least one MSB of the intermediate mapping symbol represents the absolute value of the potential of the signal sample relative to the intermediate reference value.

14. A signal processing method, comprising: encoding a multi-order pulse amplitude modulated signal sample into an intermediate mapping symbol, wherein, The LSB of the intermediate mapping symbol represents the positive or negative polarity of the signal sample, and at least one MSB of the intermediate mapping symbol represents the absolute value range of the amplitude of the signal sample; and the intermediate mapping symbol is demapped to output a restored coded symbol.

15. The method as described in claim 14, wherein the multi-order pulse amplitude modulation system is a fourth-order pulse amplitude modulation system.

16. The method as described in claim 15, wherein, When the potential of the signal sample is greater than a first threshold, the intermediate mapping symbol is 11; when the potential of the signal sample is greater than a second threshold and less than the first threshold, the intermediate mapping symbol is 01; when the potential of the signal sample is greater than the third threshold and less than the second threshold, the intermediate mapping symbol is 00; and when the potential of the signal sample is less than the third threshold, the intermediate mapping symbol is 10.

17. The method of claim 15, wherein the demapping comprises: outputting the decoded symbol as 11 when the intermediate mapping symbol is 11; outputting the decoded symbol as 10 when the intermediate mapping symbol is 01; outputting the decoded symbol as 01 when the intermediate mapping symbol is 00; and outputting the decoded symbol as 00 when the intermediate mapping symbol is 10.

18. The method as described in claim 14, wherein, When the potential of the signal sample is greater than an intermediate reference value, the LSB of the intermediate mapped symbol is 1; and when the potential of the signal sample is less than the intermediate reference value, the LSB of the intermediate mapped symbol is 0.

19. The method as described in claim 18, wherein, The at least one MSB of the intermediate mapping symbol represents the absolute value of the potential of the signal sample relative to the intermediate reference value.

20. The method of claim 14, wherein the encoding step is performed using a decision feedback equalizer (DFE), the method further comprising: processing the multi-stage pulse amplitude modulated signal sample with a continuous time linear equalizer (CTLE); and deserializing the restored encoded symbol.

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