A method for forming 3D memory structure

TW202642806AActive Publication Date: 2026-10-16MACRONIX INTERNATIONAL CO LTD
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Patent Information

Application Number
TW114113758
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Filing Date
2025-04-11
Publication Date
2026-10-16
Estimated Expiration
2045-04-10

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    Figure TWG2TA001080284_003
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Abstract

A 3D memory structure is provided. The 3D memory structure includes a substrate, a stack, a plurality of holes, a plurality of memory layers, a plurality of epitaxial channel layers, and a plurality of dielectric pillars. The stack is disposed on the substrate. The stack includes alternating gate layers and dielectric layers. The holes penetrate through the stack. The memory layers are disposed on sidewalls of the holes, respectively. The epitaxial channel layers are disposed on the memory layers, respectively. The epitaxial channel layers are landed on the substrate. The dielectric pillars are disposed in spaces defined by the epitaxial channel layers, respectively.
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Claims

1. A method for forming a three-dimensional memory structure, comprising: A stack is formed on a substrate, the stack comprising a plurality of first layers and a plurality of second layers alternately arranged on each other; Multiple holes are formed penetrating the stack; A plurality of memory layers are formed on the sidewalls of the holes; after forming the memory layers, a plurality of channel material pillars are epitaxially grown from the corresponding portions of the substrate exposed by the holes; spacer layers are formed on the stack and the portions of the memory layers above the channel material pillars; the central portions of the channel material pillars are removed using the spacer layers as a mask to form a plurality of epitaxial channel layers on the memory layers; and a plurality of dielectric pillars are formed in the spaces defined by the epitaxial channel layers.

2. The method for forming a three-dimensional memory structure as described in claim 1, wherein, The first layer of the stack includes a plurality of sacrificial layers, the second layer of the stack is a dielectric layer, and wherein the upper surface of the channel material pillar is higher than the upper surface of the uppermost sacrificial layer, the upper surface of the channel material pillar being at least 100 Å higher than the upper surface of the uppermost sacrificial layer.

3. The method for forming a three-dimensional memory structure as described in claim 1, further comprising: Before forming the memory layer, a plurality of vertical dielectric layers are conformally formed into the holes; The memory layers are respectively conformally formed on the vertical dielectric layer; And by opening the bottom of the hole to expose the corresponding portion of the substrate from which the channel material pillar grows.

4. The method for forming a three-dimensional memory structure as described in claim 1, further comprising: Dielectric material is provided onto the spacer layer and filled into the remaining space of the holes; And removing a portion of the spacer layer above the epitaxial channel layer and a portion of the dielectric material above the epitaxial channel layer; wherein the remaining portion of the dielectric material in the hole forms the dielectric pillar.

5. The method for forming a three-dimensional memory structure as described in claim 4, further comprising: A plurality of plugs are formed on the dielectric pillar and the epitaxial channel layer.