Integrated circuit and manufacturing method thereof

Abstract

In some embodiments, an integrated circuit is provided. The integrated circuit includes a transistor arranged along a semiconductor substrate, an interconnect structure overlying the transistor, and a memory cell overlying the transistor and coupled to the transistor by the interconnect structure. The interconnect structure includes a plurality of conductive lines respectively arranged in a plurality of conductive interconnect layers, and a plurality of conductive vias. The memory cell includes a plurality of resistance changing elements that are coupled to one another by the interconnect structure, and are arrange vertically between a first conductive interconnect layer and a second conductive interconnect layer of the plurality of conductive interconnect layers, the second conductive interconnect layer overlying and being adjacent to the first conductive interconnect layer.

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