Nitride semiconductor device and manufacturing method of nitride semiconductor device

Abstract

The present disclosure provides a nitride semiconductor device including a substrate, a channel layer, a first polarization layer, a polarization control layer and a second polarization layer. The channel layer is disposed on the substrate, the first polarization layer is disposed on the channel layer, the polarization control layer is disposed on the first polarization layer, and the second polarization layer is disposed on the polarization control layer. The lattice constants of the first polarization layer and the lattice constants of the second polarization layer is less than the lattice constants of the polarization control layer. By the configuration of the first polarization layer, the polarization control layer and the second polarization layer, the 2DEG of the channel layer is adjusted.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a nitride semiconductor device and a method for manufacturing the nitride semiconductor device. Prior Technology

[0002] Gallium nitride high electron mobility transistor (GaN HEMT) technology has ushered in a new era for power converters, achieving unprecedented high operating frequencies and power densities. However, power converters using GaN HEMTs inevitably possess large parasitic parameters, which can cause gate voltage oscillations during high-speed switching. Furthermore, the low threshold voltage of GaN HEMTs can lead to false turn-on.

[0003] For normally-off operation of GaN HEMTs, common practices include: (1) placing a p-type gallium nitride layer or a gate-side layer below the gate of the GaN HEMT to increase its threshold voltage. Since the p-type gallium nitride layer usually needs to be matched with the gate, it needs to be etched. However, etching the p-type gallium nitride layer will damage the surface of the barrier layer of the GaN HEMT, thus affecting the performance of the GaN HEMT. (2) using fluoride ion treatment around the gate of the GaN HEMT to accumulate fluoride ions at the interface between the channel layer and the barrier layer, thereby increasing the threshold voltage of the GaN HEMT. However, fluoride ions will damage the surface of the barrier layer of the GaN HEMT, thus affecting its performance. Summary of the Invention

[0004] Based on the foregoing, this application provides a nitride semiconductor device and a method for manufacturing a nitride semiconductor device to solve the problem of accidental activation of GaN HEMT.

[0005] Based on the foregoing, this application provides a nitride semiconductor device, including a substrate, a channel layer, a first polarization layer, a polarization control layer, and a second polarization layer. The channel layer is disposed on the substrate, the first polarization layer is disposed on the channel layer, the polarization control layer is disposed on the first polarization layer, and the second polarization layer is disposed on the polarization control layer. The lattice constants of the first polarization layer and the second polarization layer are smaller than the lattice constant of the polarization control layer.

[0006] Based on the foregoing, this application provides a nitride semiconductor device, including a substrate, a channel layer, a spacer layer, and a polarization layer. The channel layer is disposed on the substrate, the spacer layer is disposed on the channel layer, and the polarization layer is disposed on the spacer layer.

[0007] Based on the foregoing, this application provides a method for manufacturing a nitride semiconductor device, comprising: sequentially forming a channel layer, a first spacer layer, a first polarization layer, a polarization control layer, a second spacer layer, a second polarization layer, and a cap layer on a substrate; partially etching the channel layer, the first spacer layer, the first polarization layer, the polarization control layer, the second spacer layer, the second polarization layer, and the cap layer to form a platform structure, wherein the platform structure exposes the channel layer; respectively forming a first passivation layer, a drain, and a source on the platform structure and on both sides of the platform structure, wherein the drain and the source are located on the first passivation layer and extend from the first passivation layer to the channel layer; forming a second passivation layer on the first passivation layer and partially etching the second passivation layer to make the second passivation layer have an opening, wherein the opening extends to the second spacer layer; forming a gate insulating layer on the second passivation layer and in the opening; and forming a gate on the gate insulating layer.

[0008] Based on the foregoing, this application provides a method for manufacturing a nitride semiconductor device, comprising: sequentially forming a channel layer, a spacer layer, and a polarization layer on a substrate; partially etching the channel layer, spacer layer, and polarization layer to form a platform structure, wherein the platform structure exposes the channel layer; forming a first passivation layer, a drain, and a source on the platform structure and on both sides of the platform structure, wherein the drain and source are located on the first passivation layer and extend from the first passivation layer to the channel layer; forming a second passivation layer on the first passivation layer and partially etching the second passivation layer to give the second passivation layer an opening, wherein the opening extends to the spacer layer; forming a gate insulating layer on the second passivation layer and in the opening; and forming a gate on the gate insulating layer.

[0009] In summary, the nitride semiconductor device and its manufacturing method of this application achieve normally-off operation of GaN HEMT by forming a first polarization layer, a polarization control layer and a second polarization layer, and adjusting the two-dimensional electron gas of the channel layer.

[0010] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, the following describes the application in detail with reference to the preferred embodiments of the present invention and in conjunction with the accompanying drawings. Simple Explanation of the Diagram

[0011] Figure 1 is a cross-sectional view of a nitride semiconductor device according to an embodiment of this application. Figure 2 is a schematic diagram illustrating the spontaneous polarization and piezoelectric polarization of the channel layer, the first polarization layer, and the polarization control layer according to an embodiment of this application. Figure 3 is a cross-sectional view of a nitride semiconductor device according to another embodiment of this application. Figure 4 is a cross-sectional view of a nitride semiconductor device according to another embodiment of the present application. Figure 5 is a cross-sectional view of a nitride semiconductor device according to another embodiment of this application. Figure 6 is a cross-sectional view of a nitride semiconductor device according to another embodiment of this application. Figure 7 is a cross-sectional view of a nitride semiconductor device according to another embodiment of this application. Figure 8 is a cross-sectional view of a nitride semiconductor device according to another embodiment of this application. Figure 9 is a flowchart illustrating a method for manufacturing a nitride semiconductor device according to an embodiment of this application. Figures 10A to 10F are cross-sectional views illustrating various stages of a method for manufacturing a nitride semiconductor device according to an embodiment of this application. Figure 11 is a flowchart illustrating a method for manufacturing a nitride semiconductor device according to another embodiment of this application. Figures 12A and 12B are schematic diagrams illustrating the formation of dielectric layers and metal plugs in a method for manufacturing a nitride semiconductor device according to another embodiment of this application. Figure 13 is a flowchart illustrating a method for manufacturing a nitride semiconductor device according to another embodiment of this application. Figure 14 is a cross-sectional view illustrating the formation of an oxide layer in a method for manufacturing a nitride semiconductor device according to another embodiment of this application. Figure 15 is a flowchart illustrating a method for manufacturing a nitride semiconductor device according to another embodiment of this application. Figures 16A to 16F are cross-sectional views illustrating various stages of a method for manufacturing a nitride semiconductor device according to yet another embodiment of this application. Figure 17 is a flowchart illustrating a method for manufacturing a nitride semiconductor device according to another embodiment of this application. Implementation

[0012] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.

[0013] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present application will now be described in detail with reference to the accompanying drawings and embodiments. To enable those skilled in the art to better understand the solutions of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without making innovative efforts should fall within the scope of protection of this application.

[0014] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0015] Please refer to Figure 1, which is a cross-sectional view of a nitride semiconductor device according to an embodiment of this application. As shown in Figure 1, the nitride semiconductor device 1A includes a substrate 10A, a channel layer 20A, a first polarization layer 30A, a polarization control layer 40A, and a second polarization layer 50A. The channel layer 20A is disposed on the substrate 10A, the first polarization layer 30A is disposed on the channel layer 20A, the polarization control layer 40A is disposed on the first polarization layer 30A, and the second polarization layer 50A is disposed on the polarization control layer 40A. In short, the channel layer 20A, the first polarization layer 30A, the polarization control layer 40A, and the second polarization layer 50A are sequentially disposed on the substrate 10A. The lattice constant of the first polarization layer 30A and the lattice constant of the second polarization layer 50A are smaller than the lattice constant of the polarization control layer 40A.

[0016] The substrate 10A can be a silicon (111) substrate, a gallium nitride (GaN) substrate, an aluminum nitride (AlN) substrate, a sapphire substrate, a silicon carbide substrate, or a diamond substrate. Given that the crystal structure of nitrides is typically wurtzite, a hexagonal crystal structure is chosen as the substrate 10A for the nitride semiconductor device. However, the substrate 10A for the nitride semiconductor device can also be other types of substrates capable of supporting nitride thin films, and is not limited to a hexagonal crystal structure.

[0017] The channel layer 20A is located between the substrate 10A and the first polarization layer 30A. The boundary between the channel layer 20A and the first polarization layer 30A is the location where a two-dimensional electron gas (2DEG) is formed. Additionally, a nucleation layer may be selectively disposed between the channel layer 20A and the substrate 10A to facilitate the formation of subsequent semiconductor layers.

[0018] The first polarization layer 30A is located between the channel layer 20A and the polarization control layer 40A. The lattice constant of the first polarization layer 30A is smaller than that of the channel layer 20A, and the band gap of the first polarization layer 30A is larger than that of the channel layer 20A. The interface between the first polarization layer 30A and the channel layer 20A is a heterojunction. Due to the different band gaps between the first polarization layer 30A and the channel layer 20A, the band structure at the interface between the channel layer 20A and the first polarization layer 30A is bent, thus forming a triangular quantum well structure. The triangular quantum well structure leads to the formation of a 2DEG at the interface between the channel layer 20A and the first polarization layer 30A.

[0019] The polarization control layer 40A is located between the first polarization layer 30A and the second polarization layer 50A. The band gap of the polarization control layer 40A is smaller than that of the first polarization layer 30A, and the lattice constant of the polarization control layer 40A is larger than that of the first polarization layer 30A.

[0020] The band gap of the second polarization layer 50A is larger than that of the polarization control layer 40A, and may be the same as or different from that of the first polarization layer 30A; the lattice constant of the second polarization layer 50A is smaller than that of the polarization control layer 40A, and may be the same as or different from that of the first polarization layer 30A. The polarization control layer 40A and the second polarization layer 50A together adjust the 2DEG at the boundary between the channel layer 20A and the first polarization layer 30A.

[0021] The materials of the channel layer 20A, the first polarization layer 30A, the polarization control layer 40A, and the second polarization layer 50A may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium aluminum nitride (InAlN), aluminum nitride (AlN), gallium scandium nitride (ScGaN), aluminum scandium nitride (ScAlN), boron nitride (BN), aluminum indium gallium nitride (AlInGaN), or indium gallium nitride (InGaN).

[0022] The following describes the operation mechanism of the 2DEG at the junction of the polarization control layer 40A and the second polarization layer 50A, which adjusts the interface between the channel layer 20A and the first polarization layer 30A. Please further refer to Figure 2, which is a schematic diagram illustrating the spontaneous polarization and piezoelectric polarization of the channel layer, the first polarization layer, and the polarization control layer according to an embodiment of this application. As shown in Figure 2, the first polarization layer 30A and the polarization control layer 40A are sequentially disposed on the channel layer 20A. For example, the material of the channel layer 20A is GaN; the material of the first polarization layer 30A is AlxGa1-xN, x=0.08~1; and the material of the polarization control layer 40A is AlyGa1-yN, y=0~0.6, x>y. In other words, the aluminum ratio of the first polarization layer 30A is greater than the aluminum ratio of the polarization control layer 40A. Furthermore, the thickness of the channel layer 20A is greater than the thickness of the first polarization layer 30A and the thickness of the polarization control layer 40A, and the thickness of the polarization control layer 40A is greater than the thickness of the first polarization layer 30A.

[0023] Here, we first explain the spontaneous polarization and piezoelectric polarization effects affecting 2DEG as follows. Because the crystal structure of group III nitrides is wurtzite-type and therefore non-centrosymmetric, and because gallium and nitrogen atoms are not symmetrically distributed, the centers of positive and negative charges cannot coincide, resulting in a spontaneous polarization effect in the lattice direction (0001). The piezoelectric effect is the phenomenon of the exchange of electrical and mechanical energy in piezoelectric materials. The piezoelectric polarization effect is the redistribution of charges within a crystal caused by stress due to the piezoelectric effect generated in the crystal.

[0024] The spontaneous polarization coefficient of gallium nitride (GaN) is -0.029 C / m². The spontaneous polarization coefficient of aluminum gallium nitride (GaN) is (-0.052x - 0.029) C / m², where x is the aluminum content in GaN. Both the spontaneous polarization coefficients of GaN and ANU are negative. The piezoelectric polarization coefficient of GaN is 2. , and piezoelectric coefficient, and The elastic modulus, The lattice constant of aluminum gallium nitride under no stress is given. is the lattice constant of aluminum gallium nitride under stress. It is negative; when aluminum gallium nitride is subjected to tensile stress, 2 It is a positive value; when aluminum gallium nitride is subjected to compressive stress, 2 It is a negative value.

[0025] The spontaneous polarization coefficient of channel layer 20A is denoted as Psp1; the spontaneous polarization coefficient of the first polarization layer 30A is denoted as Psp2, and the piezoelectric polarization coefficient of the first polarization layer 30A is denoted as Ppe2; the spontaneous polarization coefficient of polarization control layer 40A is denoted as Psp3, and the piezoelectric polarization coefficient of polarization control layer 40A is denoted as Ppe3. Since the spontaneous polarization coefficients of gallium nitride and aluminum gallium nitride are both negative, the spontaneous polarization direction of channel layer 20A, first polarization layer 30A, and polarization control layer 40A is all downward.

[0026] Because the lattice constant of the first polarization layer 30A is smaller than that of the channel layer 20A, the first polarization layer 30A is subjected to tensile stress, and the piezoelectric polarization coefficient Ppe2 of the first polarization layer 30A is negative, with the piezoelectric polarization direction of the first polarization layer 30A pointing downwards. Through the spontaneous polarization effect of the channel layer 20A, as well as the spontaneous polarization effect and piezoelectric polarization effect of the first polarization layer 30A, positive polarization charge accumulates at the interface between the channel layer 20A and the first polarization layer 30A, and the positive polarization charge attracts 2DEG.

[0027] Because the lattice constant of the polarization control layer 40A is greater than that of the first polarization layer 30A, the polarization control layer 40A is subjected to compressive stress, and the piezoelectric polarization coefficient Ppe3 of the polarization control layer 40A is positive, with the piezoelectric polarization direction of the polarization control layer 40A pointing upwards. Through the spontaneous polarization effect and piezoelectric polarization effect of the polarization control layer 40A and the spontaneous polarization effect of the first polarization layer 30A, negative polarization charge accumulates at the interface between the polarization control layer 40A and the first polarization layer 30A. The negative polarization charge attracts holes in the first polarization layer 30A, thereby affecting the positive polarization charge located at the interface between the channel layer 20A and the first polarization layer 30A, thus controlling the generation of 2DEG at the interface between the channel layer 20A and the first polarization layer 30A.

[0028] For example, the material of the second polarization layer 50A is AlzGa1-zN, z=0.08~1, z>y. The aluminum ratio of the second polarization layer 50A is greater than that of the polarization control layer 40A, and is different from that of the first polarization layer 30A.

[0029] Because the lattice constant of the second polarization layer 50A is smaller than that of the polarization control layer 40A, the second polarization layer 50A is subjected to tensile stress, and its piezoelectric polarization coefficient is negative, with the piezoelectric polarization direction pointing downwards. Through the spontaneous polarization effect and piezoelectric polarization effect of the second polarization layer 50A and the spontaneous polarization effect of the polarization control layer 40A, positive polarization charge accumulates at the interface between the second polarization layer 50A and the polarization control layer 40A. This positive polarization charge attracts 2DEG, which in turn affects the negative polarization charge at the interface between the polarization control layer 40A and the first polarization layer 30A, thereby controlling the generation of 2DEG at the interface between the channel layer 20A and the first polarization layer 30A.

[0030] In the nitride semiconductor device of this embodiment, the generation of positive polarization charge is controlled by the configuration of the polarization control layer and the second polarization layer, which affects the accumulation of positive polarization charge at the junction of the channel layer and the first polarization layer.

[0031] Please refer to Figure 3, which is a cross-sectional view of a nitride semiconductor device according to another embodiment of this application. As shown in Figure 3, the nitride semiconductor device 1B includes a substrate 10A, a channel layer 20A, a first polarization layer 30A, a polarization control layer 40A, a second polarization layer 50A, a first buffer layer 60A, a second buffer layer 70A, a back barrier layer 80A, a first spacer layer 90A, a second spacer layer 100A, and a cap layer 110A. The configuration of the nitride semiconductor device 1B shown in Figure 3 is similar to that of the nitride semiconductor device 1A shown in Figure 1, and the similarities between the nitride semiconductor device 1B shown in Figure 3 and the nitride semiconductor device 1A shown in Figure 1 will not be described again here.

[0032] A first buffer layer 60A is disposed on the substrate 10A and located between the substrate 10A and the channel layer 20A. The first buffer layer 60A provides a relatively flat crystalline surface to facilitate the formation of subsequent semiconductor thin films and to mitigate lattice mismatch between the substrate 10A and the first buffer layer 60A. The first buffer layer 60A can be an AlN / GaN super lattice, a GaN buffer layer with a graded structure, or a GaN buffer layer with an abrupt structure. A second buffer layer 70A is disposed on the first buffer layer 60A and located between the first buffer layer 60A and the channel layer 20A. The second buffer layer 70A reduces the leakage current between the semiconductor layer on the second buffer layer 70A and the substrate 10A and increases the breakdown voltage of the nitride semiconductor device. The material of the second buffer layer 70A can include carbon-doped GaN or iron-doped GaN.

[0033] A back barrier layer 80A is disposed on the second buffer layer 70A and located between the second buffer layer 70A and the channel layer 20A. The back barrier layer 80A mitigates defects caused by lattice mismatch between the second buffer layer 70A and the channel layer 20A, and reduces leakage current in the nitride semiconductor device. The material of the back barrier layer 80A may include AlN, AlGaN, or InGaN.

[0034] In this embodiment, the nitride semiconductor device has a first buffer layer 60A, a second buffer layer 70A, and a back barrier layer 80A. In another embodiment, the nitride semiconductor device has a first buffer layer 60A and a back barrier layer 80A, or a second buffer layer 70A and a back barrier layer 80A. In yet another embodiment, the nitride semiconductor device has a first buffer layer 60A, a second buffer layer 70A, or a back barrier layer 80A.

[0035] A first spacer layer 90A is disposed between the first polarization layer 30A and the channel layer 20A to assist in inducing a 2DEG at the boundary between the channel layer 20A and the first polarization layer 30A. The first spacer layer 90A is a thin layer; the thickness of the first spacer layer 90A is less than the thickness of the first polarization layer 30A and the channel layer 20A. A second spacer layer 100A is disposed between the polarization control layer 40A and the second polarization layer 50A to assist in inducing a 2DEG at the boundary between the polarization control layer 40A and the second polarization layer 50A. The second spacer layer 100A is a thin layer; the thickness of the second spacer layer 100A is less than the thickness of the polarization control layer 40A and the second polarization layer 50A. Although the nitride semiconductor device 1B has two spacer layers in this embodiment, the number of spacer layers in the nitride semiconductor device 1B can be adjusted according to performance requirements. The number of spacer layers is not limited to two layers but can be one layer, for example, only one spacer layer can be disposed between the first polarization layer 30A and the channel layer 20A. The materials of the first spacer layer 90A and the second spacer layer 100A can be, for example, AlN or AlGaN with high aluminum content.

[0036] A cap layer 110A is disposed on the second polarization layer 50A. The purpose of the cap layer 110A is to protect the epitaxial material from damage during the fabrication process and to provide good interface quality between it and the first passivation layer. The material of the cap layer 110A may include AlN or GaN. The cap layer 110A is a thin layer; its thickness is less than that of the second polarization layer 50A.

[0037] In the nitride semiconductor device of this embodiment, the leakage current of the nitride semiconductor device is reduced by the configuration of the buffer layer and the back barrier layer, and the 2DEG is induced by the configuration of the spacer layer.

[0038] Please refer to Figure 4, which is a cross-sectional view of a nitride semiconductor device according to another embodiment of this application. As shown in Figure 4, the nitride semiconductor device 1C includes a substrate 10A, a channel layer 20A, a first polarization layer 30A, a polarization control layer 40A, a second polarization layer 50A, a first buffer layer 60A, a second buffer layer 70A, a back barrier layer 80A, a first spacer layer 90A, a second spacer layer 100A, a cap layer 110A, a first passivation layer 120A, a drain 130A, a source 140A, a second passivation layer 150A, a gate insulating layer 160A, a gate 170A, an interlayer dielectric layer 180A, a plurality of first metal plugs M1A, an interlayer dielectric layer 190A, a plurality of second metal plugs M2A, and a third passivation layer 200A. The nitride semiconductor device 1C shown in Figure 4 and the nitride semiconductor device 1B shown in Figure 3 have similar configurations, and the similarities between the nitride semiconductor device 1C shown in Figure 4 and the nitride semiconductor device 1B shown in Figure 3 will not be described again here.

[0039] It should be noted that after the cap layer 110A is formed, the first spacer layer 90A, the first polarization layer 30A, the polarization control layer 40A, the second spacer layer 100A, the second polarization layer 50A, and the cap layer 110A are etched to form a platform structure. The formation of the platform structure will be explained in the corresponding paragraph of the manufacturing method of the nitride semiconductor device.

[0040] A first passivation layer 120A is disposed on the platform structure. Specifically, the first passivation layer 120A covers the cap layer 110A on the platform structure and contacts the drain 130A and the source 140A. In other words, the cap layer 110A is located between the second polarization layer 50A and the first passivation layer 120A. A second passivation layer 150A is disposed on the first passivation layer 120A and is located on the drain 130A and the source 140A. Specifically, the second passivation layer 150A covers the first passivation layer 120A and contacts the drain 130A and the source 140A. In other words, the first passivation layer 120A is located between the second passivation layer 150A and the cap layer 110A. The configuration of the first passivation layer 120A and the second passivation layer 150A prevents contamination of the cap layer 110A and the second polarization layer 50A, thereby reducing the leakage current of the nitride semiconductor device and electrically insulating the drain 130A and the source 140A from each other. Although the nitride semiconductor device 1C has two passivation layers in this embodiment, the number of passivation layers can be adjusted according to performance requirements. The number of passivation layers is not limited to two layers but can be one or three layers. The materials of the first passivation layer 120A and the second passivation layer 150A may include silicon nitride (SiNx), silicon oxynitride (SiON), silicon carbonitride (SiCN), aluminum nitride (AlN), silicon dioxide (SiO2), aluminum oxynitride (AlON), or combinations thereof.

[0041] The drain electrode 130A and the source electrode 140A are disposed on opposite sides of the platform structure. For example, the drain electrode 130A is disposed on the right side of the platform structure, and the source electrode 140A is disposed on the left side of the platform structure. It should be noted that the positions of the drain electrode 130A and the source electrode 140A are interchangeable, that is, the drain electrode 130A is disposed on the left side of the platform structure, and the source electrode 140A is disposed on the right side of the platform structure. Both the drain electrode 130A and the source electrode 140A are located on the first passivation layer 120A and extend from the first passivation layer 120A to the channel layer 20A. Specifically, the drain electrode 130A and the source electrode 140A protrude relative to the upper surface of the first passivation layer 120A, extend through the first passivation layer 120A toward the substrate 10A, and stop at the channel layer 20A to connect with the channel layer 20A.

[0042] The detailed configuration of the drain 130A and source 140A will be further described below. The drain 130A includes a first extension 131A and a first electrode portion 132A. The first extension 131A is located on the right side of the platform structure and extends from the first passivation layer 120A to the channel layer 20A. Further, the first extension 131A extends from the lower surface of the first passivation layer 120A to the substrate 10A and terminates at the channel layer 20A to contact it. The first electrode portion 132A is disposed on the first extension 131A and penetrates the first passivation layer 120A from a position higher than the upper surface of the first passivation layer 120A to connect to the first extension 131A; the second passivation layer 150A contacts the sidewall of the first electrode portion 132A. The source 140A includes a second extension 141A and a second electrode portion 142A. The second extension 141A is located on the left side of the platform structure and extends from the first passivation layer 120A to the channel layer 20A. Further, the second extension 141A extends from the lower surface on the left side of the first passivation layer 120A toward the substrate 10A and terminates at the channel layer 20A to contact it. A second electrode portion 142A is disposed on the second extension 141A and penetrates the first passivation layer 120A from a position higher than the upper surface of the first passivation layer 120A to connect to the second extension 141A; the second passivation layer 150A contacts the sidewall of the second electrode portion 142A.

[0043] In one embodiment, the materials of the first extension 131A and the second extension 141A include n-type gallium nitride and n-type gallium indium nitride. In another embodiment, the materials of the first extension 131A and the second extension 141A are metallic materials, which may include indium (In), tin (Sn), aluminum (Al), gold (Au), platinum (Pt), indium (In), zinc (Zn), germanium (Ge), silver (Ag), lead (Pb), palladium (Pd), copper (Cu), gold beryllium bromide (AuBe), germanium beryllium bromide (BeGe), nickel (Ni), lead tin bromide (PbSn), chromium (Cr), gold zinc bromide (AuZn), titanium (Ti), tungsten (W), titanium tungsten bromide (TiW), titanium nitride (TiN), or combinations thereof. The materials of the first electrode portion 132A and the second extension 141A are both metallic materials.

[0044] In this embodiment, the second passivation layer 150A has an opening. The opening is located between the first extension 131A and the second extension 141A and extends to the second spacer layer 100A. Specifically, the opening extends from the upper surface of the second passivation layer 150A toward the substrate 10A and stops at the second spacer layer 100A.

[0045] A gate insulating layer 160A is disposed on a second passivation layer 150A, and a portion of the gate insulating layer 160A is disposed in an opening. Specifically, the gate insulating layer 160A includes a first portion and a second portion, the first portion covering the second passivation layer 150A, and the second portion covering the sidewalls and bottom of the opening. The material of the gate insulating layer 160A includes silicon oxide (SiOx), silicon carbide (SiOC), aluminum oxide (AlOx), hafnium dioxide (HfO2), yttrium oxide (Y2O3), yttrium titanium pentoxide (Y2TiO5), ytterbium oxide (Yb2O3), zirconium dioxide (ZrO2), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), or combinations thereof.

[0046] Gate 170A is disposed in the opening and is insulated from the second spacer layer 100A through gate insulating layer 160A. Specifically, gate 170A fills the opening and contacts the gate insulating layer 160A located on the sidewalls and bottom of the opening; part of gate 170A is not in the opening but is located on the gate insulating layer 160A. The gate insulating layer 160A located on the second passivation layer 150A partially contacts gate 170A, while the top and part of the sidewalls of gate 170A do not contact the gate insulating layer 160A. In other words, gate insulating layer 160A is located between gate 170A and the second spacer layer 100A, and also between gate 170A and the second passivation layer 150A; gate 170A is separated from the second polarization layer 50A, the second spacer layer 100A, and the cap layer 110A through gate insulating layer 160A. The material of gate 170A is metallic.

[0047] By configuring the gate insulating layer 160A, the gate 170A, the second polarization layer 50A, the second spacer layer 100A, and the cap layer 110A, a metal-insulator-semiconductor (MIS) structure is formed to reduce the leakage current of the gate 170A.

[0048] An interlayer dielectric layer 180A is disposed on the gate 170A and located on the gate insulating layer 160A. Specifically, the interlayer dielectric layer 180A covers the gate 170A and part of the gate insulating layer 160A, and exposes the gate 170A, drain 130A, and source 140A; the gate insulating layer 160A is located between the interlayer dielectric layer 180A and the second passivation layer 150A. Further, the interlayer dielectric layer 180A covers the top of the gate 170A and exposes part of the top of the drain 130A and the top of the source 140A. The material of the interlayer dielectric layer 180A is the same as that of the gate insulating layer 160A, and will not be described again.

[0049] A plurality of first metal plugs M1A are disposed on the interlayer dielectric layer 180A and penetrate the interlayer dielectric layer 180A, the gate insulating layer 160A, and the second passivation layer 150A to connect the drain 130A and the source 140A. It should be noted that the first metal plugs M1A connecting the source 140A are located on the side of the interlayer dielectric layer 180A closer to the source 140A and extend towards the gate 170A to form a source gate field. The source gate field shields the gate 170A; that is, the projection of the source gate field onto the substrate 10A overlaps with the projection of the gate 170A onto the substrate 10A, but the source gate field does not contact the first metal plugs M1A connecting the drain 130A. An interlayer dielectric layer 180A is provided between two adjacent first metal plugs M1A; through the interlayer dielectric layer 180A, adjacent first metal plugs M1A are electrically isolated from each other. For example, the number of the plurality of first metal plugs M1A is two. The two first metal plugs M1A are respectively connected to the drain 130A and the source 140A. The first metal plug M1A connected to the drain 130A and the first metal plug M1A connected to the source 140A are electrically insulated from the gate 170A through the interlayer dielectric layer 180A.

[0050] It should be noted that although the number of multiple first metal plugs M1A shown in Figure 4 is two, the number of multiple first metal plugs M1A can be adjusted according to performance requirements and is not limited to two. The material of the multiple first metal plugs M1A is a metallic material.

[0051] An inter-metal dielectric layer 190A is disposed on the inter-metal dielectric layer 180A. Specifically, the inter-metal dielectric layer 190A covers the inter-metal dielectric layer 180A and partially covers the tops of the plurality of first metal plugs M1A, while partially exposing the tops of the plurality of first metal plugs M1A. An inter-metal dielectric layer 190A is present between two adjacent first metal plugs M1A. In other words, the inter-metal dielectric layer 190A contacts the plurality of first metal plugs M1A, and the plurality of first metal plugs M1A are electrically insulated from each other through the inter-metal dielectric layer 190A. The material of the inter-metal dielectric layer 190A is the same as the material of the gate insulating layer 160A, and will not be described again.

[0052] A plurality of second metal plugs M2A are disposed on and penetrate the inter-metal dielectric layer 190A to connect to a plurality of first metal plugs M1A. An inter-metal dielectric layer 190A is provided between two adjacent second metal plugs M2A; through the inter-metal dielectric layer 190A, adjacent second metal plugs M2A are electrically isolated from each other. Furthermore, the plurality of second metal plugs M2A contact the inter-metal dielectric layer 190A and are electrically insulated from each other through the inter-metal dielectric layer 190A. The number of the plurality of second metal plugs M2A is equal to the number of the plurality of first metal plugs M1A.

[0053] It should be noted that although the number of multiple second metal plugs M2A shown in Figure 4 is two, the number of multiple second metal plugs M2A can be adjusted according to performance requirements and is not limited to two. The material of the multiple second metal plugs M2A is a metallic material.

[0054] A third passivation layer 200A is disposed on the inter-metal dielectric layer 190A and exposes a plurality of second metal plugs M2A. Specifically, the third passivation layer 200A covers the inter-metal dielectric layer 190A and partially covers the tops of the plurality of second metal plugs M2A, while partially exposing the tops of the plurality of second metal plugs M2A. A third passivation layer 200A is present between two adjacent second metal plugs M2A. In other words, the third passivation layer 200A contacts the plurality of second metal plugs M2A, and the plurality of second metal plugs M2A are electrically insulated from each other through the third passivation layer 200A. The material of the third passivation layer 200A is the same as that of the first passivation layer 120A, and will not be described again; however, the material selection of the third passivation layer 200A may differ from that of the first passivation layer 120A. For example, the material of the first passivation layer 120A may be aluminum nitride (AlN), and the material of the third passivation layer 200A may be silicon dioxide (SiO2).

[0055] In the nitride semiconductor device of this embodiment, the leakage current of the nitride semiconductor device is reduced through the passivation layer, and the critical voltage of the nitride semiconductor device is adjusted through the configuration of the gate, drain, source and dielectric layer with MIS structure, thereby improving the performance of the nitride semiconductor device.

[0056] Please refer to Figure 5, which is a cross-sectional view of a nitride semiconductor device according to another embodiment of this application. As shown in Figure 5, the nitride semiconductor device 1D includes a substrate 10A, a channel layer 20A, a first polarization layer 30A, a polarization control layer 40A, a second polarization layer 50A, a first buffer layer 60A, a second buffer layer 70A, a back barrier layer 80A, a first spacer layer 90A, a second spacer layer 100A, a cap layer 110A, a first passivation layer 120A, a drain 130A, a source 140A, a second passivation layer 150A, a gate insulating layer 160A, a gate 170A, an interlayer dielectric layer 180A, a plurality of first metal plugs M1A, a metal interlayer dielectric layer 190A, a plurality of second metal plugs M2A, a third passivation layer 200A, and an oxide layer 210A. The nitride semiconductor device 1D shown in Figure 5 and the nitride semiconductor device 1C shown in Figure 4 have similar configurations, and the similarities between the nitride semiconductor device 1D shown in Figure 5 and the nitride semiconductor device 1C shown in Figure 4 will not be described again here.

[0057] The oxide layer 210A is located at the bottom of the opening in the second passivation layer 150A, and the gate insulating layer 160A is located on the oxide layer 210A. Specifically, the oxide layer 210A is formed after the opening in the second passivation layer 150A is formed, and the formation time of the oxide layer 210A is earlier than the formation time of the gate insulating layer 160A; the oxide layer 210A contacts the second spacer layer 100A. The material of the oxide layer 210A is the same as that of the gate insulating layer 160A, and will not be described again; however, the material selection of the oxide layer 210A can be different from that of the gate insulating layer 160A. For example, the material of the gate insulating layer 160A is silicon oxide (SiOx), and the material of the oxide layer 210A is aluminum oxynitride (AlON).

[0058] Please refer to Figure 6, which is a cross-sectional view of a nitride semiconductor device according to another embodiment of this application. As shown in Figure 6, the nitride semiconductor device 2A includes a substrate 10B, a channel layer 20B, a spacer layer 30B, and a polarization layer 40B. The arrangement of the substrate 10B and the channel layer 20B is similar to that shown in Figure 1, and will not be repeated here.

[0059] Spacer layer 30B is disposed on channel layer 20B, and polarization layer 40B is disposed on spacer layer 30B; in other words, spacer layer 30B is located between polarization layer 40B and channel layer 20B. Spacer layer 30B is a thin layer; the thickness of spacer layer 30B is less than the thickness of channel layer 20B and polarization layer 40B.

[0060] The lattice constant of polarization layer 40B is smaller than that of channel layer 20B, and the band gap of polarization layer 40B is larger than that of channel layer 20B. Due to the different band gaps of polarization layer 40B and channel layer 20B, the energy band at the interface between them is bent, forming a triangular quantum well structure. This triangular quantum well structure leads to the generation of a 2DEG at the interface between spacer layer 30B and channel layer 20B.

[0061] The polarization layer 40B may be made of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium aluminum nitride (InAlN), aluminum nitride (AlN), gallium scandium nitride (ScGaN), aluminum scandium nitride (ScAlN), boron nitride (BN), aluminum indium gallium nitride (AlInGaN), or indium gallium nitride (InGaN). The spacer layer 30B may be made of AlN or AlGaN with high aluminum content.

[0062] In the nitride semiconductor device of this embodiment, only one polarization layer 40B and channel layer 20B generate 2DEG, while there is no polarization control layer, further reducing the size of the nitride semiconductor device.

[0063] In this embodiment, the nitride semiconductor device 2A further includes a first buffer layer 50B, a second buffer layer 60B, and a back barrier layer 70B. The configuration of the first buffer layer 50B, the second buffer layer 60B, and the back barrier layer 70B is the same as that of the first buffer layer 60A, the second buffer layer 70A, and the back barrier layer 80A shown in FIG3, and will not be described again.

[0064] The nitride semiconductor device 2B shown in Figure 7 is based on the nitride semiconductor device 2A shown in Figure 6, but with the addition of a first passivation layer 80B, a drain 90B, a source 100B, a second passivation layer 110B, a gate insulating layer 120B, a gate 130B, an interlayer dielectric layer 140B, a plurality of first metal plugs M1B, an interlayer dielectric layer 150B, a plurality of second metal plugs M2B, and a third passivation layer 160B. The configuration of the first passivation layer 80B, drain 90B, source 100B, second passivation layer 110B, gate insulating layer 120B, gate 130B, interlayer dielectric layer 140B, a plurality of first metal plugs M1B, interlayer dielectric layer 150B, a plurality of second metal plugs M2B, and third passivation layer 160B is similar to that shown in Figure 4, and will not be described again.

[0065] The nitride semiconductor device 2C shown in Figure 8 is based on the nitride semiconductor device 2A shown in Figure 6, but with the addition of a first passivation layer 80B, a drain 90B, a source 100B, a second passivation layer 110B, a gate insulating layer 120B, a gate 130B, an interlayer dielectric layer 140B, a plurality of first metal plugs M1B, an interlayer dielectric layer 150B, a plurality of second metal plugs M2B, a third passivation layer 160B, and an oxide layer 170B. The configuration of the first passivation layer 80B, drain 90B, source 100B, second passivation layer 110B, gate insulating layer 120B, gate 130B, interlayer dielectric layer 140B, a plurality of first metal plugs M1B, interlayer dielectric layer 150B, a plurality of second metal plugs M2B, third passivation layer 160B, and oxide layer 170B is similar to that shown in Figure 5 for the configuration of the first passivation layer 120A, drain 130A, source 140A, second passivation layer 150A, gate insulating layer 160A, gate 170A, interlayer dielectric layer 180A, a plurality of first metal plugs M1A, interlayer dielectric layer 190A, a plurality of second metal plugs M2A, third passivation layer 200A, and oxide layer 210A, and will not be described again.

[0066] Please refer to Figure 9, which is a flowchart illustrating a method for manufacturing a nitride semiconductor device according to an embodiment of this application. As shown in Figure 9, the method for manufacturing a nitride semiconductor device includes steps S1A to S7A.

[0067] Step S1A: Sequentially form a first buffer layer 60A, a second buffer layer 70A, and a back barrier layer 80A on the substrate 10A. The method for forming the first buffer layer 60A, the second buffer layer 70A, and the back barrier layer 80A may be chemical vapor deposition (CVD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), or sputtering.

[0068] Step S2A: The channel layer 20A, the first spacer layer 90A, the first polarization layer 30A, the polarization control layer 40A, the second spacer layer 100A, the second polarization layer 50A, and the cap layer 110A are sequentially formed on the back barrier layer 80A. The method for forming the channel layer 20A, the first spacer layer 90A, the first polarization layer 30A, the polarization control layer 40A, the second spacer layer 100A, the second polarization layer 50A, and the cap layer 110A can be the same as the method for forming the first buffer layer 60A, the second buffer layer 70A, and the back barrier layer 80A.

[0069] Step S3A: Partially etch the channel layer 20A, the first spacer layer 90A, the first polarization layer 30A, the polarization control layer 40A, the second spacer layer 100A, the second polarization layer 50A, and the cap layer 110A to form the platform structure MS1. Specifically, a first patterned photoresist layer is first formed on the cap layer 110A. Based on the first patterned photoresist layer, the channel layer 20A, the first spacer layer 90A, the first polarization layer 30A, the polarization control layer 40A, the second spacer layer 100A, the second polarization layer 50A, and the cap layer 110A are partially etched through inductively coupled plasma-reactive ion etching (ICP-RIE) or wet etching to expose the channel layer 20A, thereby forming the platform structure MS1 as shown in FIG10A and removing the first patterned photoresist layer.

[0070] Step S4A: A first passivation layer 120A, a drain electrode 130A, and a source electrode 140A are formed on the platform structure MS1 and on both sides of the platform structure MS1, respectively. The drain electrode 130A includes a first extension portion 131A and a first electrode portion 132A, and the source electrode 140A includes a second extension portion 141A and a second electrode portion 142A.

[0071] Specifically, a first extension 131A and a second extension 141A are first formed on both sides of the platform structure MS1. Next, a first passivation layer 120A is formed on the platform structure MS1, and the first passivation layer 120A is partially etched to expose the first extension 131A and the second extension 141A, thereby defining the drain region and the source region. Finally, a first electrode portion 132A and a second electrode portion 142A are formed in the drain region and the source region.

[0072] In one embodiment, the materials of the first extension 131A and the second extension 141A include n-type gallium nitride or n-type gallium indium nitride, and the method for forming the first extension 131A and the second extension 141A is the same as the method for forming the first buffer layer 60A, the second buffer layer 70A, and the back barrier layer 80A. Step S4A will be described in detail below using CVD and the materials of the first extension 131A and the second extension 141A being n-type gallium nitride as an example.

[0073] An n-type gallium nitride (GaN) thin film is formed on a platform structure MS1 using CVD. The GaN thin film covers the top of the platform structure MS1 and the sidewalls on both sides of the platform structure MS1. The GaN thin film is then partially etched, leaving the GaN thin film as the first extension 131A and the second extension 141A as shown in FIG. 10B. Next, a first passivation layer 120A is formed as shown in FIG. 10C. The first passivation layer 120A covers the first extension 131A, the second extension 141A, and the top of the platform structure MS1. The method for forming the first passivation layer 120A is the same as the method for forming the first buffer layer 60A, the second buffer layer 70A, and the back barrier layer 80A. Then, a second patterned photoresist layer is formed on the first passivation layer 120A. Based on the second patterned photoresist layer, the first passivation layer 120A is partially etched to expose the top of the first extension 131A and the top of the second extension 141A, thereby defining the drain region and the source region. Finally, a first electrode portion 132A and a second electrode portion 142A, as shown in FIG10D, are formed in the drain region and the source region, and the second patterned photoresist layer is removed; wherein, the method for forming the first electrode portion 132A and the second electrode portion 142A can be CVD, sputtering, or evaporation. The first extension portion 131A and the first electrode portion 132A constitute the drain 130A, and the second extension portion 141A and the second electrode portion 142A constitute the source 140A.

[0074] In another embodiment, the materials of the first extension 131A and the second extension 141A include metallic materials, and the method of forming the first extension 131A and the second extension 141A is the same as the method of forming the first electrode portion 132A and the second electrode portion 142A.

[0075] First, a first metal layer is formed on the platform structure MS1, covering the top of the platform structure MS1 and the sidewalls on both sides of the platform structure MS1. An auxiliary layer with openings is formed on the first metal layer, and the first metal layer is partially etched, leaving the first metal layer as the first extension 131A and the second extension 141A as shown in FIG10B. Next, a first passivation layer 120A is formed as shown in FIG10C, covering the first extension 131A, the second extension 141A, and the top of the platform structure MS1. Then, an auxiliary layer with two openings is formed on the first passivation layer 120A. Using the auxiliary layer as a reference, the first passivation layer 120A is partially etched to expose the tops of the first extension 131A and the second extension 141A, thereby defining the drain region and the source region. The auxiliary layer may be made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonate (SiOC), aluminum oxide (AlOx), hafnium dioxide (HfO2), or combinations thereof. Finally, a first electrode portion 132A and a second electrode portion 142A, as shown in FIG. 10D, are formed in the drain region and the source region, and the auxiliary layer is removed. The first extension 131A and the first electrode portion 132A constitute the drain 130A, and the second extension 141A and the second electrode portion 142A constitute the source 140A.

[0076] In another embodiment, a first passivation layer 120A is first formed on the platform structure MS1 and the channel layer 20A, and the first passivation layer 120A on the channel layer 20A is etched. Next, a first metal layer is formed on the first passivation layer 120A and the channel layer 20A by sputtering or vapor deposition, and the first metal layer is subjected to high-temperature thermal annealing. After thermal annealing, the first metal layer moves from the surface of the first passivation layer 120A to both sides of the platform structure MS1 to contact the channel layer 20A.

[0077] Step S5A: A second passivation layer 150A is formed on the first passivation layer 120A, and the second passivation layer 150A is partially etched to give the second passivation layer 150A an opening OA1. Specifically, the second passivation layer 150A is formed on the first passivation layer 120A, and the second passivation layer 150A covers the first electrode portion 132A and the second electrode portion 142A; the method of forming the second passivation layer 150A is the same as the method of forming the first buffer layer 60A, the second buffer layer 70A, and the back barrier layer 80A. Next, a third patterned photoresist layer is formed on the second passivation layer 150A, and based on the third patterned photoresist layer, the second passivation layer 150A, the first passivation layer 120A, the cap layer 110A, and the second polarization layer 50A are partially etched, and etching is stopped on the second spacer layer 100A to form the opening OA1 as shown in FIG10E. In other words, the second spacer layer 100A serves as an etch stop layer.

[0078] Step S6A: Form a gate insulating layer 160A on the second passivation layer 150A and in the opening OA1. As shown in FIG10F, the gate insulating layer 160A covers the upper surface of the second passivation layer 150A and the sidewalls and bottom of the opening OA1. The method for forming the gate insulating layer 160A is the same as the method for forming the first buffer layer 60A, the second buffer layer 70A, and the back barrier layer 80A.

[0079] Step S7A: Form a gate 170A on the gate insulating layer 160A. Specifically, a second metal layer is formed on the gate insulating layer 160A, the second metal layer fills the opening OA1, and covers the gate insulating layer 160A; wherein, the method of forming the second metal layer is the same as the method of forming the first electrode portion 132A and the second electrode portion 142A. Next, the second metal layer is partially etched to expose a portion of the upper surface of the gate insulating layer 160A, leaving the second metal layer as the gate 170A as shown in FIG10F.

[0080] Please refer to Figure 11, which is a flowchart illustrating a method for manufacturing a nitride semiconductor device according to an embodiment of this application. As shown in Figure 11, the method for manufacturing a nitride semiconductor device includes steps S1A to S14A; steps S1A to S7A shown in Figure 11 are the same as steps S1A to S7A shown in Figure 9, and will not be described again.

[0081] Step S8A: An interlayer dielectric layer 180A is formed on the gate 170A and the gate insulating layer 160A. The interlayer dielectric layer 180A covers the gate 170A and the gate insulating layer 160A. The method for forming the interlayer dielectric layer 180A is the same as the method for forming the first buffer layer 60A, the second buffer layer 70A, and the back barrier layer 80A.

[0082] Step S9A: Partially etch the interlayer dielectric layer 180A to expose the drain 130A and the source 140A. Specifically, a fourth patterned photoresist layer is formed on the interlayer dielectric layer 180A, and based on the fourth patterned photoresist layer, the interlayer dielectric layer 180A is partially etched to form two openings; wherein, after etching, there is a gap between the interlayer dielectric layer 180A and the gate insulating layer 160A, and the gap is close to the source 140A. As shown in Figure 12A, the two openings of the interlayer dielectric layer 180A expose the drain 130A and the source 140A.

[0083] Step S10A: Form a plurality of first metal plugs M1A to connect the gate 170A, drain 130A, and source 140A. As shown in FIG12A, two first metal plugs M1A are formed with a metal shield to connect the drain 130A and the source 140A; wherein, the first metal plug M1A connecting the source 140A extends from the source 140A towards the gate 170A. The method for forming the plurality of first metal plugs M1A is the same as the method for forming the first electrode portion 132A and the second electrode portion 142A.

[0084] Step S11A: Form an inter-metal dielectric layer 190A on the inter-layer dielectric layer 180A and the plurality of first metal plugs M1A. The inter-metal dielectric layer 190A covers the inter-layer dielectric layer 180A and the plurality of first metal plugs M1A. The method for forming the inter-metal dielectric layer 190A is the same as the method for forming the first buffer layer 60A, the second buffer layer 70A, and the back barrier layer 80A.

[0085] Step S12A: Partially etch the intermetallic dielectric layer 190A to expose a plurality of first metal plugs M1A. Specifically, a fourth patterned photoresist layer is formed on the intermetallic dielectric layer 190A, and based on the fourth patterned photoresist layer, the intermetallic dielectric layer 190A is partially etched to form two openings. As shown in Figure 12B, the two openings of the intermetallic dielectric layer 190A expose two first metal plugs M1A.

[0086] Step S13A: Form a plurality of second metal pins M2A to connect a plurality of first metal pins M1A. As shown in FIG12B, two second metal pins M2A are formed with a metal shield to connect two first metal pins M1A. The method for forming the plurality of second metal pins M2A is the same as the method for forming the first electrode portion 132A and the second electrode portion 142A.

[0087] Step S14A: A third passivation layer 200A is formed on the plurality of second metal plugs M2A and the inter-metal dielectric layer 190A, and the third passivation layer 200A is partially etched to expose the plurality of second metal plugs M2A. Specifically, a fourth patterned photoresist layer is formed on the third passivation layer 200A, and the third passivation layer 200A is partially etched based on the fourth patterned photoresist layer to form two openings. As shown in FIG12B, the two openings of the third passivation layer 200A expose two second metal plugs M2A. The method for forming the third passivation layer 200A is the same as the method for forming the first buffer layer 60A, the second buffer layer 70A, and the back barrier layer 80A.

[0088] Please refer to Figure 13, which is a flowchart illustrating a method for manufacturing a nitride semiconductor device according to another embodiment of this application. As shown in Figure 13, the method for manufacturing a nitride semiconductor device includes steps S111A to S125A; steps S111A to S115A and steps S117A to S125A shown in Figure 13 are the same as steps S1A to S14A shown in Figure 11, and will not be described again.

[0089] Step S116A: An oxide layer 210A is formed at the bottom of the opening OA1. As shown in Figure 14, the oxide layer 210A can eliminate surface defects of the second spacer layer 100A after etching. The method for forming the oxide layer 210A is the same as the method for forming the first buffer layer 60A, the second buffer layer 70A, and the back barrier layer 80A.

[0090] Please refer to Figure 15, which is a flowchart illustrating a method for manufacturing a nitride semiconductor device according to another embodiment of this application. As shown in Figure 15, the method for manufacturing a nitride semiconductor device includes steps S1B to S7B. Step S1B: A first buffer layer 50B, a second buffer layer 60B, and a back barrier layer 70B are sequentially formed on a substrate 10B. The method for forming the first buffer layer 50B, the second buffer layer 60B, and the back barrier layer 70B can be chemical vapor deposition (CVD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), or sputtering.

[0091] Step S2B: The channel layer 20B, the spacer layer 30B, and the polarization layer 40B are sequentially formed on the back barrier layer 70B. The method for forming the channel layer 20B, the spacer layer 30B, and the polarization layer 40B is the same as the method for forming the first buffer layer 50B, the second buffer layer 60B, and the back barrier layer 70B.

[0092] Step S3B: Partially etch the channel layer 20B, spacer layer 30B, and polarization layer 40B to form a platform structure MS2. Specifically, a first patterned photoresist layer is first formed on the polarization layer 40B. Based on the first patterned photoresist layer, the channel layer 20B, spacer layer 30B, and polarization layer 40B are partially etched by ICP-RIE or wet etching to expose the channel layer 20A, forming the platform structure MS2 as shown in FIG16A and removing the first patterned photoresist layer.

[0093] Step S4B: A first passivation layer 80B, a drain electrode 90B, and a source electrode 100B are formed on the platform structure MS2 and on both sides of the platform structure MS2, respectively. The drain electrode 90B includes a first extension 91B and a first electrode 92B, and the source electrode 100B includes a second extension 101B and a second electrode 102B.

[0094] As shown in Figure 16B, a first extension 91B and a second extension 101B are first formed on both sides of the platform structure MS1. Next, as shown in Figures 16C and 16D, a first passivation layer 80B is formed on the platform structure MS2, and the first passivation layer 80B is partially etched to expose the first extension 91B and the second extension 101B, thereby defining the drain region and the source region. Finally, a first electrode portion 92B and a second electrode portion 102B are formed in the drain region and the source region. The detailed steps of step S4B shown in Figure 15 are the same as those of step S4A shown in Figure 9, differing only in the reference numerals.

[0095] Step S5B: A second passivation layer 110B is formed on the first passivation layer 80B, and the second passivation layer 110B is partially etched to create an opening OA2 in the second passivation layer 110B. Specifically, the second passivation layer 110B is formed on the first passivation layer 80B, and the second passivation layer 110B covers the first electrode portion 92B and the second electrode portion 102B; the method for forming the second passivation layer 150A is the same as the method for forming the first buffer layer 50B, the second buffer layer 60B, and the back barrier layer 70B. Next, a third patterned photoresist layer is formed on the second passivation layer 110B, and based on the third patterned photoresist layer, the second passivation layer 110B, the first passivation layer 80B, and the spacer layer 30B are partially etched, and etching is stopped at the spacer layer 30B to form the opening OA2 as shown in FIG16E. In other words, the spacer layer 30B serves as an etching stop layer.

[0096] Step S6B: Form a gate insulating layer 120B on the second passivation layer 110B and in the opening OA2. As shown in FIG16F, the gate insulating layer 120B covers the upper surface of the second passivation layer 110B and the sidewalls and bottom of the opening OA2. The method for forming the gate insulating layer 120B is the same as the method for forming the first buffer layer 50B, the second buffer layer 60B, and the back barrier layer 70B.

[0097] Step S7B: Form a gate 130B on the gate insulating layer 120B. Specifically, a second metal layer is formed on the gate insulating layer 120B, the second metal layer fills the opening OA2 and covers the gate insulating layer 120B; wherein, the method for forming the second metal layer can be vapor deposition, sputtering, or CVD. Next, the second metal layer is partially etched to expose a portion of the upper surface of the gate insulating layer 120B, leaving the second metal layer as the gate 130B as shown in FIG16F.

[0098] The manufacturing method of the nitride semiconductor device shown in Figure 17 is based on the manufacturing method of the nitride semiconductor device shown in Figure 15, with the addition of steps S116B and S119B to S125B. Steps S116B and S119B to S125B shown in Figure 15 are the same as steps S116A and S119A to S125A shown in Figure 13, and will not be described again.

[0099] In summary, the nitride semiconductor device and its manufacturing method of this application achieve normally-off operation of GaN HEMT by forming a first polarization layer, a polarization control layer and a second polarization layer, and adjusting the two-dimensional electron gas of the channel layer.

[0100] 1A, 1B, 1C, 1D, 2A, 2B, 2C: Nitride semiconductor devices 10A, 10B:Substrate 20A, 20B: Channel Layer 30A: First polarization layer 30B: Spacer layer 40A: Polarization control layer 40B: Polarization layer 50A: Second polarization layer 60A, 50B: First buffer layer 70A, 60B: Second Buffer Layer 80A, 70B: Back barrier layer 90A: First spacer layer 100A: Second spacer layer 110A: Cap layer 120A, 80B: First passivation layer 130A, 90B: Drain 131A, 91B: First extension 132A, 92B: First electrode section 140A, 100B: Source electrode 141A, 101B: Second extension 142A, 102B: Second electrode section 150A, 110B: Second passivation layer 160A, 120B: Gate insulation layer 170A, 130B: Gate 180A, 140B: Interlayer dielectric layers 190A, 150B: Intermetallic dielectric layer 200A, 160B: Third passivation layer 210A, 170B: Oxide layer M1A, M1B: First metal bolt M2A, M2B: Second metal bolts MS1, MS2: Platform Structure OA1, OA2: Openings Psp1, Psp2, Psp3: Spontaneous polarization coefficients Ppe2, Ppe3: Piezoelectric coefficients S1A to S14A, S111A to S125A, S1B to S7B, S111B to S125B: Steps

Claims

1. A nitride semiconductor device, comprising: One substrate; A channel layer is disposed on the substrate; A first polarization layer is disposed on the channel layer; A first spacer layer is disposed between the first polarization layer and the channel layer; a polarization control layer is disposed on the first polarization layer; a second polarization layer is disposed on the polarization control layer; and a second spacer layer is disposed between the polarization control layer and the second polarization layer; wherein the lattice constants of the first polarization layer and the second polarization layer are smaller than the lattice constant of the polarization control layer.

2. The nitride semiconductor device as claimed in claim 1, wherein the material of the first polarization layer, the material of the polarization control layer, and the material of the second polarization layer are aluminum gallium nitride, and the aluminum ratio of the first polarization layer and the aluminum ratio of the second polarization layer are greater than the aluminum ratio of the polarization control layer.

3. The nitride semiconductor device as claimed in claim 1, further comprising: At least one buffer layer is disposed between the substrate and the channel layer; And a back barrier layer, disposed on at least one of the buffer layers.

4. The nitride semiconductor device as claimed in claim 1, further comprising: A cap layer is disposed on the second polarization layer.

5. The nitride semiconductor device as claimed in claim 4, wherein, The first spacer layer, the first polarization layer, the polarization control layer, the second spacer layer, the second polarization layer, and the cap layer form a platform structure, which exposes the channel layer. The nitride semiconductor device further includes: a first passivation layer disposed on the platform structure; a drain electrode disposed on one side of the platform structure and located on the first passivation layer, extending from the first passivation layer to the channel layer; and a source electrode disposed on the other side of the platform structure and located on the first passivation layer, extending from the first passivation layer to the channel layer.

6. The nitride semiconductor device as claimed in claim 5, wherein, The drain includes a first extension and a first electrode portion. The first extension extends from the first passivation layer to the channel layer. The first electrode portion is disposed on the first passivation layer and penetrates the first passivation layer to connect with the first extension. The source includes a second extension and a second electrode portion. The second extension extends from the first passivation layer to the channel layer. The second electrode portion is disposed on the first passivation layer and penetrates the first passivation layer to connect with the second extension. The materials of the first extension and the second extension include n-type gallium nitride, n-type gallium indium nitride, or a metal material.

7. The nitride semiconductor device as claimed in claim 5, further comprising: A second passivation layer is disposed on the first passivation layer and has an opening that extends to the second spacer layer; A gate insulating layer is disposed on the second passivation layer, and a portion of the gate insulating layer is disposed in the opening; and a gate is disposed in the opening and electrically insulated from the second spacer layer through the gate insulating layer.

8. The nitride semiconductor device as claimed in claim 7 further includes an oxide layer disposed at the bottom of the opening, and the gate insulating layer located on the oxide layer.

9. The nitride semiconductor device as claimed in claim 7, further comprising: An inter-dielectric layer is disposed on the gate and located on the gate insulating layer; A plurality of first metal pins are disposed on the interlayer dielectric layer and penetrate the interlayer dielectric layer, the gate insulating layer and the second passivation layer to connect the drain and the source.

10. The nitride semiconductor device as claimed in claim 9, further comprising: An inter-metal dielectric layer is disposed on the inter-metal dielectric layer; a plurality of second metal pins are disposed on the inter-metal dielectric layer and penetrate the inter-metal dielectric layer to connect the plurality of first metal pins; and a third passivation layer is disposed on the inter-metal dielectric layer and exposes the plurality of second metal pins.

11. The nitride semiconductor device as claimed in claim 4, wherein the thickness of the cap layer is less than the thickness of the second polarization layer.

12. The nitride semiconductor device as claimed in claim 11, wherein, The thickness of the channel layer is greater than the thickness of the polarization control layer, and the thickness of the polarization control layer is greater than the thickness of the first polarization layer.

13. The nitride semiconductor device as claimed in claim 1 or 12, wherein, The thickness of the first spacer layer is less than the thickness of the first polarization layer and the thickness of the channel layer, and the thickness of the second spacer layer is less than the thickness of the polarization control layer and the thickness of the second polarization layer.

14. The nitride semiconductor device as claimed in claim 4, further comprising: A passivation layer is disposed on the cap layer and has an opening that extends to the second spacer layer; A gate insulating layer is disposed on the passivation layer, and a portion of the gate insulating layer is disposed in the opening; and a gate is disposed in the opening and electrically insulated from the second spacer layer through the gate insulating layer.

15. The nitride semiconductor device of claim 14 further includes an oxide layer disposed at the bottom of the opening, and the gate insulating layer located on the oxide layer.

16. The nitride semiconductor device as claimed in claim 14, further comprising: An interlayer dielectric layer is disposed on the gate and located on the gate insulating layer; a plurality of first metal pins are disposed on the interlayer dielectric layer and penetrate the interlayer dielectric layer, the gate insulating layer and the passivation layer to connect the drain and the source respectively.

17. The nitride semiconductor device as claimed in claim 16, further comprising: An inter-metal dielectric layer is disposed on the inter-metal dielectric layer; a plurality of second metal pins are disposed on the inter-metal dielectric layer and penetrate the inter-metal dielectric layer to connect the plurality of first metal pins; and a third passivation layer is disposed on the inter-metal dielectric layer and exposes the plurality of second metal pins.

18. A method for manufacturing a nitride semiconductor device, comprising: A channel layer, a first spacer layer, a first polarization layer, a polarization control layer, a second spacer layer, a second polarization layer, and a cap layer are sequentially formed on a substrate; the channel layer, the first spacer layer, the first polarization layer, the polarization control layer, the second spacer layer, the second polarization layer, and the cap layer are partially etched to form a platform structure, wherein the platform structure exposes the channel layer; a first passivation layer, a drain, and a source are formed on the platform structure and on both sides of the platform structure, wherein the drain and the source are located on the first passivation layer and extend from the first passivation layer to the channel layer; a second passivation layer is formed on the first passivation layer, and the second passivation layer is partially etched to give the second passivation layer an opening, wherein the opening extends to the second spacer layer; a gate insulating layer is formed on the second passivation layer and in the opening; and a gate is formed on the gate insulating layer.

19. The method of manufacturing a nitride semiconductor device as claimed in claim 18, further comprising, prior to the step of forming the channel layer, the first spacer layer, the first polarization layer, the polarization control layer, the second spacer layer, the second polarization layer, and the cap layer on the substrate: At least one buffer layer and one back barrier layer are sequentially formed on the substrate.

20. A method for manufacturing a nitride semiconductor device as claimed in claim 18, comprising forming the first passivation layer, the drain, and the source on the platform structure and on both sides of the platform structure, comprising: A first extension and a second extension are formed on both sides of the platform structure; The first passivation layer is formed on the platform structure, the first extension, and the second extension; the first passivation layer is partially etched to expose the first extension and the second extension; a first electrode portion and a second electrode portion are formed on the first extension and the second extension, respectively, wherein the first electrode portion and the first extension constitute the drain electrode, and the second electrode portion and the second extension constitute the source electrode.

21. The method of manufacturing a nitride semiconductor device as described in claim 18 further comprises: An oxide layer is formed at the bottom of the opening, wherein the gate insulating layer is located on the oxide layer.

22. The method of manufacturing a nitride semiconductor device as described in claim 18 further comprises: A dielectric layer is formed on the gate and the gate insulating layer; Partial etching of the interlayer dielectric layer is performed to expose the drain and the source. And to form a plurality of first metal plugs to connect the drain and the source.

23. The method of manufacturing a nitride semiconductor device as described in claim 22 further comprises: A metal interlayer dielectric layer is formed on the interlayer dielectric layer and on the plurality of the first metal pins; Partial etching of the intermetallic dielectric layer exposes a plurality of the first metal pins; a plurality of second metal pins are formed to connect the plurality of the first metal pins; A third passivation layer is formed on the plurality of the second metal pins and the inter-metal dielectric layer, and the third passivation layer is partially etched to expose the plurality of the second metal pins.

24. A method for manufacturing a nitride semiconductor device, comprising: A channel layer, a first spacer layer, a first polarization layer, a polarization control layer, a second spacer layer, and a second polarization layer are sequentially formed on a substrate; the channel layer, the first spacer layer, the first polarization layer, the polarization control layer, the second spacer layer, and the second polarization layer are partially etched to form a platform structure, wherein the platform structure exposes the channel layer; a passivation layer, a drain, and a source are formed on the platform structure and on both sides of the platform structure, wherein the drain and the source are located on the passivation layer and extend from the passivation layer to the channel layer; the passivation layer is partially etched to give the passivation layer an opening, wherein the opening extends to the second spacer layer; and a gate is formed in the opening.

25. The method of manufacturing a nitride semiconductor device as claimed in claim 24, further comprising, prior to the step of forming the gate: A gate insulating layer is formed on the passivation layer and in the opening, so that the gate is formed on the gate insulating layer.

26. A method for manufacturing a nitride semiconductor device as claimed in claim 24, comprising forming the passivation layer, the drain, and the source on the platform structure and on both sides of the platform structure, comprising: A first extension and a second extension are formed on both sides of the platform structure; The passivation layer is formed on the platform structure, the first extension, and the second extension; the passivation layer is partially etched to expose the first extension and the second extension; a first electrode portion and a second electrode portion are formed on the first extension and the second extension, respectively, wherein the first electrode portion and the first extension constitute the drain electrode, and the second electrode portion and the second extension constitute the source electrode.

27. The method of manufacturing a nitride semiconductor device as described in claim 24, further comprising: An oxide layer is formed at the bottom of the opening, wherein the gate insulating layer is located on the oxide layer.

28. The method of manufacturing a nitride semiconductor device as described in claim 24, further comprising: A dielectric layer is formed on the gate and the gate insulating layer; Partial etching of the interlayer dielectric layer is performed to expose the drain and the source. And to form a plurality of first metal plugs to connect the drain and the source.

29. The method of manufacturing a nitride semiconductor device as described in claim 28 further comprises: A metal interlayer dielectric layer is formed on the interlayer dielectric layer and on the plurality of the first metal pins; Partial etching of the intermetallic dielectric layer exposes a plurality of the first metal pins; a plurality of second metal pins are formed to connect the plurality of the first metal pins; A third passivation layer is formed on the plurality of the second metal plugs and the inter-metal dielectric layer, and the third passivation layer is partially etched to expose the plurality of the second metal plugs.

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