Vertical thin film transistor and manufacturing method thereof

Abstract

A vertical thin film transistor including a first semiconductor layer, a sacrificed layer, a second semiconductor layer, a third semiconductor layer, a first gate electrode, a source electrode and a drain electrode is provided. The first semiconductor layer is disposed on a substrate, and has a first heavily doped portion and an extension portion. The sacrificed layer covers the extension portion of the first semiconductor layer and exposes the first heavily doped portion. The second semiconductor layer is disposed on the sacrificed layer and has a second heavily doped portion. The third semiconductor layer covers and contacts a part of the first heavily doped portion, a sidewall of the sacrificed layer and a part of the second heavily doped portion. In a direction perpendicular to the substrate, the second heavily doped portion overlaps the extension portion, and the first gate electrode overlaps the second heavily doped portion, the extension portion and the third semiconductor layer. The source electrode and the drain electrode are electrically connected tot the first heavily doped portion and the second heavily doped portion respectively.

Description

Technical Field

[0001] This invention relates to a transistor and a method for manufacturing the same, and more particularly to a vertical thin-film transistor and a method for manufacturing the same. Prior Technology

[0002] To meet the demands of high-resolution, low-power, and high-frequency display operations, short-channel thin-film transistors with high switching speeds, high electron mobility, and smaller dimensions have become a key development focus. Among these, vertical thin-film transistors, with their high integration, are particularly favored for their ability to further save layout space and manufacturing costs. However, existing vertical thin-film transistors still face some challenges, such as poor process stability, which prevents their operational electrical performance from reaching the expected levels. Summary of the Invention

[0003] This invention provides a vertical thin-film transistor with an ultra-short channel and stable operating electrical properties.

[0004] This invention provides a method for manufacturing a vertical thin-film transistor, which has better process stability and production yield.

[0005] The vertical thin-film transistor of the present invention includes a first semiconductor layer, a sacrificial layer, a second semiconductor layer, a third semiconductor layer, a first gate, a source, and a drain. The first semiconductor layer is disposed on a substrate and has a first heavily doped portion and an extended portion. The sacrificial layer covers the extended portion of the first semiconductor layer and exposes the first heavily doped portion. The second semiconductor layer is disposed on the sacrificial layer and has a second heavily doped portion. In a direction perpendicular to the substrate, the second heavily doped portion overlaps with the extended portion of the first semiconductor layer. The third semiconductor layer covers and contacts a portion of the first heavily doped portion, the sidewalls of the sacrificial layer, and a portion of the second heavily doped portion. In a direction perpendicular to the substrate, the first gate overlaps the second heavily doped portion, the extended portion, and the third semiconductor layer. The source and drain are electrically connected to the first heavily doped portion and the second heavily doped portion, respectively.

[0006] The method for manufacturing a vertical thin-film transistor of the present invention includes forming a first semiconductor material layer on a substrate; forming a sacrificial layer on the first semiconductor material layer to cover a first portion of the first semiconductor material layer and expose a second portion of the first semiconductor material layer; forming a second semiconductor material layer on the sacrificial layer; performing a heavy doping process on the second portion of the first semiconductor material layer and the second semiconductor material layer; forming a third semiconductor layer on the first semiconductor material layer and the second semiconductor material layer after the heavy doping process; performing a laser annealing process on the first semiconductor layer and the second semiconductor material layer; forming a gate and a source and a drain on the substrate. After the heavy doping process and the laser annealing process, the first portion and the second portion of the first semiconductor material layer respectively form an extension portion and a first heavily doped portion of the first semiconductor layer, and the second semiconductor material layer forms a second heavily doped portion of the second semiconductor layer. The source and drain are electrically connected to the first heavily doped portion and the second heavily doped portion, respectively.

[0007] Based on the above, in a vertical thin-film transistor and its manufacturing method according to an embodiment of the present invention, the first semiconductor layer, in addition to the first heavily doped portion, also has an extension portion extending between the sacrificial layer and the substrate. This extension portion prevents the subsequently formed third semiconductor layer from getting trapped in the gap between the sacrificial layer and the first heavily doped portion due to insufficient process precision, thus avoiding the formation of an effective short channel. In other words, it can significantly improve the process margin of the sacrificial layer, thereby enhancing the process and operational stability of the vertical thin-film transistor. Simple Explanation of the Diagram

[0008] Figure 1 is a cross-sectional schematic diagram of a vertical thin-film transistor according to a first embodiment of the present invention. Figures 2A to 2F are cross-sectional schematic diagrams of the manufacturing process of the vertical thin-film transistor shown in Figure 1. Figures 3A to 3E are cross-sectional schematic diagrams of another manufacturing process for the vertical thin-film transistor shown in Figure 1. Figure 4 is a cross-sectional schematic diagram of a vertical thin-film transistor according to a second embodiment of the present invention. Figures 5A to 5F are cross-sectional schematic diagrams of the manufacturing process of the vertical thin-film transistor shown in Figure 4. Figure 6 is a cross-sectional schematic diagram of a vertical thin-film transistor according to a third embodiment of the present invention. Figure 7 is a cross-sectional schematic diagram of a vertical thin-film transistor according to a fourth embodiment of the present invention. Figures 8A to 8G are cross-sectional schematic diagrams of the manufacturing process of the vertical thin-film transistor shown in Figure 7. Figure 9 is a cross-sectional schematic diagram of a component substrate according to an embodiment of the present invention. Figures 10A to 10H are cross-sectional schematic diagrams of the manufacturing process of the component substrate in Figure 9. Implementation

[0009] As used herein, “about,” “approximately,” “essentially,” or “substantially” includes the value and the average value within an acceptable range of deviations from a particular value as determined by one of ordinary skill in the art, taking into account the measurement under discussion and a particular number of errors associated with the measurement (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the value, or, for example, within ±30%, ±20%, ±15%, ±10%, ±5%. Furthermore, as used herein, “about,” “approximately,” “essentially,” or “substantially” may be used to select a more acceptable range of deviations or standard deviations depending on the nature of the measurement, the cutting nature, or other properties, and not necessarily apply to all properties with a single standard deviation.

[0010] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected" to another element, it may be directly on or connected to the other element, or intermediate elements may also be present. Conversely, when an element is referred to as being "directly on" or "directly connected" to another element, no intermediate elements are present. As used herein, "connection" can refer to physical and / or electrical connection. Furthermore, "electrical connection" may mean the presence of other elements between two elements.

[0011] Furthermore, relative terms such as "below" or "bottom" and "above" or "top" may be used herein to describe the relationship between one element and another, as illustrated in the figures. It should be understood that relative terms are intended to include different orientations of the device beyond those shown in the figures. For example, if a device in one figure is flipped, an element described as being "below" the other element will be oriented "above" the other element. Thus, the exemplary term "below" can include both "below" and "above" orientations, depending on the specific orientation of the figure. Similarly, if a device in one figure is flipped, an element described as being "below" or "under" the other element will be oriented "above" the other element. Thus, the exemplary terms "above" or "below" can include both "above" and "below" orientations.

[0012] This document describes exemplary embodiments with reference to cross-sectional views, which are schematic diagrams of idealized embodiments. Therefore, variations in the shape of the illustrations can be expected as a result of, for example, manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include, for example, shape deviations caused by manufacturing processes. For example, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, the acute angles shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0013] The exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0014] Figure 1 is a cross-sectional schematic diagram of a vertical thin-film transistor according to a first embodiment of the present invention. Figures 2A to 2F are cross-sectional schematic diagrams of the manufacturing process of the vertical thin-film transistor of Figure 1. Figures 3A to 3E are cross-sectional schematic diagrams of another manufacturing process of the vertical thin-film transistor of Figure 1.

[0015] Referring to Figure 1, the vertical thin-film transistor (VTFT) includes a first semiconductor layer 110, a sacrificial layer 115, a second semiconductor layer 120, and a third semiconductor layer 130. The first semiconductor layer 110 is disposed on the substrate 100 and has a first heavily doped portion 110hd and an extension portion 110ex. In this embodiment, a buffer layer 105 may also be provided between the first semiconductor layer 110 and the substrate 100. The material of the buffer layer 105 is, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials). In some embodiments, the buffer layer 105 may be a single-layer structure or a multi-layer structure, but is not limited thereto.

[0016] A sacrificial layer 115 is disposed on the substrate 100. Notably, the sacrificial layer 115 covers the extension 110ex of the first semiconductor layer 110 and exposes the first heavily doped portion 110hd, wherein the sidewalls of the extension 110ex are in contact with the sidewalls of the first heavily doped portion 110hd. Alternatively, the extension 110ex of the first semiconductor layer 110 extends from the first heavily doped portion 110hd and extends below the sacrificial layer 115. For example, the extension length L of the extension 110ex below the sacrificial layer 115 may be greater than or equal to 0.5 μm, but is not limited thereto.

[0017] The first semiconductor layer 110 can be a single-layer or multi-layer structure. In a preferred embodiment, the material of the first heavily doped portion 110hd of the first semiconductor layer 110 may include a polysilicon semiconductor material, while the material of its extended portion 110ex may include an amorphous silicon semiconductor material, but is not limited thereto. The material of the sacrificial layer 115 includes, for example, silicon oxide and silicon nitride, but is not limited thereto.

[0018] A second semiconductor layer 120 is disposed on the sacrificial layer 115 and has a second heavily doped portion 120hd. In a direction perpendicular to the substrate 100 (e.g., direction Z), the second heavily doped portion 120hd of the second semiconductor layer 120 overlaps with an extension 110ex of the first semiconductor layer 110. For example, in this embodiment, the dopant concentration of the second heavily doped portion 120hd is substantially the same as the dopant concentration of the first heavily doped portion 110hd, but this is not a limitation. The second semiconductor layer 120 can be a single-layer structure or a multi-layer structure. In a preferred embodiment, the material of the second semiconductor layer 120 may include a polysilicon semiconductor material, but this is not a limitation.

[0019] The third semiconductor layer 130 covers and contacts a portion of the first heavily doped portion 110hd, the sidewall 115sw of the sacrificial layer 115, and a portion of the second heavily doped portion 120hd. For example, in this embodiment, the third semiconductor layer 130 may contact a portion of the surface 110s2 of the first heavily doped portion 110hd facing away from the substrate 100 and a portion of the surface 120s of the second heavily doped portion 120hd facing away from the substrate 100. The third semiconductor layer 130 may be a single-layer structure or a multi-layer structure.

[0020] In a preferred embodiment, the material of the third semiconductor layer 130 may include, but is not limited to, a polysilicon semiconductor material. Specifically, the portion of the third semiconductor layer 130 that contacts the sidewall 115sw of the sacrificial layer 115 may define the channel region CH of the vertical thin-film transistor (VTFT). In this embodiment, the length of the channel region CH may be less than 3 μm. That is, the vertical thin-film transistor (VTFT) of this embodiment may be a thin-film transistor with an ultra-short channel.

[0021] In a preferred embodiment, the thickness 115t of the sacrificial layer 115 may be greater than or equal to twice the thickness 110t of the first heavily doped portion 110hd or the thickness 120t of the second heavily doped portion 120hd, wherein the defining direction of each film layer thickness is, for example, along a direction perpendicular to the substrate 100 (e.g., direction Z), but is not limited thereto. To ensure that the vertical thin-film transistor VTFT has sufficient channel length, the angle θ between the sidewall 115sw of the sacrificial layer 115 and the surface 110s1 of the extension portion 110ex of the first semiconductor layer 110 connecting the sacrificial layer 115 is less than 90 degrees. In a preferred embodiment, the angle θ may be less than 60 degrees, for example, any angle in the range of 30 degrees to 60 degrees.

[0022] First, it should be noted that since the first semiconductor layer 110, in addition to the first heavily doped portion 110hd, also has an extension portion 110ex extending between the sacrificial layer 115 and the substrate 100, it can effectively prevent the formation of gaps between the sacrificial layer 115 and the first heavily doped portion 110hd due to insufficient process precision, which would cause the subsequently formed third semiconductor layer 130 to fall into the gaps and fail to form an effective short channel. In other words, the provision of the extension portion 110ex can significantly improve the process margin of the sacrificial layer 115, thereby improving the process and operational stability of the vertical thin-film transistor (VTFT).

[0023] Furthermore, the vertical thin-film transistor (VTFT) also includes a gate (GE), a source (SE), and a drain (DE) disposed on the substrate 100. For example, in this embodiment, the gate (GE) may be disposed on the side of the third semiconductor layer 130 facing away from the substrate 100. That is, the vertical thin-film transistor (VTFT) of this embodiment may be a top-gate thin-film transistor, but is not limited thereto. More specifically, in the Z direction, the gate (GE) may overlap the first heavily doped portion 110hd, the extension portion 110ex, the second heavily doped portion 120hd, and the third semiconductor layer 130.

[0024] In this embodiment, a dielectric layer 135 may be provided between the third semiconductor layer 130 and the gate GE. The dielectric layer 135 may be a single-layer structure or a multi-layer structure, and its material may include, for example, silicon oxide, silicon nitride, or other suitable insulating materials. For example, an insulating layer 145 may be covered on the gate GE, and the source SE and drain DE are disposed on the insulating layer 145. The material of the insulating layer 145 may include, for example, inorganic materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a stack of at least two of the above materials), organic materials (e.g., polyester (PET), polyolefins, polyacrylic acids, polycarbonates, polyoxyalkylene compounds, polystyrene, polyethers, polyketides, polyols, polyaldehydes, or other suitable materials, or combinations thereof), or other suitable materials, or combinations thereof.

[0025] In this embodiment, the source (SE) and drain (DE) can penetrate the insulating layer 145 and the dielectric layer 135 to electrically connect the first heavily doped portion 110hd of the first semiconductor layer 110 and the second heavily doped portion 120hd of the second semiconductor layer 120, respectively. The gate (GE), source (SE), and drain (DE) can each be a single-layer or multi-layer structure, and their materials include, for example, transparent conductive materials (e.g., metal oxides), non-transparent conductive materials (e.g., molybdenum, aluminum, copper, titanium, chromium, etc.), combinations thereof, or other suitable conductive materials.

[0026] It should be noted that the vertical thin-film transistor (VTFT) of this embodiment can be applied on the element substrate 10, and the element substrate 10 can serve as the driving circuit board for the display panel. The display panel can be a self-emissive display panel, such as an organic light-emitting diode (OLED) display panel or a micro light-emitting diode (micro-LED) display panel, but is not limited thereto. In other applications, the display panel can also be a non-self-emissive display panel, such as a liquid crystal display (LCD) panel or an electrophoretic display (EPD) panel.

[0027] For example, a vertical thin-film transistor (VTFT) can be used as a driving element in the display area of ​​a display panel, such as a driving element for display sub-pixels, but is not limited thereto. In other applications, a vertical thin-film transistor (VTFT) can also be used as a driving element in the non-display area of ​​a display panel, such as a driving element for peripheral circuits.

[0028] The following is an exemplary description of a method for manufacturing a vertical thin-film transistor (VTFT). Referring to FIGA, firstly, a buffer layer 105 and a first semiconductor material layer 110M are sequentially formed on a substrate 100. Preferably, the first semiconductor material layer 110M is made of, for example, amorphous silicon semiconductor material. However, the present invention is not limited thereto. In another embodiment, the first semiconductor material layer 110M can be formed directly on the substrate 100, that is, the buffer layer 105 can be omitted.

[0029] Referring to Figures 2B and 2C, a sacrificial material layer 115M is then formed on the first semiconductor material layer 110M, and a second semiconductor material layer 120M is formed on the sacrificial material layer 115M. The sacrificial material layer 115M and the second semiconductor material layer 120M are patterned to form a stacked structure of the sacrificial layer 115M and the second semiconductor material layer 120M. The patterning process is, for example, photolithography, but is not limited to this.

[0030] It is particularly noteworthy that the sacrificial layer 115, formed through a patterning process, covers the first portion 110Mp1 of the first semiconductor material layer 110M and exposes the second portion 110Mp2 of the first semiconductor material layer 110M, as shown in FIG2C. Since the first semiconductor material layer 110M reserves the first portion 110Mp1 to be covered by the sacrificial layer 115, gaps between the sacrificial layer 115 and the first semiconductor material layer 110M due to insufficient process precision can be avoided, thereby ensuring that the subsequently fabricated third semiconductor layer can form a short channel. In this embodiment, to cover deviations between the process and the design, the extension length L of the first portion 110Mp1 of the first semiconductor material layer 110M below the sacrificial layer 115 can be greater than or equal to 0.5 μm, but is not limited thereto. The extension length L can be adjusted according to the actual process deviation.

[0031] Referring to Figure 2D, a heavy doping process is performed on the second portion 110Mp2 of the first semiconductor material layer 110M and the second semiconductor material layer 120M. Since the second portion 110Mp2 of the first semiconductor material layer 110M and the second semiconductor material layer 120M are subjected to heavy doping processes simultaneously, the dopant concentration of the second portion 110Mp2 of the first semiconductor material layer 110M is substantially equal to the dopant concentration of the second semiconductor material layer 120M.

[0032] Referring to Figures 2E and 2F, after the heavy doping process is completed, a third semiconductor material layer 130M is formed on the first semiconductor material layer 110M, and laser annealing is performed on the first semiconductor material layer 110M, the second semiconductor material layer 120M, and the third semiconductor material layer 130M. After the laser annealing process, the first portion 110Mp1 and the second portion 110Mp2 of the first semiconductor material layer 110M respectively form the extension portion 110ex and the first heavily doped portion 110hd of the first semiconductor layer 110, the second semiconductor material layer 120M forms the second heavily doped portion 120hd of the second semiconductor layer 120, and the third semiconductor material layer 130M forms the third semiconductor layer 130.

[0033] For example, in this embodiment, the amorphous silicon semiconductor material of the second portion 110Mp2 of the first semiconductor material layer 110M and the second semiconductor material layer 120M will transform into polycrystalline silicon semiconductor material after being irradiated by a laser beam. However, since the second semiconductor material layer 120M covers the first portion 110Mp1 of the first semiconductor material layer 110M, the exposure of the laser beam LB received by it is insufficient, resulting in the first portion 110Mp1 of the first semiconductor material layer 110M still retaining the composition of amorphous silicon semiconductor material after the laser annealing process.

[0034] Next, a gate GE is formed on the substrate 100. In this embodiment, the manufacturing method of the vertical thin-film transistor VTFT of FIG1 may further include: forming a dielectric layer 135 to cover the third semiconductor layer 130, wherein the gate GE is formed on the dielectric layer 135. Referring to FIG2F and FIG1, after the gate GE is fabricated, an insulating layer 145 is formed to cover the gate GE and the dielectric layer 135, and a source SE and a drain DE are formed on the insulating layer 145, wherein the source SE and the drain DE penetrate the insulating layer 145 and the dielectric layer 135 to electrically connect the first heavily doped portion 110hd of the first semiconductor layer 110 and the second heavily doped portion 120hd of the second semiconductor layer 120, respectively.

[0035] This completes the fabrication of the vertical thin-film transistor VTFT shown in Figure 1.

[0036] However, the present invention is not limited thereto. In another manufacturing process of the vertical thin-film transistor (VTFT) of FIG1, the laser annealing process can be performed twice. For example, after the formation of the second semiconductor material layer 120M and the sacrificial layer 115 and before the heavy doping process, the first semiconductor material layer 110M and the second semiconductor material layer 120M can be subjected to a first laser annealing process, as shown in FIG3A and FIG3B. After the first laser annealing process is completed, the second portion 110Mp2 of the first semiconductor material layer 110M and the second semiconductor material layer 120M are subjected to a heavy doping process, as shown in FIG3B and FIG3C.

[0037] After completing the heavy doping process, a third semiconductor material layer 130M is formed on the first semiconductor layer 110 and the second semiconductor layer 120, and a second laser annealing process is performed on the third semiconductor material layer 130M to form the third semiconductor layer 130, as shown in Figures 3D and 3E. Since the steps of forming the first semiconductor material layer 110M, the second semiconductor material layer 120M, and the sacrificial layer 115, as well as the methods of forming the gate GE, source SE, and drain DE, are similar to the manufacturing methods of the aforementioned embodiments, detailed descriptions can be found in the relevant paragraphs of the aforementioned embodiments, and will not be repeated here.

[0038] The following will provide another embodiment to illustrate the present invention in detail, wherein the same components will be marked with the same symbols, and the description of the same technical content will be omitted. For the omitted parts, please refer to the foregoing embodiments, and they will not be repeated below.

[0039] Figure 4 is a cross-sectional schematic diagram of a vertical thin-film transistor according to the second embodiment of the present invention. Figures 5A to 5F are cross-sectional schematic diagrams of the manufacturing process of the vertical thin-film transistor of Figure 4. Referring to Figure 4, the difference between the vertical thin-film transistor VTFT-A of the element substrate 10A in this embodiment and the vertical thin-film transistor VTFT of Figure 1 is that the gate is positioned differently.

[0040] Specifically, the gate GE” of the vertical thin-film transistor VTFT-A can be selectively disposed below the third semiconductor layer 130. That is, the vertical thin-film transistor VTFT-A in this embodiment can be a bottom-gate thin-film transistor. In detail, in this embodiment, the sacrificial layer 115A has a first sublayer SL1 and a second sublayer SL2, and the gate GE” is sandwiched between the first sublayer SL1 and the second sublayer SL2. Therefore, in the Z direction, the gate GE” overlaps the extension portion 110ex, the second heavily doped portion 120hd, and the third semiconductor layer 130, but does not overlap the first heavily doped portion 110hd. On the other hand, since the gate GE” is enclosed within the sacrificial layer 115A, the dielectric layer 135 shown in FIG1 is not covered above the third semiconductor layer 130 in this embodiment.

[0041] The following will exemplarily describe a method for manufacturing a vertical thin-film transistor (VTFT-A). Referring to FIG5A, firstly, a buffer layer 105 and a first semiconductor material layer 110M are sequentially formed on a substrate 100. Preferably, the first semiconductor material layer 110M is made of, for example, amorphous silicon semiconductor material. However, the present invention is not limited thereto. In another embodiment, the first semiconductor material layer 110M can be formed directly on the substrate 100, that is, the buffer layer 105 can be omitted.

[0042] Referring to Figures 5B and 5C, a sacrificial material layer 115M and a gate GE” are then formed on the first semiconductor material layer 110M, and a second semiconductor material layer 120M” is formed on the sacrificial material layer 115M. The step of forming the sacrificial material layer 115M may include sequentially forming a first sub-sacrificial material layer 115Ma and a second sub-sacrificial material layer 115Mb on the first semiconductor material layer 110M. It is particularly noteworthy that the gate GE is formed after the formation of the first sub-sacrificial material layer 115Ma and before the formation of the second sub-sacrificial material layer 115Mb.

[0043] A patterning process is performed on the sacrificial material layer 115M and the second semiconductor material layer 120M to form a stacked structure of the sacrificial layer 115A and the second semiconductor material layer 120M. The patterning process is, for example, photolithography, but is not limited to it. Notably, the sacrificial layer 115A formed by the patterning process covers a first portion 110Mp1 of the first semiconductor material layer 110M and exposes a second portion 110Mp2 of the first semiconductor material layer 110M, as shown in FIG5C. Since the first semiconductor material layer 110M reserves the first portion 110Mp1 to be covered by the sacrificial layer 115A, gaps between the sacrificial layer 115A and the first semiconductor material layer 110M due to insufficient process precision can be avoided, thereby ensuring that the subsequently fabricated third semiconductor layer can form a short channel.

[0044] Referring to Figure 5D, a heavy doping process is performed on the second portion 110Mp2 of the first semiconductor material layer 110M and the second semiconductor material layer 120M. Since the second portion 110Mp2 of the first semiconductor material layer 110M and the second semiconductor material layer 120M are subjected to heavy doping processes simultaneously, the dopant concentration of the second portion 110Mp2 of the first semiconductor material layer 110M is substantially equal to the dopant concentration of the second semiconductor material layer 120M.

[0045] Referring to Figures 5E and 5F, after the heavy doping process is completed, a third semiconductor material layer 130M is formed on the first semiconductor material layer 110M, and laser annealing is performed on the first semiconductor material layer 110M, the second semiconductor material layer 120M, and the third semiconductor material layer 130M. After the laser annealing process, the first portion 110Mp1 and the second portion 110Mp2 of the first semiconductor material layer 110M respectively form the extension portion 110ex and the first heavily doped portion 110hd of the first semiconductor layer 110, the second semiconductor material layer 120M forms the second heavily doped portion 120hd of the second semiconductor layer 120, and the third semiconductor material layer 130M forms the third semiconductor layer 130.

[0046] For example, in this embodiment, the amorphous silicon semiconductor material of the second portion 110Mp2 of the first semiconductor material layer 110M and the second semiconductor material layer 120M will transform into polycrystalline silicon semiconductor material after being irradiated by a laser beam. However, since the second semiconductor material layer 120M covers the first portion 110Mp1 of the first semiconductor material layer 110M, the exposure of the laser beam LB received by it is insufficient, resulting in the first portion 110Mp1 of the first semiconductor material layer 110M still retaining the composition of amorphous silicon semiconductor material after the laser annealing process.

[0047] Referring to Figures 5F and 4, after the fabrication of the third semiconductor layer 130 is completed, an insulating layer 145 is formed to cover the third semiconductor layer 130. A source electrode (SE) and a drain electrode (DE) are formed on the insulating layer 145, wherein the source electrode (SE) and the drain electrode (DE) penetrate the insulating layer 145 to electrically connect the first heavily doped portion 110hd of the first semiconductor layer 110 and the second heavily doped portion 120hd of the second semiconductor layer 120, respectively. This completes the fabrication of the vertical thin-film transistor VTFT-A shown in Figure 4.

[0048] Figure 6 is a cross-sectional schematic diagram of a vertical thin-film transistor according to a third embodiment of the present invention. Referring to Figure 6, in the element substrate 10B of this embodiment, the vertical thin-film transistor VTFT-B can be a dual-gate thin-film transistor. Specifically, the vertical thin-film transistor VTFT-B of this embodiment can simultaneously have a gate GE located above the third semiconductor layer 130 and a gate GE” located below the third semiconductor layer 130. Since the setting and formation method of the gate GE in this embodiment is similar to the gate GE of the vertical thin-film transistor VTFT in Figure 1, and the setting and formation method of the gate GE” is similar to the gate GE” of the vertical thin-film transistor VTFT-A in Figure 4, detailed descriptions can be found in the relevant paragraphs of the foregoing embodiments, and will not be repeated here.

[0049] Figure 7 is a cross-sectional schematic diagram of a vertical thin-film transistor according to a fourth embodiment of the present invention. Figures 8A to 8G are cross-sectional schematic diagrams of the manufacturing process of the vertical thin-film transistor of Figure 7. Referring to Figure 7, compared with the vertical thin-film transistor VTFT of Figure 1, the vertical thin-film transistor VTFT-C of the element substrate 10C in this embodiment further includes a first etch protection pattern 161 and a second etch protection pattern 162.

[0050] In this embodiment, a first etch protection pattern 161 is disposed between the first heavily doped portion 110hd of the first semiconductor layer 110 and the third semiconductor layer 130A, and contacts the first heavily doped portion 110hd and the third semiconductor layer 130A. A second etch protection pattern 162 is disposed between the second heavily doped portion 120hd of the second semiconductor layer 120 and the third semiconductor layer 130A, and contacts the second heavily doped portion 120hd and the third semiconductor layer 130A. The source electrode SE penetrates the insulating layer 145, the dielectric layer 135, the third semiconductor layer 130A, and the first etch protection pattern 161 to electrically connect with the first heavily doped portion 110hd of the first semiconductor layer 110. The drain electrode DE penetrates the insulating layer 145, the dielectric layer 135, the third semiconductor layer 130A, and the second etch protection pattern 162 to electrically connect with the second heavily doped portion 120hd of the second semiconductor layer 120.

[0051] Alternatively, the source SE can be electrically connected to the first heavily doped portion 110hd via the first contact hole TH1 of the first etch protection pattern 161 through the insulating layer 145, dielectric layer 135, third semiconductor layer 130A, and the first etch protection pattern 161, while the drain DE can be electrically connected to the second heavily doped portion 120hd via the second contact hole TH2 of the second etch protection pattern 162 through the insulating layer 145, dielectric layer 135, third semiconductor layer 130A, and the second etch protection pattern 162. It is particularly noteworthy that the orthogonal projections of the first contact hole TH1 and the second contact hole TH2 onto the substrate 100 lie within the orthogonal projections of the first etch protection pattern 161 and the second etch protection pattern 162 onto the substrate 100.

[0052] Because the etching solution used in the etching process of the third semiconductor layer 130A does not have an etching selectivity for the third semiconductor layer 130A and the first heavily doped portion 110hd (or the second heavily doped portion 120hd), when etching the third semiconductor layer 130A in order to expose the first heavily doped portion 110hd and the second heavily doped portion 120hd, it is easy to damage or even break the film of the underlying heavily doped portion, resulting in the failure of the electrical connection between the source SE and the drain DE and the heavily doped portion.

[0053] Therefore, by providing the aforementioned first etch protection pattern 161 and second etch protection pattern 162, damage to the heavily doped portion from the etch solution during the etching of the third semiconductor layer 130A can be prevented. Preferably, the materials of the first etch protection pattern 161 and the second etch protection pattern 162 may include silicon oxide (SiO) or silicon nitride (SiN). From another perspective, during the etching process of the etch protection pattern, since the etch solution has an etching selectivity ratio for the material of the etch protection pattern (e.g., SiO or SiN) and the material of the heavily doped portion (e.g., Si), damage to the heavily doped portion from the etch solution during the etching process of the etch protection pattern can be prevented.

[0054] The following will exemplarily describe a method for manufacturing a vertical thin-film transistor (VTFT-C). Referring to FIG8A, firstly, a buffer layer 105 and a first semiconductor material layer 110M are sequentially formed on a substrate 100. Preferably, the first semiconductor material layer 110M is made of, for example, amorphous silicon semiconductor material. However, the present invention is not limited thereto. In another embodiment, the first semiconductor material layer 110M can be formed directly on the substrate 100, that is, the buffer layer 105 can be omitted.

[0055] Referring to Figures 8B and 8C, a sacrificial material layer 115M is then formed on the first semiconductor material layer 110M, and a second semiconductor material layer 120M is formed on the sacrificial material layer 115M. The sacrificial material layer 115M and the second semiconductor material layer 120M are patterned to form a stacked structure of the sacrificial layer 115M and the second semiconductor material layer 120M. The patterning process is, for example, photolithography, but is not limited to this.

[0056] It should be noted that in the manufacturing process of the vertical thin-film transistor VTFT-C in this embodiment, the laser annealing process can be performed twice. For example, after forming the second semiconductor material layer 120M and the sacrificial layer 115 and before performing the heavy doping process, the first semiconductor material layer 110M and the second semiconductor material layer 120M can be subjected to a first laser annealing process, as shown in Figures 8C and 8D. After completing the first laser annealing process, the second portion 110Mp2 of the first semiconductor material layer 110M and the second semiconductor material layer 120M are subjected to a heavy doping process, as shown in Figures 8D and 8E.

[0057] After the heavy doping process is completed, a first etch protection pattern 161 and a second etch protection pattern 162 are formed on the first heavily doped portion 110hd of the first semiconductor layer 110 and the second heavily doped portion 120hd of the second semiconductor layer 120, respectively. Next, a third semiconductor material layer 130M is formed to cover the first etch protection pattern 161, the second etch protection pattern 162, the first heavily doped portion 110hd, the second heavily doped portion 120hd, and the sidewall 115sw of the sacrificial layer 115. The third semiconductor material layer 130M is then subjected to a second laser annealing process to form the third semiconductor layer 130A, as shown in Figures 8F and 8G.

[0058] Referring to Figures 8G and 7, after the fabrication of the third semiconductor layer 130A is completed, a gate GE is formed on the substrate 100. In this embodiment, the manufacturing method of the vertical thin-film transistor VTFT-C of Figure 7 may further include: forming a dielectric layer 135 to cover the third semiconductor layer 130A, wherein the gate GE is formed on the dielectric layer 135. After the fabrication of the gate GE is completed, an insulating layer 145 is formed to cover the gate GE and the dielectric layer 135, and a source SE and a drain DE are formed on the insulating layer 145, wherein the source SE and drain DE penetrate the insulating layer 145, the dielectric layer 135, the third semiconductor layer 130A, and the etched protective pattern to electrically connect the first heavily doped portion 110hd of the first semiconductor layer 110 and the second heavily doped portion 120hd of the second semiconductor layer 120, respectively. Thus, the fabrication of the vertical thin-film transistor VTFT-C of Figure 7 is completed.

[0059] Figure 9 is a cross-sectional schematic diagram of a component substrate according to an embodiment of the present invention. Figures 10A to 10H are cross-sectional schematic diagrams of the manufacturing process of the component substrate of Figure 9. Referring to Figure 9, compared with the component substrate 10B of Figure 6, the component substrate 10D of this embodiment may also be provided with a thin-film transistor (TFT). Unlike the vertical thin-film transistor VTFT-D, which is a bottom-gate thin-film transistor, the thin-film transistor TFT is a top-gate thin-film transistor.

[0060] In this embodiment, the thin-film transistor (TFT) may include a source (SE'), a drain (DE'), a gate (GE'), a third doped portion 121hd, a fourth doped portion 122hd, and a channel (120ch). Specifically, the third doped portion 121hd, the fourth doped portion 122hd, and the channel (120ch) of the TFT may be on the same film layer as the second doped portion 120hd of the vertical thin-film transistor (VTFT-D), for example, a second semiconductor layer 120A. The second etch-protected pattern 162A covering a portion of the second doped portion 120hd of the vertical thin-film transistor (VTFT-D) may also cover the third doped portion 121hd, the fourth doped portion 122hd, and the channel (120ch) of the TFT. The gate (GE') of the TFT is disposed on the second etch-protected pattern 162A and is covered by an insulating layer 145. The source SE' and drain DE' of a thin-film transistor (TFT) can be the same film layer as the source SE and drain DE of a vertical thin-film transistor (VTFT-D).

[0061] It should be noted that in this embodiment, a second etch protection pattern 162A is provided between the gate GE' of the thin-film transistor TFT and the second semiconductor layer 120A, so there is no need to provide the dielectric layer 135 as shown in FIG1 to isolate the gate GE' and the channel 120ch.

[0062] The following will exemplarily describe the manufacturing methods of vertical thin-film transistor VTFT-D and thin-film transistor TFT. Referring to FIG10A, firstly, a buffer layer 105 and a first semiconductor material layer 110M are sequentially formed on a substrate 100. Preferably, the first semiconductor material layer 110M is made of, for example, amorphous silicon semiconductor material. However, the present invention is not limited thereto. In another embodiment, the first semiconductor material layer 110M can be formed directly on the substrate 100, that is, the buffer layer 105 can be omitted.

[0063] Referring to Figure 10B, a sacrificial layer 115A and a gate GE are then formed on the first semiconductor material layer 110M. Since the steps for forming the sacrificial layer 115A and the gate GE in this embodiment are similar to those in Figure 4, detailed explanations can be found in the relevant paragraphs of the aforementioned embodiments, and will not be repeated here. It is particularly noteworthy that the sacrificial layer 115A formed via the patterning process covers the first portion 110Mp1 of the first semiconductor material layer 110M and exposes the second portion 110Mp2 of the first semiconductor material layer 110M. Because the first semiconductor material layer 110M reserves the first portion 110Mp1 to be covered by the sacrificial layer 115A, gaps between the sacrificial layer 115A and the first semiconductor material layer 110M due to insufficient process precision can be avoided, thereby ensuring that the subsequently fabricated third semiconductor layer can form a short channel.

[0064] Referring to Figure 10C, a second semiconductor material layer 120M is formed on the sacrificial layer 115A, and a laser annealing process is performed on the first semiconductor material layer 110M and the second semiconductor material layer 120M. As shown in Figure 10D, an etch protection material layer 160M is then formed to cover the first semiconductor material layer 110M and the second semiconductor material layer 120M, and another gate GE' is formed on the etch protection material layer 160M.

[0065] After the gate GE' is fabricated, the second portion 110Mp2 of the first semiconductor material layer 110M and the second semiconductor material layer 120M are subjected to a heavy doping process, as shown in Figures 10D and 10E. The first portion 110Mp1 and the second portion 110Mp2 of the first semiconductor material layer 110M form the extension portion 110ex and the first heavily doped portion 110hd of the first semiconductor layer 110, respectively. The second semiconductor material layer 120M forms the second heavily doped portion 120hd, the third heavily doped portion 121hd and the fourth heavily doped portion 122hd of the second semiconductor layer 120A. The undoped portion of the second semiconductor material layer 120M (i.e., the portion overlapping the gate GE' along the Z direction) forms the channel 120ch.

[0066] Referring to Figures 10E and 10F, the etch protection material layer 160M is then patterned to form a first etch protection pattern 161 and a second etch protection pattern 162A, exposing a portion of the first heavily doped portion 110hd, the sidewall 115sw of the sacrificial layer 115A, and a portion of the second heavily doped portion 120hd. After the patterning process of the etch protection material layer 160M is completed, a third semiconductor material layer 130M is formed to cover the etch protection pattern, a portion of the first heavily doped portion 110hd, the sidewall 115sw of the sacrificial layer 115A, and a portion of the second heavily doped portion 120hd. The third semiconductor material layer 130M then undergoes another laser annealing and patterning process to form the third semiconductor layer 130, as shown in Figures 10G and 10H. The patterning process can be, for example, photolithography, but is not limited to this.

[0067] Because the etching solution used in the etching process of the third semiconductor material layer 130M does not have an etching selectivity for the third semiconductor material layer 130M and the first heavily doped portion 110hd (or the second heavily doped portion 120hd), when etching the third semiconductor material layer 130M in order to expose part of the first heavily doped portion 110hd and part of the second heavily doped portion 120hd, it is easy to damage or even break the film of the underlying heavily doped portion, resulting in the failure of the electrical connection between the subsequently formed source SE, drain DE, source SE' and drain DE' and the heavily doped portion.

[0068] Therefore, by providing the aforementioned first etch protection pattern 161 and second etch protection pattern 162A, damage to the heavily doped portion from the etchant can be prevented during the etching of the third semiconductor material layer 130M. Preferably, the materials of the first etch protection pattern 161 and the second etch protection pattern 162A may include silicon oxide (SiO) or silicon nitride (SiN). From another perspective, during the etching process of the etch protection pattern, since the etchant has an etching selectivity ratio between the material of the etch protection pattern (e.g., SiO or SiN) and the material of the heavily doped portion (e.g., Si), damage to the heavily doped portion from the etchant can be prevented during the etching process of the etch protection pattern.

[0069] Since the methods for forming the source SE, drain DE, source SE', and drain DE' are similar to the manufacturing method of the vertical thin-film transistor VTFT-A in Figure 4, detailed descriptions can be found in the relevant paragraphs of the foregoing embodiments, and will not be repeated here. Thus, the fabrication of the vertical thin-film transistor VTFT-D and the thin-film transistor TFT in Figure 9 is complete.

[0070] In summary, in one embodiment of the vertical thin-film transistor and its manufacturing method of the present invention, the first semiconductor layer, in addition to the first heavily doped portion, also has an extension portion extending between the sacrificial layer and the substrate. This extension portion prevents the subsequently formed third semiconductor layer from getting trapped in the gap between the sacrificial layer and the first heavily doped portion due to insufficient process precision, thus avoiding the formation of an effective short channel. In other words, it can significantly improve the process margin of the sacrificial layer, thereby enhancing the process and operational stability of the vertical thin-film transistor.

[0071] 10, 10A, 10B, 10C, 10D: Component substrate 100:Substrate 105: Buffer layer 110: First semiconductor layer 110ex: Extended section 110hd: First doped portion 110M: First semiconductor material layer 110Mp1: Part 1 110Mp2: Part Two 110s1, 110s2, 120s: Surface 110t, 115t, 120t: Thickness 115, 115A: Sacrificial Layer 115M: Sacrificial Material Layer 115Ma: First Sub-Sacrificial Material Layer 115Mb: Second Subsacrificial Material Layer 115sw: Sidewall 120, 120A: Second semiconductor layer 120ch: channel 120hd: Second doped portion 121hd: Third doped portion 122hd: Fourth doped portion 120M, 120M”: Second semiconductor material layer 130, 130A: Third semiconductor layer 130M: Third semiconductor material layer 135: Dielectric layer 145: Insulation layer 160M: Etching protective material layer 161: First Etched Protective Pattern 162, 162A: Second etched protective pattern CH: Passage Area DE, DE': drain GE, GE', GE": gate L: Extension length LB: Laser Beam SE, SE': Source SL1: First sub-layer SL2: Second Sublayer TFT: Thin Film Transistor TH1: First contact hole TH2: Second contact hole VTFT, VTFT-A, VTFT-B, VTFT-C, VTFT-D: Vertical thin-film transistors Z: Direction θ: included angle

Claims

1. A vertical thin-film transistor, comprising: A first semiconductor layer is disposed on a substrate and has a first heavily doped portion and an extended portion; A sacrificial layer is disposed on the substrate, the sacrificial layer covering the extension portion and exposing the first heavily doped portion; a second semiconductor layer is disposed on the sacrificial layer and has a second heavily doped portion, wherein the second heavily doped portion overlaps with the extension portion of the first semiconductor layer in a direction perpendicular to the substrate; a third semiconductor layer covers and contacts a portion of the first heavily doped portion, a sidewall of the sacrificial layer, and a portion of the second heavily doped portion; a first gate is disposed on the substrate, wherein the first gate overlaps the second heavily doped portion, the extension portion, and the third semiconductor layer in a direction perpendicular to the substrate; and a source and a drain are disposed on the substrate and electrically connected to the first heavily doped portion and the second heavily doped portion, respectively.

2. The vertical thin-film transistor as described in claim 1, further comprising: A dielectric layer is disposed on the substrate and covers the third semiconductor layer, wherein the first gate is disposed on the dielectric layer and overlaps the first heavily doped portion in the direction perpendicular to the substrate.

3. The vertical thin-film transistor as claimed in claim 2, wherein the thickness of the sacrificial layer is greater than or equal to twice the thickness of the first heavily doped portion or the second heavily doped portion.

4. The vertical thin-film transistor as described in claim 2, further comprising: A first etch protection pattern is disposed between the first heavily doped portion and the third semiconductor layer, and contacts the first heavily doped portion and the third semiconductor layer; and a second etch protection pattern is disposed between the second heavily doped portion and the third semiconductor layer, and contacts the second heavily doped portion and the third semiconductor layer, wherein the source electrode penetrates the third semiconductor layer and the first etch protection pattern to electrically connect the first heavily doped portion, and the drain electrode penetrates the third semiconductor layer and the second etch protection pattern to electrically connect the second heavily doped portion.

5. The vertical thin-film transistor as claimed in claim 4, wherein the source is electrically connected to the first heavily doped portion via a first contact hole, the drain is electrically connected to the second heavily doped portion via a second contact hole, and the projections of the first contact hole and the second contact hole onto the substrate along the direction perpendicular to the substrate are located within the projections of the first etch protection pattern and the second etch protection pattern onto the substrate along the direction perpendicular to the substrate.

6. The vertical thin-film transistor as claimed in claim 1, wherein the sacrificial layer has a first sublayer and a second sublayer, and the first gate is sandwiched between the first sublayer and the second sublayer.

7. The vertical thin-film transistor as claimed in claim 6, wherein the thickness of the sacrificial layer is greater than or equal to twice the thickness of the first heavily doped portion or the second heavily doped portion.

8. The vertical thin-film transistor as described in claim 6, further comprising: A first etch protection pattern is disposed between the first heavily doped portion and the third semiconductor layer, and contacts the first heavily doped portion and the third semiconductor layer; and a second etch protection pattern is disposed between the second heavily doped portion and the third semiconductor layer, and contacts the second heavily doped portion and the third semiconductor layer, wherein the source electrode penetrates the third semiconductor layer and the first etch protection pattern to electrically connect the first heavily doped portion, and the drain electrode penetrates the third semiconductor layer and the second etch protection pattern to electrically connect the second heavily doped portion.

9. The vertical thin-film transistor of claim 8, wherein the source is electrically connected to the first heavily doped portion via a first contact hole, the drain is electrically connected to the second heavily doped portion via a second contact hole, and the projections of the first contact hole and the second contact hole onto the substrate along the direction perpendicular to the substrate lie within the projections of the first etch protection pattern and the second etch protection pattern onto the substrate along the direction perpendicular to the substrate.

10. The vertical thin-film transistor as claimed in claim 6, further comprising: A dielectric layer is disposed on the substrate and covers the third semiconductor layer; A second gate is disposed on the dielectric layer and overlaps the first heavily doped portion, the second heavily doped portion, the extension portion and the third semiconductor layer in the direction perpendicular to the substrate.

11. The vertical thin-film transistor of claim 1, wherein the extension of the first semiconductor layer has a surface connected to the sacrificial layer, and the angle between the sidewall of the sacrificial layer and the surface of the extension is less than 60 degrees.

12. A method for manufacturing a vertical thin-film transistor, comprising: A first semiconductor material layer is formed on a substrate; A sacrificial layer is formed on the first semiconductor material layer, the sacrificial layer covering a first portion of the first semiconductor material layer and exposing a second portion of the first semiconductor material layer; a second semiconductor material layer is formed on the sacrificial layer; a heavy doping process is performed on the second portion of the first semiconductor material layer and the second semiconductor material layer; after the heavy doping process is completed, a third semiconductor layer is formed on the first semiconductor material layer and the second semiconductor material layer; a laser annealing process is performed on the first semiconductor material layer and the second semiconductor material layer, wherein after the heavy doping process and the laser annealing process, the first portion and the second portion of the first semiconductor material layer respectively form an extension portion and a first heavily doped portion of the first semiconductor material layer, and the second semiconductor material layer forms a second heavily doped portion of the second semiconductor material layer; a gate is formed on the substrate; and a source and a drain are formed to electrically connect the first heavily doped portion and the second heavily doped portion, respectively.

13. A method for manufacturing a vertical thin-film transistor as claimed in claim 12, wherein the laser annealing process is performed after the heavy doping process, and the step of forming the third semiconductor layer includes: Form a third semiconductor material layer; And perform the laser annealing process on the third semiconductor material layer.

14. A method for manufacturing a vertical thin-film transistor as claimed in claim 12, wherein the laser annealing process precedes the heavy doping process, and the step of forming the third semiconductor layer includes: Form a third semiconductor material layer; And perform another laser annealing process on the third semiconductor material layer.

15. The method for manufacturing a vertical thin-film transistor as described in claim 12, further comprising: A dielectric layer is formed to cover the third semiconductor layer, wherein the gate is formed on the dielectric layer.

16. A method for manufacturing a vertical thin-film transistor as claimed in claim 12, wherein the step of forming the sacrificial layer includes: A first sub-sacrificial material layer and a second sub-sacrificial material layer are sequentially formed on the first semiconductor material layer, wherein the gate is formed after the formation of the first sub-sacrificial material layer and before the formation of the second sub-sacrificial material layer; and a patterning process is performed on the first sub-sacrificial material layer and the second sub-sacrificial material layer to form a first sub-layer and a second sub-layer of the sacrificial layer.

17. The method for manufacturing a vertical thin-film transistor as described in claim 12, further comprising: Before forming the third semiconductor layer, a first etch protection pattern and a second etch protection pattern are formed on the first semiconductor material layer and the second semiconductor material layer, respectively.

18. A method for manufacturing a vertical thin-film transistor as claimed in claim 17, wherein the first etch protection pattern and the second etch protection pattern are formed after the heavy doping process is completed.

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