Sic device with vertical field plates and method of manufacturing the same

Abstract

A SiC device with vertical field plates, including a SiC substrate, a SiC drift region on the front surface of the SiC substrate, multiple field plates within the SiC drift region, wherein the field plates are stacked in the vertical direction and separated by an insulating layer, a gate within the SiC drift region and exposed from the surface of the SiC drift region, the gate being positioned above the field plates and overlapping the field plates in the vertical direction, a source electrode on the SiC drift region, and a drain electrode on the back surface of the SiC substrate.

Description

[Technical Field]

[0001] This invention generally relates to a silicon carbide (SiC) element, and more specifically, to a silicon carbide element having a vertical field plate and a method for manufacturing the same. [Previous Technology]

[0002] Silicon carbide (SiC) is a wide-bandgap third-generation semiconductor material. Compared with silicon, it has better physical and chemical properties, such as high power, high switching frequency, low switching loss, high temperature resistance, high breakdown voltage, and high current density. Therefore, it can be widely used in electronic systems that require high frequency, high power density, and high reliability, including power conversion systems for electric vehicles, power converters such as inverters, chargers and uninterruptible power supplies, energy management systems, and industrial drive systems. It plays an increasingly important role in high-performance electronic devices.

[0003] Metal-oxide-semiconductor field-effect transistors (SiC MOSFETs, hereinafter referred to as such) made of silicon carbide are expected to replace commonly used insulated-gate bipolar transistors (IGBTs) power devices. Besides offering high voltage withstand capability, high-frequency drive, and low on-resistance, they can significantly reduce switching losses and facilitate chip miniaturization. However, despite these advantages, SiC MOSFETs have poor resistance to electrostatic discharge (ESD) and short circuits. This is partly due to the small chip area and high current density of SiC MOSFETs, which results in excessively high electric fields at the gate during operation, causing the gate oxide layer at the interface to easily degrade and fail, leading to reliability issues. Therefore, those skilled in the art need to further improve the structure of SiC MOSFETs to solve these problems. [Summary of the Invention]

[0004] In view of the problems encountered in the aforementioned prior art, the present invention proposes a novel silicon carbide element, characterized by having multiple vertical field plates below the gate, which can change the electric field distribution in this area, thereby reducing the electric field peak at the gate edge, thereby improving the breakdown voltage (VBD) performance of the silicon nitride element and increasing the reliability of the element.

[0005] One aspect of the present invention is to provide a silicon carbide element having vertical field plates, comprising: a silicon carbide substrate having a front side and a back side; a silicon carbide drift region located on the front side of the silicon carbide substrate; a plurality of field plates located in the silicon carbide drift region, the plurality of field plates being stacked in a vertical direction and separated by an insulating layer; a gate located in the silicon carbide drift region and exposed from the surface of the silicon carbide drift region, the gate being located above the field plates and overlapping the field plates in the vertical direction; a source electrode located on the silicon carbide drift region; and a drain electrode located on the back side of the silicon carbide substrate.

[0006] Another aspect of the present invention is to provide a method for manufacturing a silicon carbide element having a vertical field plate, comprising: providing a silicon carbide substrate; forming a first silicon carbide drift region material layer on the front side of the silicon carbide substrate; forming a stacked structure on the first silicon carbide drift region material layer, the stacked structure being formed by alternating stacking of a plurality of field plate material layers and a plurality of first insulating material layers; forming a gate material layer on the stacked structure; and performing a photolithography process to pattern the gate material layer and the stacked structure. Thus, the gate material layer becomes a gate and the field plate material layers become multiple field plates; a conformal second insulating material layer is formed on the gate, the field plates, and the first silicon carbide drift region material layer; a second silicon carbide drift region material layer is formed on the second insulating material layer, the second silicon carbide drift region material layer and the first silicon carbide drift layer together constitute a silicon carbide drift region; and a source electrode is formed on the silicon carbide drift region and the gate, and a drain electrode is formed on the back side of the silicon carbide substrate.

[0007] Such and other objects of the present invention should become more apparent to the reader after reading the detailed description of the preferred embodiments described below with various illustrations and drawings.

Implementation Method

[0008] Exemplary embodiments of the present invention will now be described in detail below, with reference to the accompanying drawings illustrating the described features to enable the reader to understand and achieve the technical effects. The reader will understand that the descriptions herein are by way of illustration only and are not intended to limit the scope of the invention. Various embodiments of the invention and various non-conflicting features thereof can be combined or rearranged in various ways. Modifications, equivalents, or improvements to the invention will be understood by those skilled in the art without departing from the spirit and scope of the invention, and are intended to be included within the scope of the invention.

[0009] The reader should readily understand that the meanings of "on," "above," and "above" in this case should be interpreted broadly, so that "on" not only means "directly on" something, but also includes the meaning of being "on" something with an intervening feature or layering structure. Furthermore, "above" or "above" not only means "above" or "above" something, but also includes the meaning of being "above" or "above" something without an intervening feature or layering structure (i.e., directly on something). In addition, for ease of description, spatially related terms such as "below," "under," "lower part," "above," and "upper part" may be used herein to describe the relationship between one element or feature and one or more other elements or features, as shown in the accompanying drawings.

[0010] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a extent smaller than that of the structure below or above. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any opposing horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along an inclined surface. A substrate may be a layered structure, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0011] Readers can generally understand the terminology used in this invention at least in part from its usage in the context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a," "an," "the," or "described" can also be understood to convey either a singular or a plural usage. In addition, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but can allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0012] Readers will better understand that when words such as "comprising" and / or "containing" are used in this specification, they expressly define the presence of the stated features, areas, wholes, steps, operations, elements and / or components, but do not preclude the possibility of the presence or addition of one or more other features, areas, wholes, steps, operations, elements, components and / or combinations thereof.

[0013] The text uses designations such as "N" and "P," generally referring to donor and acceptor dopants that promote electron and hole transport, such as P-type boron (B) atoms or N-type phosphorus (P) and arsenic (As) atoms. A dopant type suffixed with "++" indicates that its doping concentration is higher than that of dopants suffixed with "+". Conversely, a dopant type suffixed with "-" indicates that its doping concentration is lower than that of dopants without a suffix.

[0014] First, please refer to Figure 1, which is a cross-sectional schematic diagram of a trench gate silicon carbide (SiC) element 100 according to an embodiment of the present invention. The silicon carbide element 100 of the present invention may be a SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), but is not limited thereto. As shown in Figure 1, the silicon carbide element 100 includes a substrate 102 as the basis for setting the components to be formed thereon. In the embodiment of the present invention, the substrate 102 is made of silicon carbide (SiC), such as a 6-inch or 8-inch 4H-SiC substrate with a thickness of approximately 175 μm, wherein it may be heavily doped (N+) with N-type dopants, such as phosphorus (P) or arsenic (As), with a doping concentration of approximately 1 × 10¹⁹ cm⁻³, to improve conductivity, reduce drain contact resistance, and adjust its band gap. A drain electrode D is provided on the back side of the substrate 102, which is in direct contact with the substrate 102 to output current to an operating voltage VDD. The drain electrode D can be made of a metal with high conductivity, such as aluminum (Al), nickel (Ni), titanium (Ti), or gold (Au). On the other hand, a drift region 104 is formed on the front side of the substrate 102. This drift region can also be made of silicon carbide and is grown on the surface of the silicon carbide substrate 102 through an epitaxial growth process, with a thickness of approximately 12 μm. The drift region 104 may be lightly doped with N-type dopant, with a doping concentration of approximately 1 × 10¹⁶ cm⁻³. The thickness and doping concentration of the drift region 104 partially determine the cutoff voltage of the device. A lower doping concentration reduces the probability of carrier recombination, ensuring that carriers in the device can effectively move and drift under the influence of an electric field, thereby maintaining a high current density under high voltage conditions. It should be noted that in some embodiments, one or more buffer layers (not shown) may be formed between the drift region 104 and the substrate 102 to alleviate stress and improve crystal quality. On the other hand, a current distribution layer (between the body region 106, not shown) may also be formed on the drift region 104, such as a doped layer (N) with a higher doping concentration than the drift region 104, so as to uniformly distribute the current laterally to the horizontal cross section of the substrate and reduce the on-resistance during operation.

[0015] Referring again to Figure 1. In this embodiment of the invention, a body region 106 is formed on the drift region 104, which can be formed by moderately doping the silicon carbide region with P-type doping (P), such as doping with boron (B) dopant, with a doping concentration of approximately 1 × 10¹⁸ cm⁻³ and a depth of 0.7 μm. The P-type body region 106 helps to more effectively control the conduction and current flow of the N-type SiC MOSFET device channel, avoid or reduce reverse current, and adjust the threshold voltage and performance of the device to avoid unnecessary voltage deviation. Furthermore, in this embodiment, a source doped region 108 and a contact doped region 110 are also formed on the body region 106. The source doped region 108 can be formed by heavily doping the body region 106 with N-type doping (N+), such as doping with nitrogen (N) dopant, with a doping concentration of approximately 1 × 10¹⁹ cm⁻³, which is greater than the doping concentration of the drift region 104, and a depth of 0.2 μm. The source doped region 108 serves as the current input terminal of the substrate and can be connected to a reference voltage VSS, such as ground, through the source electrode S. The contact doped region 110 is formed on the outer side of the source doped region 108 in the first direction D1, directly contacting the source doped region 108. It can be formed by heavily doping the body region 106 with P-type (P+), such as by doping with boron (B) or aluminum (Al), with a doping concentration of approximately 5 × 10¹⁹ cm⁻³, greater than the doping concentration of the body region 106. Its depth can be 0.3 μm, preferably greater than the depth of the source doped region 108, to confine the source doped region 108. In this embodiment, the contact doped region 110 and the source doped region 108 are both connected to the reference voltage VSS, which can fix each source doped region 108 at the same source potential. The pitch of the entire component in the first direction D1 can be 14 μm.

[0016] Referring again to Figure 1. In this embodiment of the invention, the silicon carbide element 100 further includes a gate G and a plurality of field plates 112 formed on the drift region 104. More specifically, the gate G and the field plates 112 overlap in the vertical direction, preferably completely overlapping and aligned in the vertical direction. The gate G passes through the upper source doped region 108 and the body region 106 to enter the drift region 104, the field plates 112 are located in the drift region 104 below the gate G, and the aforementioned source doped region 108 and body region 106 are located around the gate G or on both sides in the first direction D1. In this embodiment, an insulating layer 114 electrically isolates the gate G and each field plate 112 from each other. The insulating layer 114 also electrically isolates the gate G and each field plate 112 from surrounding layer structures such as the drift region 104, the source doped region 108, and the body region 106. The insulating layer 114 can be made of silicon oxide, such as TEOS (Tetraethyl Orthosilicate), but is not limited thereto. The insulating layer 114 adjacent to the gate G can also be referred to as the gate insulating layer. Preferably, the top surfaces of the gate G, the insulating layer 114, the source doped region 108, and the contact doped region 110 are flush. In this invention, the presence of the field plate 112 located directly below the gate G helps to change the electric field distribution in that area, thereby reducing the electric field peak near the gate edge. The more field plates 112 are provided, the more the electric field peak decreases, up to 1 / 3 of the inherent value. This can improve the breakdown voltage (VBD) performance of the silicon nitride device and increase the reliability of the device.

[0017] Furthermore, in this embodiment of the invention, an interlayer insulating layer 116 is formed above the gate G and the source doped region 108. This interlayer insulating layer is located between the source electrode S and the gate G and the source doped region 108, covering a portion of the source doped region 108. The interlayer insulating layer 116 electrically isolates the gate G from the upper source electrode S, and its material can be silicon oxide. A contact can pass through the interlayer insulating layer 116 to contact the gate G (not shown in this section). The source electrode S is disposed on the interlayer insulating layer 116, directly contacting the source doped region 108 and the contact doped region 110, but electrically isolated from the gate G by the interlayer insulating layer 116. The material of the source electrode S can be the same as that of the drain electrode D, using a metal with high conductivity, such as aluminum (Al), nickel (Ni), titanium (Ti), or gold (Au). The source electrode S is connected to a reference voltage VSS, such as ground voltage. In a trench gate structure, the sidewall of the gate trench below the substrate serves as the channel Ch for the component. Thus, for the same on-resistance (RON), the trench gate requires a smaller component area compared to a planar gate structure, which is beneficial for component miniaturization and practical applications.

[0018] Having described the structure of the silicon carbide element 100 of the present invention above, the following embodiments will describe the fabrication process of the silicon carbide element of the present invention in sequence with reference to Figures 2 to 8. These figures will show the evolution and formation of the various components and features of the silicon carbide element 100 of the present invention during the fabrication process in the form of cross-sectional views. It should be noted that the fabrication processes of the various doped regions mentioned above will be omitted in these figures to avoid obscuring the focus of the present invention.

[0019] First, please refer to Figure 2. At the beginning of the process, a substrate 102 is provided as the basis for setting up the silicon carbide element of the present invention. In this embodiment, the substrate 102 is made of silicon carbide (SiC), such as a 6-inch or 8-inch 4H-SiC substrate, with a thickness of approximately 175 μm. It may be heavily doped (N+) with N-type dopants, such as phosphorus (P) or arsenic (As), at a doping concentration of approximately 1 × 10¹⁹ cm⁻³, to improve conductivity, reduce drain contact resistance, and adjust its bandgap. After the substrate 102 is prepared, an epitaxial layer serving as the drift region material layer 104a is formed on the substrate 102 through an epitaxial process. The drift region material layer 104a may also be made of silicon carbide, with a thickness of approximately 12 μm. It may be lightly doped with N-type dopants, at a doping concentration of approximately 1 × 10¹⁶ cm⁻³, to determine the cutoff voltage of the element. After the drift region material layer 104a is formed, a stacked structure 115 consisting of an alternating insulating material layer 114a and a field plate material layer 112a is then formed on the drift region material layer 104a. These insulating material layers 114a and field plate material layers 112a can be formed through a suitable deposition process, such as low-pressure chemical vapor deposition (LPCVD) or plasma-assisted chemical vapor deposition (PECVD), and their thickness can be 40 nm. The materials can be TEOS and heavily N-type doped polycrystalline silicon (N+), respectively, and are not limited thereto. In this embodiment, the uppermost layer of the stacked structure 115 must be an insulating material layer 114a to insulate it from the upper gate material layer 118 and the lower drift region material layer 104a. After the stacked structure 115 is formed, the gate material layer 118 is then formed on the stacked structure 115. The gate material layer 118 can be made of the same material as the field plate material layer 112a, such as heavily doped N-type polycrystalline silicon (N+), with a thickness of about 1 μm, which can be formed by LPCVD or PECVD.

[0020] Please refer to Figure 3. After the stacked structure 115 and the gate material layer 118 are formed, a photolithography process P is then performed to remove portions of the gate material layer 118 and the stacked structure 115, thus defining the gate G and field plate 112 of the device. More specifically, this step first forms a photoresist (not shown) with a gate pattern on the gate material layer 118, and then uses the photoresist as an etching mask to perform an anisotropic etching process to remove the gate material layer 118 and the stacked structure 115 that are not covered by the photoresist until the underlying drift region material layer 104a is exposed. In this way, the formed gate G and field plate 112 will overlap in the vertical direction, preferably completely overlap, and the gate G and field plate 112, as well as each field plate 112, will be isolated by an insulating material layer 114a.

[0021] Please refer to Figure 4. After the gate G and field plate 112 are formed, another conformal insulating material layer 114b is formed on the stacked structure 115 consisting of the gate G, field plate 112, and insulating material layer 114a. The insulating material layer 114b is distributed along the surface of the gate G, the stacked structure 115, and the drift region material layer 104a. It can be formed by LPCVD or PECVD processes and has a thickness of approximately 40 nm. The insulating material layer 114b can isolate the gate G and the stacked structure 115 from the subsequently formed drift region, body region, and source doped region in the device.

[0022] Please refer to Figure 5. After the insulating material layer 114b is formed, in order to expose the covered drift region material layer 104a, an etching process is performed to remove the insulating material layer 114b on the process plane, so that the drift region material layer 104a and the top surface of the gate G are exposed. The insulating material layer 114b located on the gate G and the sidewall of the stacked structure 115 remains unchanged. The aforementioned insulating material layer 114a and insulating material layer 114b can be regarded together as the insulating layer 114 of the device, wherein the insulating material layer 114a can serve as the interlayer insulating layer of the stacked structure, and the insulating material layer 114b serves as the gate insulating layer.

[0023] Please refer to Figure 6. After the top surface of the drift region material layer 104a and the gate G is exposed, another drift region material layer 104b is formed on the drift region material layer 104a. The drift region material layer 104b can be formed through the same epitaxial process as the drift region material layer 104a, and it can also be made of silicon carbide, lightly doped with N-type dopant (N-), with a doping concentration of approximately 1 × 10¹⁶ cm⁻³. Then, a chemical mechanical planarization (CMP) process is performed to remove the drift region material layer 104b located on the gate G, thus exposing the gate G and making the top surfaces of the drift region material layer 104b, the gate G, and the insulating layer 114 flush. In this embodiment of the invention, the drift region material layer 104a and the drift region material layer 104b together constitute the drift region 104 of the silicon carbide element of the present invention. The aforementioned gate G, field plate 112, and insulating layer 114 are located in the trench of drift region 104.

[0024] Please refer to Figure 7. After the drift region 104 is formed, a multi-pass ion doping process is then performed to form doped regions such as the body region 106, the source doped region 108, and the contact doped region 110 on the drift region 104. Taking an N-type silicon nitride MOSFET device as an example, the body region 106 can be formed by performing moderate P-type doping (P) on the surface of the drift region 104, such as doping with boron (B) dopant, with a doping concentration of approximately 1 × 10¹⁸ cm⁻³ and a depth of 0.7 μm. The source doped region 108 can be formed by performing heavy N-type doping (N+) on the aforementioned body region 106, such as doping with nitrogen (N) dopant, with a doping concentration of approximately 1 × 10¹⁹ cm⁻³, which is greater than the doping concentration of the drift region 104, and a depth of 0.2 μm. The contact doped region 110 is formed on the outer side of the source doped region 108 in the first direction D1. It is in direct contact with the source doped region 108 and can be formed by heavily doping the aforementioned bulk region 106 with P-type doping (P+), such as doping with boron (B) or aluminum (Al). The doping concentration is about 5×10¹⁹ cm⁻³ and the depth can be 0.3 μm.

[0025] Finally, please refer to Figure 8. After the doped regions such as the body region 106, the source doped region 108, and the contact doped region 110 are formed, an interlayer insulating layer 116 is then formed above the gate G and the source doped region 108. In this embodiment, the interlayer insulating layer 116 covers the gate G and the insulating layer 114, and also covers a portion of the source doped region 108. The interlayer insulating layer 116 is in direct contact with the gate G, the insulating layer 114, and the source doped region 108. The material of the interlayer insulating layer 116 can be silicon oxide, which can be formed by first depositing a silicon oxide layer on the substrate surface and then patterning it through a photolithography process. After the interlayer insulating layer 116 is formed, a source electrode S and a drain electrode D are formed on the interlayer insulating layer 116 and the back surface of the substrate 102, respectively. The source electrode S is in direct contact with the aforementioned source doped region 108 and contact doped region 110, but is electrically isolated from the gate electrode G by the interlayer insulating layer 116. The source electrode S and the drain electrode D can be made of the same material, such as high-conductivity metals like aluminum (Al), nickel (Ni), titanium (Ti), and gold (Au), which can be formed through a PVD process. This completes the fabrication of the silicon carbide element 100 of the present invention. The above description is only a preferred embodiment of the present invention. All equivalent variations and modifications made within the scope of the claims of this invention should be considered within the scope of this invention. [Simplified Explanation of the Diagram]

[0026] Figure 1 is a cross-sectional schematic diagram of a silicon carbide element according to Embodiment 1 of the present invention; and Figures 2 to 8 are cross-sectional schematic diagrams of the manufacturing process of a silicon carbide element according to Embodiment 1 of the present invention. It should be noted that all illustrations in this specification are for illustrative purposes. For clarity and convenience of illustration, the dimensions and proportions of the components in the illustrations may be exaggerated or reduced. Generally, the same reference symbols in the figures are used to indicate corresponding or similar component features in modified or different embodiments.

Claims

1. A silicon carbide element having vertical field plates, comprising: a silicon carbide substrate having a front side and a back side; a silicon carbide drift region located on the front side of the silicon carbide substrate; a plurality of field plates located in the silicon carbide drift region, the plurality of field plates being stacked in a vertical direction and separated by an insulating layer; a gate located in the silicon carbide drift region and exposed from the surface of the silicon carbide drift region, the gate being located above the field plates and overlapping the field plates in the vertical direction; a source electrode located on the silicon carbide drift region; and a drain electrode located on the back side of the silicon carbide substrate.

2. The silicon carbide element with vertical field plates as described in claim 1, wherein the insulating layer is composed of a first insulating material layer and a second insulating material layer, the first insulating material layer being located between the gate and the field plates and between the individual field plates, and the second insulating material layer being located between the gate and the sidewalls of the field plates and the silicon carbide drift region.

3. The silicon carbide element with a vertical field plate as described in claim 1 further includes an interlayer insulating layer located between the gate electrode and the source electrode.

4. The silicon carbide element with a vertical field plate as described in claim 1 further includes a silicon carbide drift region in which the body electrode region is located on both sides of the gate electrode.

5. The silicon carbide device with a vertical field plate as described in claim 4 further includes a source doped region and a contact doped region located on each of the body regions.

6. A silicon carbide element with a vertical field plate as described in claim 4, wherein the silicon carbide substrate is heavily doped with n-type, the silicon carbide drift region is lightly doped with n-type, and the bulk electrode region is moderately doped with p-type.

7. A silicon carbide element with vertical field plates as described in claim 1, wherein the field plates and the gate are made of polycrystalline silicon.

8. A silicon carbide element with a vertical field plate as described in claim 1, wherein the source electrode and the drain electrode are made of aluminum, nickel, titanium or gold.

9. A method for manufacturing a silicon carbide element having vertical field plates, comprising: providing a silicon carbide substrate; forming a first silicon carbide drift region material layer on the front side of the silicon carbide substrate; forming a stacked structure on the first silicon carbide drift region material layer, the stacked structure being formed by alternating stacking of a plurality of field plate material layers and a plurality of first insulating material layers; forming a gate material layer on the stacked structure; performing a photolithography process to pattern the gate material layer and the stacked structure, such that the gate material layer becomes a gate and the field plate material layers become a plurality of field plates; forming a conformal second insulating material layer on the gate, the field plates, and the first silicon carbide drift region material layer; A second silicon carbide drift region material layer is formed on the second insulating material layer, the second silicon carbide drift region material layer and the first silicon carbide drift region material layer together constitute a silicon carbide drift region; and a source electrode is formed on the silicon carbide drift region and the gate electrode, and a drain electrode is formed on the back side of the silicon carbide substrate.

10. The method for manufacturing a silicon carbide element with a vertical field plate as described in claim 9 further includes performing an etching process after the formation of the second insulating material layer to remove the second insulating material layer on the process plane, leaving only the second insulating material layer located on the sidewalls of the gate, the field plates, and the first insulating material layers, such that the second insulating material layer and the first insulating material layers together constitute an insulating layer.

11. The method for manufacturing a silicon carbide element with a vertical field plate as described in claim 9 further includes performing a chemical mechanical planarization process after the formation of the second silicon carbide drift region material layer to remove the second silicon carbide drift region material layer located on the gate, so that the top surfaces of the second silicon carbide drift region material layer, the gate, and the insulating layer are flush.

12. The method for manufacturing a silicon carbide element with a vertical field plate as described in claim 9 further includes performing an ion implantation process after the silicon carbide drift region is formed, thereby forming a bulk electrode region on the silicon carbide drift region.

13. The method for manufacturing a silicon carbide element with a vertical field plate as described in claim 12 further includes, after the silicon carbide drift region is formed, performing an ion implantation process to form a source doped region and a contact doped region on each of the body regions.

14. The method for manufacturing a silicon carbide element with a vertical field plate as described in claim 9 further includes forming an inter-insulating layer on the gate electrode before the source electrode is formed.

Images