Semiconductor structure and method of manufacturing the same

Abstract

A method includes providing a structure including a stack of alternating channel layers and interposers, an oxide layer over the stack, a dummy electrode over the oxide layer, a source / drain feature connected to the stack, a contact etch stop layer (CESL) along a top surface of the source / drain feature, an interlayer dielectric (ILD) layer over the CESL. The method further includes removing the dummy electrode to form an opening, forming a mask layer in the opening and over the CESL and the ILD layer, patterning the mask layer to remove the mask layer from the opening, performing a first etch process to remove a portion of the oxide layer, performing a second etch process to remove a portion of a topmost channel layer, removing a remainder of the mask layer, the interposers, and the oxide layer, and forming a gate structure in the opening and wrapping around lower channel layers.

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