Preparation method of hybrid transistors
TW202642856APending Publication Date: 2026-10-16薛英家
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Patent Information
- Application Number
- TW114114012
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-04-14
- Publication Date
- 2026-10-16
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Abstract
A hybrid transistor and its fabrication method are disclosed. The fabrication method is used to prepare a hybrid transistor comprising a low-temperature polycrystalline silicon thin-film transistor and an oxide thin-film transistor on a substrate. The method mainly involves using a photomask design to allow the photoresist formed on the surface of the second insulating layer to have different thicknesses in the areas corresponding to the first and second gates and the areas where the source metal / drain metal is to be formed subsequently. This allows for the formation of contact windows and vias for the source metal and drain metal of the low-temperature polycrystalline silicon thin-film transistor and the oxide thin-film transistor by different etching processes, thereby effectively simplifying the overall fabrication steps.
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