Method for forming a contact and semiconductor cluster tool

Abstract

Disclosed herein are approaches for integrated processes for forming logic and memory devices using monolayer doping with integrated metal contact deposition for low-temperature reduction of contact resistance. Methods may include performing a plasma treatment on a semiconductor substrate to remove a residue layer along an exposed surface of the semiconductor substrate, forming a dopant-containing layer over the exposed surface, and forming a contact by forming one or more metal layers over the exposed surface.

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