Integrated chip and method of manufacturing the same

Abstract

An integrated chip includes a barrier layer including a first conductive material over a semiconductor substrate. The integrated chip includes a lower electrode layer including a second conductive material, different than the first conductive material, over the barrier layer. The integrated chip includes a dielectric layer over the lower electrode layer. The integrated chip includes an upper electrode layer over the dielectric layer. The integrated chip includes an encapsulation layer including a first dielectric material encapsulating the upper electrode layer, the dielectric layer, the lower electrode layer, and the barrier layer. The integrated chip includes a spacer layer including a second dielectric material, different than the first dielectric material, on an upper surface of the barrier layer. The encapsulation layer is spaced from sidewalls of the lower electrode layer, sidewalls of the dielectric layer, and sidewalls of the upper electrode layer by the spacer layer.

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