Chip on film package structure

Abstract

A chip on film package structure includes a flexible circuit substrate and a chip. A plurality of the leads of the flexible circuit substrate include a plurality of first inner leads and a plurality of second inner leads. The chip includes a plurality of first bumps, a plurality of second bumps and a plurality of third bumps. The second bumps are located on two opposite sides of the third bumps. Each of the first bumps corresponds to at least one of the third bumps. Each of the first inner leads is bonded to one of the first bumps and the corresponding at least one of the third bumps. The second inner leads are bonded to the second bumps respectively. Any two of the adjacent first bumps in either of two outermost groups of the first bumps have a first pitch. Any two of the adjacent second bumps near the outermost group of the first bumps have a second pitch equal to the first pitch.

Description

Technical Field

[0001] This invention relates to a packaging structure, and more particularly to a thin-film flip-chip packaging structure. Prior Technology

[0002] Chip-on-Film (COF) packaging is a packaging technology that uses conductive bumps to bond a chip to leads on a flexible circuit board. Due to the high density and fine pitch of the inner leads (or inner pins) of the flexible circuit board used to electrically connect the conductive bumps, to ensure accurate alignment and bonding between the inner pins and the conductive bumps, a detection device typically captures images of the inner pins and conductive bumps at the corners of the chip for alignment and interpretation during and after the inner pin bonding process. However, when the conductive bumps are far from the chip edge, it becomes more difficult for the detection device to capture images of the inner pins and conductive bumps, making it difficult to observe whether the inner pins and conductive bumps are properly aligned and bonded during and after the inner pin bonding process. In addition, the conductive bumps far from the wafer edge also increase the length of the inner pins connecting the conductive bumps extending into the wafer mounting area. Since the inner pins have a long cantilever section in the wafer mounting area, they are very easy to bend down and contact the seal ring located at the wafer edge without support, which can lead to an electrical abnormal edge touch problem and reduce the yield of the product. Summary of the Invention

[0003] This invention provides a thin-film flip-chip packaging structure, in which the bump configuration helps to confirm alignment and bonding, and also reduces the risk of internal pins bending down and contacting the chip edge, thereby improving product yield and reliability.

[0004] The thin-film flip-chip packaging structure of the present invention includes a flexible circuit carrier and a wafer. The flexible circuit carrier includes a flexible substrate and a plurality of pins. The flexible substrate has a wafer mounting region. The wafer mounting region has a first boundary and a second boundary. The pins are disposed on the flexible substrate and include a plurality of first inner pins and a plurality of second inner pins. The first inner pins and the second inner pins extend through the first boundary into the wafer mounting region. The first inner pins and the second inner pins are arranged adjacent to each other along the first boundary. The second inner pins are located on opposite sides of the first inner pins. The wafer is disposed on the flexible circuit carrier and located within the wafer mounting region. The wafer has a first long side and a second long side and includes a plurality of first bumps, a plurality of second bumps, and a plurality of third bumps. The first long side and the second long side correspond to the first boundary and the second boundary, respectively. The second bumps and the third bumps are adjacent to the first long side and arranged adjacent to each other along the first long side. The second bumps are located on opposite sides of the third bumps. Each first bump corresponds to at least one third bump and is further away from the first long side than the corresponding at least one third bump. Each of these first inner pins engages one of these first bumps with the corresponding at least one third bump. These second inner pins engage the second bumps respectively. The first bumps have two sets of outermost first bumps on opposite sides. Any two adjacent first bumps in any set of the two sets of outermost first bumps have a first spacing. Any two adjacent second bumps adjacent to the set of outermost first bumps have a second spacing. The second spacing is equal to the first spacing.

[0005] In one embodiment of the present invention, the number of first bumps in any one of the two outermost groups of the first bumps is at least three.

[0006] In one embodiment of the present invention, the number of the second bumps in any one of the two adjacent outermost groups of the first bumps is not less than three.

[0007] In one embodiment of the present invention, the wafer has two first corners located at opposite ends of a first long side, and the second bumps are located at the two first corners.

[0008] In one embodiment of the present invention, the wafer has a center line perpendicular to the first long side, and the first bumps and the first inner pins are arranged in a mirror image on both sides of the center line.

[0009] In one embodiment of the invention, the aforementioned first protrusions located on one side of the center line are arranged in at least one row along a direction parallel to a first oblique line. The first oblique line is inclined to the first long side.

[0010] In one embodiment of the invention, each of the first protrusions described above has a first distance perpendicular to the first long side. These first distances between the first protrusions gradually increase from the center line in a direction away from the center line.

[0011] In one embodiment of the invention, each of the aforementioned first protrusions has a second distance perpendicular to the second long side. Some of these first distances of the first protrusions are greater than these second distances.

[0012] In one embodiment of the invention, the aforementioned first bumps are electrically connected to the first internal pins.

[0013] In one embodiment of the present invention, the above-described thin-film flip-chip packaging structure further includes an encapsulating colloid that at least fills the space between the wafer and the flexible circuit carrier and covers the wafer mounting area, the first bumps, the second bumps, and the third bumps.

[0014] Based on the above, in the design of the thin-film flip-chip packaging structure of the present invention, by setting a second bump and a second inner pin at the corner of the chip to simulate the configuration of the outermost first inner pin and the first bump, the detection device or operator can not only determine whether the electrically connected first inner pin and the first bump are accurately aligned during pin bonding, but also confirm whether the actual bonding state of the first inner pin and the first bump has shifted after pin bonding, so as to ensure that the inner pin and the bump are accurately connected, reducing the risk of electrical abnormalities or failures in the thin-film flip-chip packaging structure of the present invention. By setting a third bump corresponding to the first bump on a long side adjacent to the chip, support for the first inner pin can be provided, preventing the first inner pin from bending down and contacting the chip edge, thereby improving the product yield of the thin-film flip-chip packaging structure of the present invention.

[0015] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Simple Explanation of the Diagram

[0016] Figure 1 is a top view schematic diagram of a thin-film flip-chip packaging structure according to an embodiment of the present invention. Figure 2 is an enlarged perspective view of the wafer placement area of ​​the flexible circuit carrier in Figure 1. Figure 3 is a cross-sectional view along line II in Figure 1. Implementation

[0017] The invention is illustrated in the accompanying drawings to provide a more complete picture. However, the invention may be embodied in various different forms and should not be limited to the embodiments described herein. The thickness, dimensions, or sizes of layers or regions in the drawings are enlarged for clarity.

[0018] Figure 1 is a top view of a thin-film flip-chip package structure according to an embodiment of the present invention. Figure 2 is an enlarged perspective view of the wafer mounting area of ​​the flexible circuit carrier in Figure 1. Figure 3 is a cross-sectional view along line II of Figure 1. In Figure 1, the pins covered by the solder mask are omitted, and only the pin layout area is schematically marked. The wafer and encapsulant are drawn in perspective and the bumps are not shown.

[0019] Referring simultaneously to Figures 1, 2, and 3, in this embodiment, the thin-film flip-chip package structure 100 includes a flexible circuit carrier 110 and a wafer 120. The flexible circuit carrier 110 includes a flexible substrate 112 and a plurality of pins 114. The flexible substrate 112 has a wafer placement region 113. The wafer placement region 113 has a first boundary B1 and a second boundary B2. The pins 114 are disposed on the flexible substrate 112 and include a plurality of first inner pins 115 and a plurality of second inner pins 117. The first inner pins 115 and the second inner pins 117 extend through the first boundary B1 into the wafer placement region 113. The first inner pins 115 and the second inner pins 117 are arranged adjacent to each other along the first boundary B1. The second inner pins 117 are located on opposite sides of the first inner pins 115. The wafer 120 is disposed on the flexible circuit carrier 110 and located within the wafer placement region 113. The chip 120 has a first long side S1 and a second long side S2 and includes a plurality of first bumps 122, a plurality of second bumps 124, and a plurality of third bumps 126. The first long side S1 and the second long side S2 correspond to a first boundary B1 and a second boundary B2, respectively. The second bumps 124 and the third bumps 126 are adjacent to and arranged along the first long side S1. The second bumps 124 are located on opposite sides of the third bumps 126. Each first bump 122 corresponds to at least one third bump 126 and is further away from the first long side S1 than the corresponding at least one third bump 126. Each first inner pin 115 engages one of the first bumps 122 with the corresponding at least one third bump 126. In this embodiment, each first bump 122 corresponds to one third bump 126, and each first inner pin 115 engages one first bump 122 with one corresponding third bump 126, but is not limited thereto. These second inner pins 117 respectively engage with these second bumps 124. These first bumps 122 have two sets of outermost first bumps 122e on opposite sides. Any two adjacent first bumps 122e in any set of the two sets of outermost first bumps 122e have a first spacing D1. Any two adjacent second bumps 124 adjacent to these sets of outermost first bumps 122e have a second spacing D2. The second spacing D2 is equal to the first spacing D1. The first spacing D1 is the shortest distance between the midlines of two adjacent first bumps 122e, and the second spacing D2 is the shortest distance between the midlines of two adjacent second bumps 124. These second bumps 124 may be dummy bumps, and these second inner pins 117 may be dummy leads, meaning that the second bumps 124 and the second inner pins 117 do not have electrical transmission functionality, but this invention does not limit this.

[0020] In detail, in this embodiment, the flexible substrate 112 of the flexible circuit board 110 may be made of, for example, polyethylene terephthalate, polyimide, polyethersulfone, polycarbonate, or other suitable flexible materials. Furthermore, the flexible circuit board 110 of this embodiment also includes a solder resist layer 118 disposed on the flexible substrate 112 and partially covering the pins 114 to prevent damage to the pins 114 or bridging and short-circuiting due to foreign matter. The solder resist layer 118 has an opening exposing the wafer mounting area 113. The portions of the pins 114 exposed by the solder resist layer 118 can be used for electrical connection to the wafer 120 or external components.

[0021] Referring also to Figures 2 and 3, in this embodiment, the chip 120 is disposed in the chip mounting area 113 in a flip-chip manner, with the active surface of which is provided with first bumps 122, second bumps 124, and third bumps 126 facing the flexible circuit carrier 110. These first bumps 122 are electrically connected to the first internal pins 115; that is, the chip 120 is electrically connected to the first internal pins 115 located in the chip mounting area 113 via the first bumps 122. In one embodiment, the chip 120 has a center line L perpendicular to the first long side S1, and the first bumps 122 and the first internal pins 115 are arranged in a mirror image on both sides of the center line L. In another embodiment, the first bumps 122 located on one side of the center line L are arranged in at least one row along a direction parallel to a first oblique line T1, wherein the first oblique line T1 is inclined to the first long side S1. In this embodiment, the first protrusions 122 located on one side (e.g., the left side) of the center line L are arranged in two rows R1 and R2 along a direction parallel to the first oblique line T1, and these first protrusions 122 in these two rows R1 and R2 are staggered, but not limited thereto. In one embodiment, the arrangement of these first protrusions 122 (e.g., the number of rows) can be arranged in a single row or multiple rows depending on the needs and space allowance. Each of these first protrusions 122 has a first distance E1 perpendicular to the first long side S1. The first distance E1 mentioned here is the shortest distance from the center position of the first protrusion 122 to the first long side S1. These first distances E1 of the first protrusions 122 gradually increase from the center line L in the direction away from the center line L, that is, the first distance E1 is the smallest near the center line L, and gradually increases as it moves away from the center line L. Each of these first protrusions 122 has a second distance E2 perpendicular to the second long side S2, and some of these first protrusions 122 have first distances E1 greater than these second distances E2. The second distance E2 described herein is the shortest distance from the center of the first protrusion 122 to the second long side S2. In other words, the first protrusions 122 are closer to the first long side S1 near the center line L, and closer to the second long side S2 the further away from the center line L, i.e., these first protrusions 122 are arranged in an inclined manner.

[0022] Referring again to Figure 2, in one embodiment, the number of first bumps 122e in any one of the two sets of outermost first bumps 122e is at least three. The number of second bumps 124 in any one of the two sets of outermost first bumps 122e is not less than three. The chip 120 has two first corners C located at opposite ends of the first long side S1, and the second bumps 124 are located at the two first corners C. Since the first bumps 122 used by the chip 120 for electrical connection with the flexible circuit board 110 are far from the first long side S1 of the chip 120, it is not easy to observe whether the first internal pins 115 and the first bumps 122 are aligned and engaged when the internal pins are engaged with the bumps and after engagement. Therefore, in this embodiment, second bumps 124 and second internal pins 117 are provided at the two first corners C of the first long side S1 of the chip 120 as alignment marks when the internal pins are engaged with the bumps. Furthermore, the second distance D2 between any two adjacent second bumps 124 is equal to the first distance D1 between any two adjacent first bumps 122e in a group of adjacent outermost first bumps 122e. In other words, the configuration of the outermost first inner pin 115 and the first bump 122e is simulated by the second bump 124 and the second inner pin 117 located at the first corner C. Therefore, by identifying the alignment and engagement of the second bump 124 and the second inner pin 117 located at the first corner C, the detection device or operator can determine whether the first inner pin 115 and the first bump 122 are accurately aligned when the inner pin and the bump are engaged, and confirm whether the actual engagement of the first inner pin 115 and the first bump 122 has shifted after the inner pin and the bump are engaged, so as to ensure that the inner pin and the bump are accurately connected, avoid electrical abnormalities or failures in the thin-film flip-chip package structure 100, and thus improve the reliability of the thin-film flip-chip package structure 100.

[0023] Furthermore, because the first bump 122 is far from the first long side S1 of the wafer 120, the length of the first inner pin 115 extending into the wafer mounting area 113 connected to the first bump 122 increases. This results in a longer cantilever section (i.e., the portion from the rear end of the first bump 122 to the first boundary B1) within the wafer mounting area 113, which could potentially bend downwards and contact the protective ring located at the edge of the wafer 120, thus posing a risk of edge contact. Therefore, in this embodiment, a third bump 126 corresponding to the first bump 122 is provided near the first long side S1 of the wafer 120 to support the first inner pin 115, preventing it from contacting the edge of the wafer 120 and improving the yield of the thin-film flip-chip package structure 100. In short, the third bump 126 can be considered a support bump, without electrical function, serving only as a support structure. These third bumps 126 can be arranged in at least one row along the first long side S1. In this embodiment, the third bumps 126 are arranged in two rows along the first long side S1, and these three rows of third bumps 126 are staggered, but not limited thereto. Furthermore, to ensure pin support and bonding quality, a third spacing D3 between two adjacent third bumps 126 is equal to the first spacing D1. The third spacing D3 mentioned here is the distance between the centerlines of two adjacent third bumps 126.

[0024] Additionally, referring to Figures 1 and 3, the thin-film flip-chip packaging structure 100 of this embodiment may further include an encapsulating colloid 130, which at least fills the space between the wafer 120 and the flexible circuit carrier 110 and covers the wafer mounting area 113, the first bumps 122, the second bumps 124, and the third bumps 126 to protect the electrical contacts between the wafer 120 and the flexible circuit carrier 110. In this embodiment, the encapsulating colloid 130 may be, for example, an underfill, but is not limited thereto.

[0025] In summary, in the design of the thin-film flip-chip packaging structure of the present invention, by setting a second bump and a second inner pin at the corner of the chip to simulate the configuration of the outermost first inner pin and the first bump, the detection device or operator can not only determine whether the electrically connected first inner pin and the first bump are accurately aligned during pin bonding, but also confirm whether the actual bonding state of the first inner pin and the first bump has shifted after pin bonding, thus ensuring accurate connection between the inner pin and the bump and reducing the risk of electrical abnormalities or failures in the thin-film flip-chip packaging structure of the present invention. By setting a third bump corresponding to the first bump on a long side adjacent to the chip, support for the first inner pin can be provided, preventing the first inner pin from bending down and contacting the chip edge, thereby improving the product yield of the thin-film flip-chip packaging structure of the present invention.

[0026] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0027] 100: Thin-film flip-chip packaging structure 110: Flexible Circuit Board 112: Flexible substrate 113: Chip Setup Area 114: Pin 115: First internal pin 117: Second internal pin 118: Solder resist layer 120: Chip 122, 122e: First bump 124: Second bump 126: Third bump 130: Encapsulating colloid B1: First Boundary B2: Second Boundary C: First Corner D1: First spacing D2: Second spacing D3: Third spacing E1: First distance E2: Second distance L: Centerline R1, R2: Row S1: First long side S2: Second longest side T1: First diagonal line

Claims

1. A thin-film flip-chip packaging structure, comprising: A flexible circuit board includes: a flexible substrate having a wafer placement area having opposing first boundaries and a second boundary; and a plurality of pins disposed on the flexible substrate and including a plurality of first inner pins and a plurality of second inner pins, the first inner pins and the second inner pins extending through the first boundary into the wafer placement area, the first inner pins and the second inner pins being arranged adjacently along the first boundary, and the second inner pins being located on opposite sides of the first inner pins; and a wafer disposed on the flexible circuit board and located within the wafer placement area, the wafer having opposing first long sides and A second long side includes a plurality of first bumps, a plurality of second bumps and a plurality of third bumps, the first long side and the second long side respectively corresponding to the first boundary and the second boundary, the second bumps and the third bumps being adjacent to the first long side and arranged adjacently along the first long side, the second bumps being located on opposite sides of the third bumps, each first bump corresponding to at least one third bump and being farther away from the first long side than the corresponding at least one third bump, wherein each of the first inner pins engages one of the first bumps with the corresponding at least one third bump, and the second inner pins are respectively engaged with the second bumps; The first bumps have two sets of outermost first bumps on opposite sides. Any two adjacent first bumps in any set of the two sets of outermost first bumps have a first spacing. Any two adjacent second bumps adjacent to the set of outermost first bumps have a second spacing, and the second spacing is equal to the first spacing. The wafer has two first corners located at opposite ends of the first long side. The second bumps are located at the two first corners, and the third bumps do not have electrical functions.

2. The thin-film flip-chip packaging structure as claimed in claim 1, wherein the number of the first bumps in any one of the two outermost groups of the first bumps is at least three.

3. The thin-film flip-chip packaging structure as claimed in claim 2, wherein the number of the second bumps adjacent to either of the two sets of outermost first bumps is not less than three.

4. The thin-film flip-chip package structure as claimed in claim 1, wherein the wafer has a center line perpendicular to the first long side, and the first bumps and the first internal pins are arranged in a mirror image on both sides of the center line.

5. The thin-film flip-chip packaging structure as claimed in claim 4, wherein the first bumps located on one side of the centerline are arranged in at least one row along a direction parallel to a first oblique line, wherein the first oblique line is inclined to the first long side.

6. The thin-film flip-chip packaging structure as claimed in claim 4, wherein each of the first bumps has a first distance perpendicular to the first long side, and the first distance of the first bumps gradually increases from the center line in a direction away from the center line.

7. The thin-film flip-chip packaging structure as claimed in claim 6, wherein each of the first bumps has a second distance perpendicular to the second long side, and the first distance of some of the first bumps is greater than the second distance.

8. The thin-film flip-chip package structure as claimed in claim 1, wherein the first bumps are electrically connected to the first internal pins.

9. The thin-film flip-chip packaging structure as described in claim 1, further comprising: An encapsulating colloid is at least filled between the chip and the flexible circuit board and covers the chip mounting area, the first bumps, the second bumps and the third bumps.

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