Semiconductor package structure

Abstract

A semiconductor package structure includes a substrate, a chip, at least one conductive post, a molding compound, and at least one semiconductor component. The chip and the conductive post are disposed on the substrate and electrically connected to the substrate. The molding compound is disposed on the substrate and covers the chip and the conductive post. The molding compound has a first surface and a second surface opposite to each other, and at least one accommodating recess. The accommodating recess extends from the first surface toward the second surface and has at least one bottom surface. The bottom surface exposes at least one top surface of the conductive post. The semiconductor component is disposed on the bottom surface of the accommodating recess and contacts the top surface of the conductive post. The semiconductor component is electrically connected to the substrate through the conductive post.

Description

Technical Field

[0001] This invention relates to a packaging structure, and more particularly to a semiconductor packaging structure. Prior Technology

[0002] In existing packaging structures, chips are typically tested before being mounted on a substrate for packaging. However, some active or passive components, such as diodes, capacitors, resistors, and other semiconductor devices, are directly mounted on the substrate for packaging without testing. When these semiconductor devices are damaged or require electrical adjustments, the entire package must be destroyed to remove and replace them. However, this rework process is extremely difficult and can easily damage the chip and its associated electrical components. Summary of the Invention

[0003] This invention provides a semiconductor packaging structure that is easy to rework and can improve the reusability of products.

[0004] The semiconductor packaging structure of the present invention includes a substrate, a wafer, at least one conductive pillar, an encapsulating agent, and at least one semiconductor device. The wafer is disposed on the substrate and electrically connected to the substrate. At least one conductive pillar is disposed on the substrate and electrically connected to the substrate. The encapsulating agent is disposed on the substrate and covers the wafer and at least one conductive pillar. The encapsulating agent has a first surface and a second surface opposite to each other, and at least one receiving groove. The second surface contacts the substrate, and the at least one receiving groove extends from the first surface to the second surface and has at least one bottom surface. The at least one bottom surface exposes at least one top surface of the at least one conductive pillar. At least one semiconductor device is disposed on at least one bottom surface of the at least one receiving groove and contacts at least one top surface of the at least one conductive pillar. The at least one semiconductor device is electrically connected to the substrate through the at least one conductive pillar.

[0005] In one embodiment of the present invention, the above-described semiconductor packaging structure further includes a cover plate disposed in at least one receiving groove to cover at least one semiconductor element.

[0006] In one embodiment of the present invention, the cover plate is an insulating material, and the material of the cover plate includes glass, plastic, ceramic or glass fiber.

[0007] In one embodiment of the present invention, the semiconductor packaging structure further includes an adhesive material disposed around the cover plate and between the cover plate and the inner wall of at least one receiving groove. The cover plate is fixed to the at least one receiving groove by the adhesive material.

[0008] In one embodiment of the present invention, the adhesive material described above includes an ultraviolet (UV) depolymerizer or a thermal release tape.

[0009] In one embodiment of the present invention, the above-described semiconductor packaging structure further includes an insulating adhesive material that fills at least one receiving groove and completely covers at least one semiconductor element.

[0010] In one embodiment of the present invention, the above-mentioned insulating adhesive material includes an ultraviolet degradable adhesive, a pyrolytic adhesive film, an epoxy resin, or an encapsulating compound.

[0011] In one embodiment of the present invention, the above-mentioned wafer is bonded to the substrate by wire bonding or flip-chip bonding.

[0012] In one embodiment of the present invention, the orthographic projection of the at least one semiconductor element on the substrate does not overlap with the orthographic projection of the wafer on the substrate.

[0013] In one embodiment of the present invention, the above-mentioned at least one semiconductor element includes at least one passive element or at least one active element.

[0014] Based on the above, in the semiconductor packaging structure of the present invention, the encapsulating colloid covers the conductive pillars disposed on the substrate and has a receiving groove exposing the top surface of the conductive pillars. The semiconductor element is disposed within the receiving groove and contacts the top surface of the conductive pillars to be electrically connected to the substrate. In other words, the semiconductor element of the present invention is not encapsulated within the encapsulating colloid. With this design, when the semiconductor element is subsequently damaged or requires electrical adjustment of its specifications, the semiconductor element can be quickly removed from the receiving groove for rework, thereby improving product reuse rate.

[0015] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0016] Figure 1A is a schematic cross-sectional view of a semiconductor packaging structure according to an embodiment of the present invention. Figure 1B is a top view of region A in Figure 1A. Figure 2 is a cross-sectional schematic diagram of a semiconductor packaging structure according to another embodiment of the present invention. Figure 3 is a cross-sectional schematic diagram of a semiconductor packaging structure according to another embodiment of the present invention. Figure 4 is a cross-sectional schematic diagram of a semiconductor packaging structure according to another embodiment of the present invention. Implementation

[0017] The embodiments of this invention can be understood in conjunction with the accompanying drawings, which are also considered part of the disclosure. It should be understood that the drawings are not drawn to scale; in fact, the dimensions of the components may be arbitrarily enlarged or reduced to clearly illustrate the features of the invention.

[0018] Figure 1A is a cross-sectional schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention. Figure 1B is a top view of region A of Figure 1A. Referring to both Figures 1A and 1B, in this embodiment, the semiconductor packaging structure 100a includes a substrate 110, a wafer 120, at least one conductive pillar (two conductive pillars 130 are schematically shown in Figure 1A, and four conductive pillars 130 are schematically shown in Figure 1B), an encapsulating colloid 140, and at least one semiconductor element (two semiconductor elements 150 and 152 are schematically shown). The wafer 120 is disposed on the substrate 110 and electrically connected to the substrate 110. The conductive pillar 130 is disposed on the substrate 110 and electrically connected to the substrate 110. The encapsulating colloid 140 is disposed on the substrate 110 and covers the wafer 120 and the conductive pillar 130. The encapsulating colloid 140 has a first surface 141 and a second surface 143 opposite to each other, and at least one receiving groove (one receiving groove 145 is schematically shown). The second surface 143 contacts the substrate 110. A receiving groove 145 extends from the first surface 141 to the second surface 143 and has a bottom surface B. The bottom surface B exposes the top surface 131 of the conductive post 130. Semiconductor elements 150 and 152 are disposed on the bottom surface B of the receiving groove 145 and contact the top surface 131 of the conductive post 130. The semiconductor elements 150 and 152 are electrically connected to the substrate 110 through the conductive post 130, respectively.

[0019] In detail, in this embodiment, the substrate 110 has an upper surface 111 and a lower surface 113 opposite to each other, and includes a plurality of conductive portions 112, 114, and 116. Conductive portions 112 and 114 are disposed on the upper surface 111, while conductive portion 116 is disposed on the lower surface 113. In one embodiment, conductive portions 112 and 114 may be disposed on the upper surface 111, while conductive portion 116 may be disposed on the lower surface 113. In one embodiment, conductive portions 112, 114, and 116 may be, for example, circuits, conductive vias, conductive blind vias, pads, or combinations thereof; as long as they have conductive function, they are all considered conductive portions as described in this disclosure. In one embodiment, the semiconductor package structure 100a can be electrically connected to an external circuit through the conductive portion 116. In one embodiment, the substrate 110 may be, for example, a printed circuit board, an Ajinomoto build-up film (ABF) substrate, a bismalleimide triazine (BT) substrate, or other suitable substrate.

[0020] Referring again to Figure 1A, the chip 120 in this embodiment has an active surface 121 and a back surface 123 facing each other, and includes a plurality of pads 122 disposed on the active surface 121. Here, the chip 120 is disposed on the substrate 110 with the active surface 121 facing upward (i.e., away from the substrate 110). In other words, the chip 120 has its back surface 123 facing the upper surface 111 of the substrate 110. In this embodiment, the semiconductor package structure 100a also includes a die-attach material 125 disposed between the chip 120 and the substrate 110, wherein the chip 120 is fixed to the substrate 110 by means of the die-attach material 125. The die-attach material 125 directly contacts the upper surface 111 of the substrate 110 and the back surface 123 of the chip 120. In one embodiment, the die-attach material 125 is, for example, a die attach film (DAF) or other suitable material. Furthermore, the semiconductor package structure 100a of this embodiment also includes at least one bonding wire (two bonding wires 180 are schematically shown) that electrically connects the pads 122 of the chip 120 to the conductive portion 112 of the substrate 110. That is, the chip 120 of this embodiment is bonded to the substrate 110 by wire bonding.

[0021] Furthermore, in this embodiment, the conductive pillars 130 are disposed around or on one side of the wafer 120, wherein the bottom surface 133 of the conductive pillars 130 is structurally and electrically connected to the conductive portion 114 of the substrate 110. The encapsulating colloid 140 is disposed on the upper surface 111 of the substrate 110, and... The encapsulation 140 covers the upper surface 111, wafer 120, die bonding material 125, wire bonding 180, and conductive pillars 130. Here, a receiving recess 145 of the encapsulation 140 can simultaneously expose the top surfaces 131 of multiple conductive pillars 130. Only the top surface 131 of the conductive pillars 130 is exposed outside the encapsulation 140; the rest is encapsulated within the encapsulation 140. In one embodiment, the conductive pillars 130 are, for example, copper pillars, but are not limited thereto.

[0022] Referring simultaneously to Figures 1A and 1B, in this embodiment, semiconductor elements 150 and 152 are disposed within the same receiving recess 145 and are electrically connected to the substrate 110 via conductive posts 130. Semiconductor elements 150 and 152 are, for example, passive or active elements. In one embodiment, a passive element includes a resistor, capacitor, inductor, or a combination thereof. In one embodiment, an active element includes a transistor, diode, or a combination thereof, but is not limited thereto. Specifically, the orthographic projections of semiconductor elements 150 and 152 onto the substrate 110 do not overlap with the orthographic projection of the wafer 120 onto the substrate 110.

[0023] Furthermore, the semiconductor packaging structure 100a of this embodiment also includes a cover plate 160 disposed within the receiving groove 145 to cover the semiconductor elements 150 and 152, thereby protecting the semiconductor elements 150 and 152. That is, the cover plate 160 can be considered a protective cover. In addition, the semiconductor packaging structure 100a also includes an adhesive material 170 disposed around the cover plate 160 and between it and the inner wall of the receiving groove 145. The cover plate 160 is fixed within the receiving groove 145 by the adhesive material 170. In one embodiment, the top surface 161 of the cover plate 160 may be flush with or slightly lower than the first surface 141 of the encapsulating colloid 140. In one embodiment, the cover plate 160 is specifically embodied as an insulating material, wherein the material of the cover plate 160 is, for example, glass, plastic, ceramic, or fiberglass. In one embodiment, the glass includes colored tempered glass or transparent tempered glass. In one embodiment, the cover plate 160 may also be a coating on the glass surface. In one embodiment, the cover plate 160 may also be a silicon substrate. In one embodiment, the adhesive material 170 is, for example, an ultraviolet (UV) degradable adhesive or a thermal release tape. In one embodiment, the receiving groove 145 may be selectively filled with a filling adhesive and covered by the cover plate 160.

[0024] In this embodiment, semiconductor elements 150 and 152 are not encapsulated together with the wafer within the encapsulating colloid 140, but are separately disposed within the receiving groove 145 of the encapsulating colloid 140. Therefore, when semiconductor elements 150 and 152 are subsequently damaged or require adjustment of their specifications due to electrical needs, the adhesive material 170 can be detached by direct ultraviolet light irradiation or direct heating to remove the cover plate 160 without damaging the encapsulation structure. This allows for rework or replacement of the semiconductor elements 150 and 152 within the receiving groove 145, after which the cover plate 160 can be replaced and the encapsulating colloid (i.e., bonded with adhesive material 170) can be applied again. This embodiment improves product reusability. In short, the semiconductor encapsulation structure 100 of this embodiment is easy to rework, and the process is simple and fast.

[0025] It must be noted that the following embodiments use the component reference numerals and some content from the foregoing embodiments, with the same reference numerals used to represent the same or similar components, and descriptions of the same technical content omitted. For explanations of the omitted parts, please refer to the foregoing embodiments; these will not be repeated in the following embodiments.

[0026] Figure 2 is a cross-sectional schematic diagram of a semiconductor packaging structure according to another embodiment of the present invention. Referring to Figures 1A and 2 simultaneously, the semiconductor packaging structure 100b of this embodiment is similar to the semiconductor packaging structure 100a described above, except that in this embodiment, the encapsulating colloid 140' has two receiving grooves 145 and 147. Semiconductor elements 150 and 152 are respectively located on the bottom surfaces B and B' of the receiving grooves 145 and 147, and are in direct contact and electrically connected to the top surface 131 of the exposed conductive pillars 130 of the corresponding receiving grooves 145 and 147. The cover plate 160 simultaneously covers the semiconductor elements 150 and 152 located in the different receiving grooves 145 and 147, and is fixed to the inner wall of the receiving grooves 145 and 147 by the adhesive material 170.

[0027] Figure 3 is a cross-sectional schematic diagram of a semiconductor packaging structure according to another embodiment of the present invention. Referring simultaneously to Figures 1A and 3, the semiconductor packaging structure 100c of this embodiment is similar to the semiconductor packaging structure 100a described above. The difference is that in this embodiment, the cover plate 160 and adhesive material 170 shown in Figure 1A are not provided. Instead, the semiconductor packaging structure 100c further includes an insulating adhesive 190, which fills the receiving groove 145 and completely covers the semiconductor elements 150 and 152. In one embodiment, the insulating adhesive 190 is, for example, an ultraviolet-degradable adhesive, a thermally degradable adhesive film, an epoxy resin, or an encapsulating compound. When the insulating adhesive 190 is an ultraviolet-degradable adhesive or a thermally degradable adhesive film, the insulating adhesive 190 can be dissociated by irradiation with ultraviolet light or direct heating to replace / repair the semiconductor elements 150 and 152 located in the receiving groove 145. When the insulating material 190 is epoxy resin or encapsulating colloid, the insulating material 190 can be locally removed by laser to replace / repair the semiconductor components 150 and 152 located in the receiving groove 145.

[0028] Figure 4 is a cross-sectional schematic diagram of a semiconductor package structure according to another embodiment of the present invention. Referring to Figures 1A and 4 simultaneously, the semiconductor package structure 100d of this embodiment is similar to the semiconductor package structure 100a described above, except that in this embodiment, the semiconductor package structure 100d further includes a plurality of bumps (two bumps 185 are schematically shown) electrically connecting the pads 124 of the chip 120' to the conductive portion 112 of the substrate 110. That is, in this embodiment, the chip 120' is bonded to the substrate 110 by flip-chip bonding.

[0029] In summary, in the semiconductor packaging structure of this invention, the encapsulating colloid covers the conductive pillars disposed on the substrate and has a receiving groove exposing the top surface of the conductive pillars. The semiconductor element is disposed within the receiving groove and contacts the top surface of the conductive pillars, thus electrically connecting with the substrate. In other words, the semiconductor element of this invention is independently encapsulated within the receiving groove and does not interfere with the wafer. With this design, when the semiconductor element is subsequently damaged or requires electrical adjustment, it can be quickly removed from the receiving groove for rework. Compared to traditional rework methods, this invention does not damage the original encapsulating colloid and does not adversely affect the wafer, thereby improving product reuse rate.

[0030] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0031] 100a, 100b, 100c, 100d: Semiconductor package structure 110:Substrate 111: Upper surface 112, 114, 116: Conductive parts 113: Lower surface 120, 120': Chip 121: Active side 122, 124: Sealing pads 123: Back 125: Adhesive Crystal Materials 130: Conductive column 131: Top surface 133: Bottom surface 140, 140': Encapsulating colloid 141: First Surface 143: Second Surface 145: Receiving groove 150, 152: Semiconductor components 160: Cover plate 161: Top surface 170: Adhesive materials 180: Stringing 185: Bump 190: Insulating adhesive A: Area B, B': Bottom surface

Claims

1. A semiconductor package structure, comprising: One substrate; A wafer disposed on and electrically connected to the substrate; at least one conductive post disposed on and electrically connected to the substrate; an encapsulating colloid disposed on the substrate and covering the wafer and the at least one conductive post, the encapsulating colloid having a first surface and a second surface opposite to each other and at least one receiving groove, the second surface contacting the substrate, the at least one receiving groove extending from the first surface to the second surface and having at least one bottom surface, the at least one bottom surface exposing at least one top surface of the at least one conductive post; at least one semiconductor element disposed on the at least one bottom surface of the at least one receiving groove and contacting the at least one top surface of the at least one conductive post, the at least one semiconductor element being electrically connected to the substrate through the at least one conductive post; a cover plate disposed within the at least one receiving groove to cover the at least one semiconductor element; An adhesive material is disposed around the cover plate and between the inner wall of the at least one receiving groove, the cover plate being fixed to the at least one receiving groove by means of the adhesive material.

2. The semiconductor packaging structure as claimed in claim 1, wherein the cover plate is an insulating material, and the material of the cover plate includes glass, plastic, ceramic or glass fiber.

3. The semiconductor packaging structure as claimed in claim 1, wherein the adhesive material comprises an ultraviolet degradable adhesive or a thermal degradable adhesive film.

4. The semiconductor package structure as described in claim 1, further comprising: An insulating adhesive is filled in the at least one receiving groove and completely covers the at least one semiconductor element.

5. The semiconductor packaging structure as claimed in claim 4, wherein the insulating adhesive material comprises an ultraviolet degradable adhesive, a pyrolytic adhesive film, an epoxy resin, or an encapsulating colloid.

6. The semiconductor package structure as claimed in claim 1, wherein the wafer is bonded to the substrate by wire bonding or flip-chip bonding.

7. The semiconductor package structure as claimed in claim 1, wherein the orthographic projection of the at least one semiconductor element on the substrate does not overlap with the orthographic projection of the wafer on the substrate.

8. The semiconductor package structure as claimed in claim 1, wherein the at least one semiconductor element comprises at least one passive element or at least one active element.

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