Optical package module and chip set structure and manufacturing method thereof
Patent Information
- Application Number
- TW114113594
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-04-10
- Publication Date
- 2026-10-16
- Estimated Expiration
- 2045-04-09
AI Technical Summary
Conventional co-packaged optical devices face issues such as signal delays, heat generation, and large size due to multiple circuit layers and long signal transmission paths, which hinder miniaturization and increase signal loss.
An optical packaging module integrating electronic and photonic integrated circuit elements into an optoelectronic integrated photonic chip, with grooves for optical elements, heat sinks for stabilization, and conductive vias for electrical connections, enabling direct signal conversion and transmission.
This integration reduces signal delays, heat generation, and alignment loss, while enhancing signal accuracy and speed, and is feasible with existing semiconductor equipment, reducing production costs.
Smart Images
Figure TWG2TA001080238_001 
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Figure TWG2TA001080238_003
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor packaging structure and manufacturing method, and more particularly to an optical packaging module and its wafer assembly structure and manufacturing method. Prior Technology
[0002] With the booming development of the electronics industry, electronic products are gradually moving towards multifunctionality and high performance. The application of fifth-generation (5G) communication technology has expanded to various fields such as the Internet of Things (IoT), Industrial Internet of Things (IIoT), cloud computing, artificial intelligence (AI), autonomous vehicles, and medical care. As applications expand, a massive amount of data needs to be efficiently transmitted, processed, and stored. The demand for data transmission, in particular, is surging, leading industries to replace electricity with light as the data transmission medium. This aims to improve transmission capacity, efficiency, and distance while reducing energy consumption. Against this backdrop, co-packaged optical devices have become a future trend in semiconductor and packaging technology.
[0003] Please refer to Figure 1, which is a cross-sectional schematic diagram of a conventional co-packaged optical device 1. It mainly has an optical engine 11 disposed on a circuit board 10. The optical engine 11 includes an electronic chip 112 formed in the package structure 111 and a photonic chip 113 disposed on the package structure 111. One end of the photonic chip 113 is connected to an optical fiber 14, and a shelf 15 is provided below the junction of the photonic chip 113 and the optical fiber 14 to enable the optical signal to be transmitted to the optical engine 11 for communication. At the same time, a switching chip 12 needs to be disposed on the circuit board 10 to be used in the end product. The switching chip 12 is first disposed on a substrate 13 and then disposed on the circuit board 10 through the substrate 13.
[0004] However, in the aforementioned co-packaged optical devices, since the electronic chip is embedded in the package structure, its electrical connection with the photonic chip requires multiple circuit layers. Therefore, for future high-speed computing and data-intensive applications that require the transmission of large amounts of information, there will be message delays. Furthermore, the transmission of signals along long lines will generate a large amount of heat. Moreover, the photonic chip and the conversion chip must transmit signals through the circuits in the circuit board and substrate. This not only makes the overall size of the device too large and thick, which is not conducive to the miniaturization of electronic products, but also makes the signal transmission path too long, which can easily lead to signal loss and cause problems in the application of end products.
[0005] Therefore, how to overcome the problems of the aforementioned conventional technologies has become an urgent issue that needs to be addressed. Summary of the Invention
[0006] In view of the various deficiencies of the prior art, the present invention provides a chip assembly structure comprising: an optoelectronic integrated photonic chip, which includes electronic integrated circuit elements and photonic integrated circuit elements; electronic elements disposed on the optoelectronic integrated photonic chip; and optical elements disposed on the optoelectronic integrated photonic chip.
[0007] The present invention further provides an optical packaging module, comprising: a carrier structure; and a chip assembly structure disposed on and electrically connected to the carrier structure, comprising: an optoelectronic integrated photonic chip, comprising electronic integrated circuit elements and photonic integrated circuit elements; electronic elements disposed on the optoelectronic integrated photonic chip; and optical elements disposed on the optoelectronic integrated photonic chip.
[0008] The present invention further provides a method for manufacturing an optical packaging module, comprising: providing a chip assembly structure including an optoelectronic integrated photonic chip and electronic components disposed on the optoelectronic integrated photonic chip; attaching and electrically connecting the chip assembly structure to a carrier structure; and disposing optical components on the optoelectronic integrated photonic chip.
[0009] The aforementioned optical packaging module and its wafer assembly structure and manufacturing method further include a heat sink on the support structure for mounting the optical element.
[0010] The aforementioned optical packaging module and its wafer assembly structure and manufacturing method further include placing the carrier structure and electrically connecting it to a circuit board.
[0011] In the aforementioned optical packaging module and its wafer assembly structure and manufacturing method, the supporting structure is a substrate, an interposer, a circuit structure, or a packaging unit.
[0012] In the aforementioned optical packaging module and its wafer assembly structure and manufacturing method, the optoelectronic integrated photonic wafer has a plurality of conductive vias connecting its surface.
[0013] In the aforementioned optical packaging module and its wafer assembly structure and manufacturing method, the optoelectronic integrated photonic wafer forms a groove for connecting the optical element.
[0014] In the aforementioned optical packaging module and its wafer assembly structure and manufacturing method, the electronic component is a high-bandwidth memory.
[0015] In the aforementioned optical packaging module and its wafer assembly structure and manufacturing method, the optical element is a lens structure.
[0016] As can be seen from the above, the optical packaging module and its chip assembly structure and manufacturing method of the present invention mainly integrate electronic integrated circuit elements and photonic integrated circuit elements into a chip assembly (optoelectronic integrated photonic chip), which can directly perform signal conversion and transmission, thereby avoiding the signal delay and large amount of heat generation problems caused by the transmission of signals over long lines in conventional structures. In addition, the surface of the optoelectronic integrated photonic chip has grooves for optical elements to be connected to the grooves, and the optical elements are supported by heat sinks to stabilize them, which can effectively increase the accuracy of the optical signal and effectively reduce alignment loss. Furthermore, conductive vias are formed in the optoelectronic integrated photonic chip, and electronic elements are electrically connected to the conductive vias. In addition to being electrically connected to the optoelectronic integrated photonic chip, they can also be electrically connected to the underlying support structure, thereby increasing the signal transmission speed. Simple Explanation of the Diagram
[0017] Figure 1 is a cross-sectional schematic diagram of a conventionally co-packaged optical device.
[0018] Figures 2A to 2E are cross-sectional schematic diagrams illustrating the manufacturing process of the optical packaging module and its wafer assembly structure according to the present invention. Implementation
[0019] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.
[0020] It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings of this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," "third," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of the present invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the present invention.
[0021] Please refer to Figures 2A to 2E, which are cross-sectional schematic diagrams illustrating the manufacturing process of the optical packaging module and its wafer assembly structure of the present invention.
[0022] As shown in Figure 2A, an optoelectronic integrated photonic chip (EPIC) 20 is provided, wherein at least one groove 200 is formed on the optoelectronic integrated photonic chip 20, and at least one electronic component 21 is disposed on the optoelectronic integrated photonic chip 20 and electrically connected to the optoelectronic integrated photonic chip 20.
[0023] In this embodiment, the optoelectronic integrated photonic chip 20 includes electronic integrated circuit elements (EIC) and photonic integrated circuit elements (PIC), and can directly perform signal conversion and transmission to avoid the signal delay and large amount of heat generated when transmitting signals between long lines in conventional structures. It has a first side 20a and a second side 20b, and forms a plurality of conductive vias 201 (e.g., conductive silicon vias) connecting the first side 20a and the second side 20b.
[0024] The groove 200 can be formed on the first side 20a of the optoelectronic integrated photonic chip 20 by means of laser cutting or cutting tool. A plurality of conductive bumps 202 are provided on the second side 20b of the optoelectronic integrated photonic chip 20.
[0025] In this embodiment, the electronic component 21 is, for example, a high bandwidth memory (HBM), which can be connected to the first side 20a of the optoelectronic integrated photonic chip 20 through a plurality of conductive elements and electrically connected to the optoelectronic integrated photonic chip 20, and a filling layer covering the plurality of conductive elements can be formed between the electronic component 21 and the optoelectronic integrated photonic chip 20.
[0026] The electronic component 21 can be directly electrically connected to the optoelectronic integrated photonic chip 20 (which includes electronic integrated circuit elements and photonic integrated circuit elements) through the plurality of conductive vias 201, thereby improving the signal transmission speed.
[0027] As shown in Figure 2B, the optoelectronic integrated photonic chip 20 is mounted and electrically connected to a carrier structure 22 via a plurality of conductive bumps 202. The carrier structure has a first surface 22a and a second surface 22b opposite to each other, so that the optoelectronic integrated photonic chip 20 is mounted on the first surface 22a. The carrier structure 22 may be, for example, a substrate, an interposer, a circuit structure, or a packaging unit.
[0028] As shown in Figure 2C, a heat sink 23 is disposed on the first surface 22a of the support structure 22, and a plurality of conductive elements 24 are disposed on the second surface 22b of the support structure 22. The heat sink 23 may be arranged in a ring around the optoelectronic integrated photonic chip 20, and the plurality of conductive elements 24 may be, for example, solder balls.
[0029] As shown in Figure 2D, an optical element 25 is disposed on the first side 20a of the optoelectronic integrated photonic chip 20 and connected to the groove 200. In this embodiment, the optical element 25 can also be placed on the heat sink 23 to stabilize the optical element 25 by the support of the heat sink 23, which can effectively increase the accuracy of the optical signal and effectively reduce alignment loss. For example, the optical signal provided by the subsequent laser and / or optical fiber can be effectively introduced into the optoelectronic integrated photonic chip 20 through the optical element 25. The optical element 25 is, for example, a lens structure.
[0030] It should be understood that in other embodiments, the electronic component 21 and the optical component 25 may be disposed on the first side 20a of the optoelectronic integrated photonic chip 20, and the optoelectronic integrated photonic chip 20 may be attached to the support structure 22, and the support structure 22 is provided with a heat sink 23 so that the optical component 25 may be placed on the heat sink 23 at the same time.
[0031] As shown in Figure 2E, the supporting structure 22 can then be connected to a circuit board 26 through the plurality of conductive elements 24.
[0032] Through the aforementioned manufacturing method, the present invention discloses a chip assembly structure 2a, which includes an optoelectronic integrated photonic chip 20, electronic components 21 disposed on the optoelectronic integrated photonic chip 20, and optical components 25 disposed on the optoelectronic integrated photonic chip 20.
[0033] The optoelectronic integrated photonic chip 20 includes electronic integrated circuit elements and photonic integrated circuit elements. It has a first side 20a and a second side 20b opposite to each other, and forms a plurality of conductive through holes 201 connecting the first side 20a and the second side 20b. A groove 200 is formed on the first side.
[0034] The electronic component 21 is, for example, a high bandwidth memory (HBM) and can be directly electrically connected to the optoelectronic integrated photonic chip 20 through the plurality of conductive vias 201.
[0035] The optical element 25 is, for example, a lens structure, which is disposed on the first side 20a of the optoelectronic integrated photonic chip 20 and connected to the groove 200.
[0036] The present invention further discloses an optical packaging module 2b, which includes a carrier structure 22 and a wafer assembly structure 2a disposed on the carrier structure 22.
[0037] The support structure 22 is, for example, a substrate, an interposer, a circuit structure or a packaging unit, and the support structure 22 is provided with a heat sink 23 so that the optical element 25 can be placed on the heat sink 23 at the same time.
[0038] The optical packaging module 2b further includes a circuit board 26 for mounting the carrier structure 22.
[0039] In summary, the optical packaging module and its chip assembly structure and manufacturing method of the present invention mainly integrate electronic integrated circuit elements and photonic integrated circuit elements into a chip assembly (optoelectronic integrated photonic chip), which can directly perform signal conversion and transmission, thereby avoiding the signal delay and large amount of heat generation problems caused by the transmission of signals over long lines in conventional structures. In addition, a groove is formed on the surface of the optoelectronic integrated photonic chip for optical elements to be connected to the groove, and the optical elements are supported by heat sinks to stabilize them, which can effectively increase the accuracy of the optical signal and effectively reduce alignment loss. Furthermore, conductive vias are formed in the optoelectronic integrated photonic chip, and electronic elements are electrically connected to the conductive vias. In addition to being electrically connected to the optoelectronic integrated photonic chip, they can also be electrically connected to the underlying support structure, thereby increasing the signal transmission speed.
[0040] In addition, the optical packaging module and its chip assembly structure technology are highly feasible to implement and can be manufactured with existing semiconductor packaging equipment without the need to develop special processes or purchase special equipment, thus reducing product production costs.
[0041] The above embodiments are illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as set forth in the following patent claims.
[0042]
[0043] 1: Co-packaged optical devices
[0044] 10: Circuit board
[0045] 11: Optical Engine
[0046] 111: Packaging Structure
[0047] 112: Electronic Chip
[0048] 113: Photonic chip
[0049] 12: Conversion chip
[0050] 13:Substrate
[0051] 14: Optical Fiber
[0052] 15: Bracket
[0053] 2a: Chipset Structure
[0054] 2b: Optical packaging module
[0055] 20: Optoelectronic integrated photonic chip
[0056] 20a: First side
[0057] 20b: Second side
[0058] 200: Groove
[0059] 201: Conductive Through-hole
[0060] 202: Conductive bump
[0061] 21: Electronic Components
[0062] 22: Load-bearing structure
[0063] 22a: First surface
[0064] 22b: Second surface
[0065] 23: Heat sink
[0066] 24: Conductive elements
[0067] 25: Optical Components
[0068] 26: Circuit Board
Claims
1. A chip assembly structure, comprising: The optoelectronic integrated photonic chip includes electronic integrated circuit elements and photonic integrated circuit elements, wherein at least one groove is formed on the optoelectronic integrated photonic chip; electronic elements are disposed on the optoelectronic integrated photonic chip; and optical elements are disposed on the optoelectronic integrated photonic chip and connected to the groove.
2. The wafer assembly structure as described in claim 1, wherein, The optoelectronic integrated photonic chip has a plurality of conductive vias connecting its surface.
3. The wafer assembly structure as described in claim 1, wherein, This electronic component is a high-bandwidth memory.
4. The wafer assembly structure as described in claim 1, wherein, The optical element has a lens structure.
5. An optical packaging module, comprising: Load-bearing structure; The chip assembly structure is disposed on and electrically connected to the carrier structure, comprising: an optoelectronic integrated photonic chip, which includes electronic integrated circuit elements and photonic integrated circuit elements, wherein at least one groove is formed on the optoelectronic integrated photonic chip; electronic elements disposed on the optoelectronic integrated photonic chip; and optical elements disposed on the optoelectronic integrated photonic chip and connected to the groove.
6. The optical packaging module as described in claim 5 further includes a heat sink disposed on the support structure for mounting the optical element.
7. The optical packaging module as described in claim 5 further includes a circuit board for mounting the carrier structure.
8. The optical packaging module as described in claim 5, wherein, The supporting structure can be a substrate, an interposer, a circuit structure, or a packaging unit.
9. The optical packaging module as described in claim 5, wherein, The optoelectronic integrated photonic chip has a plurality of conductive vias connecting its surface.
10. The optical packaging module as described in claim 5, wherein, This electronic component is a high-bandwidth memory.
11. The optical packaging module as described in claim 5, wherein, The optical element has a lens structure.
12. A method for manufacturing an optical packaging module, comprising: A chip assembly structure is provided, comprising an optoelectronic integrated photonic chip and electronic components disposed on the optoelectronic integrated photonic chip, wherein at least one groove is formed on the optoelectronic integrated photonic chip; the chip assembly structure is disposed and electrically connected to a carrier structure; and optical components are disposed on the optoelectronic integrated photonic chip and connected to the groove.
13. The method of manufacturing the optical packaging module as described in claim 12 further includes providing a heat sink on the support structure for mounting the optical element.
14. The method of manufacturing the optical packaging module as described in claim 12 further includes attaching and electrically connecting the carrier structure to a circuit board.
15. A method for manufacturing an optical packaging module as described in claim 12, wherein, The supporting structure can be a substrate, an interposer, a circuit structure, or a packaging unit.
16. A method for manufacturing an optical packaging module as described in claim 12, wherein, The optoelectronic integrated photonic chip has a plurality of conductive vias connecting its surface.
17. A method for manufacturing an optical packaging module as described in claim 12, wherein, This electronic component is a high-bandwidth memory.
18. A method for manufacturing an optical packaging module as described in claim 12, wherein, The optical element has a lens structure.