Distributed memory shingle layout for data transfer between dies implementing neural networks

Abstract

A stacked wafer may include integrated dies that can implement neural network models. The stacked wafer may include a memory layer (e.g., a memory wafer) and a logic layer (e.g., a logic wafer). The memory layer and logic layer may each include dies and scribe lines. A memory die in the memory layer may include a first scribe line. The logic layer may include a second scribe line between a first logic die and a second logic die of the logic layer. The memory die and first logic die may be offset and electrically coupled through interconnects and a metal layer. The interconnects may connect the first scribe line to an input / output circuit of the first logic die. The metal layer may be the top metal layer of the memory wafer. The metal layer may facilitate both vertical electrical connectivity and horizontal electrical connectivity within the stacked wafer.

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