High performance integrated RF passives using dual lithography process

Abstract

Embodiments of the present invention include an electrical package and a method of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop formed in the package. Another embodiment of the present invention includes forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate from a second capacitor plate formed in the package. The thin dielectric spacer material in the transformer and capacitor allows for an increase in coupling factor and capacitance density in the electrical components.

Description

[Technical Field] Invention Field Embodiments of the present invention generally relate to the manufacture of semiconductor devices. In particular, embodiments of the present invention relate to a package including an inductor having improved coupling and a capacitor having improved capacitance density, and a method for manufacturing such a device. [Previous Technology] Background of the Invention Highly coupled transformers and high-density capacitors are useful in many radio frequency (RF) and power delivery applications. To provide greater integration in a single package, more passive components (e.g., transformers and capacitors) are fabricated within that package. However, current package design rules limit the optimization of some of the electrical performance of these components. For example, the minimum permissible spacing between conductors in a package makes it difficult to implement tightly coupled inductors in a small area. A coupling factor higher than approximately 0.5 is difficult to achieve without consuming a relatively large area and a large number of layers on the package. Currently, low coupling factors are addressed by using resonant transformers in RF, eliminating leakage inductance by inserting a discrete capacitor connected in series or parallel with the transformer. This increases cost and system size. Furthermore, resonant transformers are narrow-bandwidth, requiring additional transformers for other bands. For power delivery applications (e.g., buck-boost or flyback converters), these transformers are implemented as discrete components on the package or the motherboard. In RF applications, capacitors are commonly used for amplifier tuning or antenna matching. Currently, capacitors can be integrated into the package substrate layer. However, this package design typically requires a fairly thick dielectric layer (e.g., 20 μm or more) to separate the parallel plates of these capacitors. Since the capacitance value is inversely proportional to the dielectric thickness, the capacitance per unit area is relatively small, and the desired capacitance value must be obtained by increasing the package size or by using additional discrete capacitors. In addition to the increased system cost and / or size, using additional discrete capacitors increases routing parasitics and increases losses. This, in turn, reduces the maximum operating frequency of the device. Therefore, improvements are needed in the field of electronic packaging manufacturing to create integrated transformers and capacitors with improved coupling and capacitance per unit area, respectively. [Summary of the Invention] According to one embodiment of the present invention, a transformer formed in an electrical package is specifically provided, comprising: a first dielectric layer; a first conductive loop formed on one surface of the first dielectric layer; a dielectric spacer formed on the first conductive loop; and a second conductive loop separated from the first conductive loop by the dielectric spacer layer. [Simplified Explanation of the Diagram] Figure 1 is a perspective view of one of the encapsulation substrates of a transformer. Figure 2A is a plan view and a corresponding cross-sectional view of a packaging substrate, which has a dielectric layer on the surface on which a seed layer is formed, according to an embodiment of the present invention. Figure 2B is a plan view and a corresponding cross-sectional view of the encapsulation substrate after a first conductive circuit is formed on a surface of the substrate, according to an embodiment of the present invention. Figure 2C is a plan view and a corresponding cross-sectional view of the package substrate after a dielectric spacer is formed on the first conductive circuit, according to an embodiment of the present invention. Figure 2D is a plan view and a corresponding cross-sectional view of the package substrate after a second conductive loop is formed on the dielectric spacer, according to an embodiment of the present invention. Figure 2E is a plan view and a corresponding cross-sectional view of the encapsulation substrate after the exposed portions of the second photoresist material and the seed layer have been removed, according to an embodiment of the present invention. Figure 3A is a plan view and a corresponding cross-sectional view of a packaging substrate, the packaging substrate having a dielectric layer on the surface on which a seed layer is formed, according to an embodiment of the present invention. Figure 3B is a plan view and a corresponding cross-sectional view of the encapsulation substrate after a first conductive circuit is formed on a surface of the substrate, according to an embodiment of the present invention. Figure 3C is a plan view and a corresponding cross-sectional view of the package substrate after a dielectric spacer is formed on the first conductive circuit, according to an embodiment of the present invention. Figure 3D is a plan view and a corresponding cross-sectional view of the package substrate after a second conductive circuit is formed within the first conductive circuit, according to an embodiment of the present invention. Figure 3E is a plan view and a corresponding cross-sectional view of the encapsulation substrate after the exposed portions of the second photoresist material and the seed layer have been removed, according to an embodiment of the present invention. Figure 4A is a cross-sectional view of an encapsulation substrate after a first conductive circuit is formed in a patterned photoresist layer, according to an embodiment of the present invention. Figure 4B is a cross-sectional view of the package substrate after a top cover dielectric is formed on the first conductive circuit, according to an embodiment of the present invention. Figure 4C is a cross-sectional view of the encapsulation substrate after the photoresist layer has been removed and a sidewall dielectric has been deposited on the exposed surface, according to an embodiment of the invention. Figure 4D is a cross-sectional view of the package substrate after the sidewall dielectric layer has been etched to provide sidewall dielectric spacers along the sidewalls of the first conductive loop, according to an embodiment of the invention. Figure 5A is a cross-sectional view of a package substrate comprising a parallel-plate capacitor formed within a single dielectric layer, according to an embodiment of the present invention. Figure 5B is a cross-sectional view of a capacitor having interdigitated extensions that can be included in one layer of a package substrate, according to an embodiment of the invention. Figure 5C is a perspective view of a portion of a first conductive plate that can be used in a capacitor having interdigitated extensions, according to an embodiment of the invention. Figure 5D is a perspective view of a capacitor having interdigitated extensions, according to another embodiment of the present invention. Figure 6A is a cross-sectional view of a packaging substrate having a dielectric layer on the surface on which a seed layer is formed, according to an embodiment of the present invention. Figure 6B is a cross-sectional view of the encapsulation substrate after a first meandering plate is formed on a surface of the substrate, according to an embodiment of the invention. Figure 6C is a cross-sectional view of the package substrate after a dielectric spacer has been formed on the first meandering plate, according to an embodiment of the present invention. Figure 6D is a cross-sectional view of the encapsulation substrate after the exposed portion of the seed layer has been removed, according to an embodiment of the present invention. Figure 6E is a cross-sectional view of the encapsulation substrate after a patterned photoresist material is formed on the surface and a second seed layer is formed on the dielectric spacer layer, according to an embodiment of the present invention. Figure 6F is a cross-sectional view of the encapsulation substrate after a second meandering plate is formed on the dielectric spacer layer, according to an embodiment of the present invention. Figure 6G is a cross-sectional view of the encapsulation substrate after a second dielectric layer has been deposited on the surface of the encapsulation substrate, according to an embodiment of the present invention. Figure 7 is a schematic diagram of a computing device constructed according to an embodiment of the present invention.

Implementation Method

Claims

1. A transformer in an electrical package, comprising: a first dielectric layer; a first conductive loop on a surface of the first dielectric layer, wherein a first trace forming the first conductive loop has a first width; a dielectric spacer on the first conductive loop; a second conductive loop on the surface of the first dielectric layer, the second conductive loop being laterally adjacent to the first conductive loop in a coplanar plane and separated from the first conductive loop by the dielectric spacer, wherein the first conductive loop is not electrically connected to the second conductive loop, and wherein a second trace forming the second conductive loop has a second width smaller than the first width; and a second dielectric layer, wherein the first conductive loop, the second conductive loop, and the dielectric spacer are located within the second dielectric layer.

2. The transformer of claim 1, wherein the dielectric spacer includes a top cover layer formed on a top surface of the first conductive circuit and a sidewall spacer formed on a sidewall of the first conductive circuit.

3. The transformer of claim 1, wherein the second conductive loop is formed within a periphery of the first conductive loop.

4. The transformer of claim 1, wherein the dielectric spacer has a thickness of less than 20 μm.

5. The transformer of claim 4, wherein the dielectric spacer has a thickness of less than 5 μm.

6. A transformer in an electrical package, comprising: a first dielectric layer; a first conductive loop on a surface of the first dielectric layer, wherein a first trace forming the first conductive loop has a first width; a dielectric spacer on the first conductive loop; a second conductive loop laterally adjacent to the first conductive loop, the second conductive loop being separated from the first conductive loop by the dielectric spacer, wherein the first conductive loop is not electrically connected to the second conductive loop, and wherein a second trace forming the second conductive loop has a second width smaller than the first width, wherein the second conductive loop is formed on the first dielectric layer, and wherein a sidewall surface of the first conductive loop is separated from a sidewall surface of the second conductive loop by the dielectric spacer; and a second dielectric layer, wherein the first conductive loop, the second conductive loop, and the dielectric spacer are located within the second dielectric layer, wherein the dielectric spacer includes a top cap layer formed on a top surface of the first conductive loop and a sidewall spacer formed on a sidewall of the first conductive loop.

7. A transformer in an electrical package, comprising: a first dielectric layer; a first conductive loop formed on a surface of the first dielectric layer; a dielectric spacer formed on the first conductive loop; and a second conductive loop separated from the first conductive loop by the dielectric spacer, wherein the first conductive loop is not electrically connected to the second conductive loop, wherein the dielectric spacer includes a top cover layer formed on a top surface of the first conductive loop and a sidewall spacer formed on a sidewall of the first conductive loop, and wherein the top cover layer is made of a material different from the sidewall spacer.

8. A method of forming a transformer in an electrical package, comprising: forming a first conductive loop over a first dielectric layer, wherein a first trace forming the first conductive loop has a first width; forming a dielectric spacer over the first conductive loop; forming a second conductive loop, wherein the first conductive loop is not electrically connected to the second conductive loop, wherein a second trace forming the second conductive loop has a second width smaller than the first width, wherein the second conductive loop is formed laterally adjacent to the first conductive loop in a coplanar plane, and wherein forming the second conductive loop comprises: forming a seed layer over the dielectric spacer; depositing and patterning a photoresist material to form an opening above the first conductive loop; electroplating a conductive material in the openings; and forming a second dielectric layer, wherein the first conductive loop, the second conductive loop, and the dielectric spacer are located within the second dielectric layer.

9. The method of claim 8, wherein the dielectric spacer includes a top cap layer formed on a top surface of the first conductive circuit and a sidewall spacer formed on a sidewall of the first conductive circuit.

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