Group iii nitride-based radio frequency transistor amplifiers having source, gate and / or drain conductive vias

Abstract

This invention discloses a radio frequency (RF) transistor amplifier comprising a group III nitride-based RF transistor amplifier die. The group III nitride-based RF transistor amplifier die includes: a semiconductor layer structure; a power supply electrode path connected to a source region of the group III nitride-based RF transistor amplifier die, the power supply electrode path extending through the semiconductor layer structure; and an additional conductive path extending through the semiconductor layer structure. A first end of the additional conductive path is connected to a first external circuit, and a second end of the additional conductive path opposite to the first end is connected to a first matching circuit.

Description

[Technical Field]

[0001] This invention relates to microelectronic devices, and more particularly, to high-power high-frequency transistor amplifiers. [Previous Technology]

[0002] In recent years, circuits requiring high power handling capabilities and high-frequency operation at frequencies such as the R-band (0.5 GHz to 1 GHz), S-band (3 GHz), and X-band (10 GHz) have become more common. Specifically, there is a great need for radio frequency ("RF") transistor amplifiers used to amplify RF signals at radio (including microwave) frequencies. These RF transistor amplifiers need to exhibit high reliability, good linearity, and the ability to handle high output power levels.

[0003] Most RF transistor amplifiers are implemented in silicon or using wide-bandgap semiconductor materials such as silicon carbide (“SiC”) and group III nitride materials. As used herein, the term “group III nitride” refers to a semiconducting compound formed between nitrogen and a group III element of the periodic table (typically aluminum (Al), gallium (Ga), and / or indium (In)). The term also refers to ternary and quaternary compounds such as AlGaN and AlInGaN. These compounds have empirical formulas in which 1 mole of nitrogen is combined with a total of 1 mole of group III elements.

[0004] Silicon-based RF transistor amplifiers are typically implemented using laterally diffused metal-oxide-semiconductor ("LDMOS") transistors. Silicon LDMOS RF transistor amplifiers exhibit high linearity levels and are relatively inexpensive to manufacture. Group III nitride-based RF transistor amplifiers are typically implemented using high electron mobility transistors ("HEMT") and are primarily used in applications requiring high power and / or high-frequency operation, where LDMOS RF transistor amplifiers have inherent performance limitations.

[0005] An RF transistor amplifier may include one or more amplification stages, wherein each stage is typically implemented as a transistor amplifier. To improve output power and current handling capability, an RF transistor amplifier is typically implemented as a "unit cell" configuration, wherein a large number of individual "unit cell" transistors are connected in parallel. An RF transistor amplifier may be implemented as a single integrated circuit chip or "die," or may include multiple dies. When multiple RF transistor amplifier dies are used, they may be connected in series and / or in parallel.

[0006] RF transistor amplifiers typically include matching circuitry (such as impedance matching circuitry) designed to improve impedance matching between an RF amplifier die and the transmission lines connected to the RF amplifier die for the RF signal at the fundamental operating frequency, and harmonic termination circuitry designed to at least partially terminate harmonics (such as second and third harmonics) that may be generated during device operation. Harmonic termination also affects intermodulation distortion products. (Several) The RF transistor amplifier die and the impedance matching and harmonic termination circuitry may be enclosed in a package. Electrical leads may extend from the package and are used to electrically connect the RF transistor amplifier to external circuitry elements, such as input and output RF transmission lines and bias voltage sources.

[0007] As mentioned above, RF transistor amplifiers based on group III nitrides are typically used in high-power and / or high-frequency applications. Typically, high heat is generated during operation within the RF transistor(s) based on group III nitrides. If the RF transistor(s) become too hot, the performance of the RF transistor(s) (e.g., output power, efficiency, linearity, gain, etc.) will deteriorate and / or the RF transistor(s) may be damaged. Therefore, RF transistor amplifiers based on group III nitrides are typically mounted in packages optimized for heat removal. Figures 1A and 1B illustrate a conventionally packaged RF transistor amplifier based on group III nitrides. Specifically, Figure 1A is a schematic side view of a conventionally packaged RF transistor amplifier 100 based on a group III nitride, and Figure 1B is a schematic cross-sectional view of an RF transistor amplifier die contained in the RF transistor amplifier 100 based on a group III nitride, wherein the cross-section is taken along line 1B-1B of Figure 1A. It should be understood that Figures 1A to 1B (and various other figures) are highly simplified diagrams, and actual RF transistor amplifiers may contain many more unit cells and various circuit systems and components not shown in these simplified diagrams.

[0008] As shown in Figure 1A, the group III nitride-based RF transistor amplifier 100 includes an RF transistor amplifier die 110 mounted within an open-cavity package 170. The package 170 includes a gate lead 172, a drain lead 174, a metal flange 176, and a ceramic sidewall and cap 178. The RF transistor amplifier die 110 is mounted on the upper surface of the metal flange 176 within a cavity formed by the metal flange 176 and the ceramic sidewall and cap 178. The RF transistor amplifier die 110 has a top side 112 and a bottom side 114. The RF transistor amplifier die 110 includes a sequentially stacked bottom-side (also referred to as a "back") metallization structure 120, a semiconductor layer structure 130, and a top-side metallization structure 140. The back-side metallization structure 120 includes a metal source terminal 126. The RF transistor amplifier 100 may be a HEMT-based RF transistor amplifier. In this case, the semiconductor layer structure 130 may include at least one channel layer and a barrier layer typically formed on a semiconductor or insulating growth substrate (such as a SiC or sapphire substrate). Even if the growth substrate is formed of a non-semiconductor material, it can be considered part of the semiconductor layer structure 130. The top-side metallization structure 140 includes a metal gate terminal 142 and a metal drain terminal 144, etc.

[0009] Input matching circuit 190 and / or output matching circuit 192 may also be installed within housing 170. Matching circuits 190 and 192 may be: impedance matching circuits that match the impedance of the fundamental component of the RF signal input to or output from RF transistor amplifier 100 to the impedance at the input or output of RF transistor amplifier chip 110, respectively; and / or harmonic termination circuits configured to short-circuit to ground harmonics, such as second or third harmonics, of the fundamental RF signal present at the input or output of RF transistor amplifier chip 110. As schematically shown in FIG1A, input matching circuit 190 and output matching circuit 192 may be mounted on metal flange 176. Gate lead 172 may be connected to input matching circuit 190 by one or more first bonding lines 182, and input matching circuit 190 may be connected to gate terminal 142 of RF amplifier chip 110 by one or more second bonding lines 183. Similarly, drain lead 174 may be connected to output matching circuit 192 via one or more fourth junction lines 185, and output matching circuit 192 may be connected to drain terminal 144 of RF amplifier die 110 via one or more third junction lines 184. Source terminal 126 of RF transistor amplifier die 110 may be directly mounted on metal flange 176. Metal flange 176 provides electrical connection to source terminal 126 and also serves as a heat dissipation structure. First junction lines 182 to fourth junction lines 185 may form portions of input and / or output matching circuits. Housing 170 may include a ceramic housing, and gate lead 172 and drain lead 174 may extend through housing 170. Housing 170 may include multiple components, such as a frame forming a lower portion of the sidewalls and supporting gate lead 172 and drain lead 174, and a cover placed on top of the frame. The interior of the device may include an air-filled cavity.

[0010] Figure 1B is a schematic cross-sectional view of an RF transistor amplifier die 110 taken through a portion of the top-side metallization structure 140. The dielectric layer that isolates the various conductive elements of the top-side metallization structure 140 from each other is not shown in Figure 1B for the sake of simplicity.

[0011] As shown in FIG1B, the RF transistor amplifier die 110 includes a HEMT RF transistor amplifier based on a group III nitride, having a plurality of unit transistors 116, each including a gate finger 152, a drain finger 154, and a source finger 156. The gate finger 152 is electrically connected to a common gate bus 146, and the drain finger 154 is electrically connected to a common drain bus 148. The gate bus 146 is electrically connected to a gate terminal 142 implemented as a gate pad (see FIG1A) (e.g., through a conductive path extending upward from the gate bus 146), and the drain bus 148 is electrically connected to a drain terminal 144 implemented as a drain pad (see FIG1A) (e.g., through a conductive path extending upward from the drain bus 148). The source terminal 156 is electrically connected to the source terminal 126 via a plurality of conductive electrode paths 166 extending through the semiconductor layer structure 130. The conductive electrode paths 166 may include metal-plated paths that extend completely through the semiconductor layer structure 130.

[0012] Referring again to FIG. 1A, the metal flange 176 can act as a heat sink to dissipate heat generated in the RF transistor amplifier die 110. Heat is primarily generated in the upper portion of the RF transistor amplifier die 110, where, for example, a relatively high current density is generated in the channel region of the unit transistor 116. This heat can be transferred to the metal flange 176 through the source path 166 and the semiconductor layer structure 130.

[0013] Figure 1C is a schematic side view of a conventional packaged RF transistor amplifier 100' based on a group III nitride, similar to the RF transistor amplifier discussed above with reference to Figure 1A. The RF transistor amplifier 100' differs from the RF transistor amplifier 100 in that it includes a different package 170'. Package 170' includes a metal substrate 176 (which acts as a metal heat sink and can be implemented as a metal block) and gate leads 172' and drain leads 174'. In some embodiments, a metal lead frame may be formed, which is then processed to provide the metal substrate 176 and / or the gate leads 172' and drain leads 174'. RF transistor amplifier 100' also includes a plastic overmolded part 178' that at least partially surrounds the RF transistor amplifier die 110, leads 172', 174', and metal substrate 176'. Depending on the embodiment, the packaged transistor amplifier 100' may include, for example, a monolithic microwave integrated circuit (MMIC) as the RF transistor amplifier die 110. In this case, the input matching circuit 190 and / or the output matching circuit 192 may be omitted (since they can be implemented within the RF transistor amplifier die 110), and the junction lines 182 and / or 185 may extend directly from the gate lead 172' and the drain lead 174' to the gate terminal 142 and the drain terminal 144. In some embodiments, the packaged RF transistor amplifier 100 may include a plurality of RF transistor amplifier dies connected in series to form a multi-stage RF transistor amplifier, and / or may include a plurality of transistor dies disposed in multiple paths (e.g., in parallel) to form an RF transistor amplifier (such as a doherty amplifier configuration) with the plurality of RF transistor amplifier dies and the multiple paths. [Summary of the Invention]

[0014] According to an embodiment of the present invention, an RF transistor amplifier is provided, comprising a group III nitride-based RF transistor amplifier die, the group III nitride-based RF transistor amplifier die comprising: a semiconductor layer structure; a power supply electrode path connected to a source region of the group III nitride-based RF transistor amplifier die, the power supply electrode path extending through the semiconductor layer structure; and an additional conductive path extending through the semiconductor layer structure. A first end of the additional conductive path is connected to a first external circuit, and a second end of the additional conductive path opposite to the first end is connected to a first matching circuit.

[0015] In some embodiments, the additional conductive path may be a conductive gate path connected to a gate electrode of the group III nitride-based RF transistor amplifier die, and the first matching circuit may be a first input matching circuit. In these embodiments, the group III nitride-based RF transistor amplifier die may further include a conductive drain path connected to a drain finger of the group III nitride-based RF transistor amplifier die, wherein a first end of the conductive drain path is connected to a second external circuit and a second end of the conductive drain path opposite to the first end of the conductive drain path is connected to a first output matching circuit.

[0016] In some embodiments, the additional conductive path may be a conductive drain path connected to a drain finger of the group 3 nitride-based RF transistor amplifier chip, and the first matching circuit may be a first output matching circuit.

[0017] In some embodiments, the RF transistor amplifier may further include an interconnect structure, and the group III nitride-based RF transistor amplifier die may be mounted on an upper surface of the interconnect structure. In some of these embodiments, the first end of the conductive gate path may be a top end, and the second end of the conductive gate path may be electrically connected to a bottom end of a first conductive pad on the interconnect structure via a first contact such as a conductive bump or a die attachment material. The first input matching circuit may include a capacitor coupled between the bottom end of the conductive gate path and the electrical ground. The first input matching circuit may include a harmonic termination circuit, and the RF transistor amplifier may further include a second input impedance matching circuit, which includes a basic matching circuit connected to the top end of the conductive gate path.

[0018] In other embodiments, the first end of the conductive gate path may be electrically connected to the bottom end of a first conductive pad on the interconnect structure via a first contact, and the second end of the conductive gate path may be a top end. In these embodiments, the first input matching circuit may include a capacitor coupled between the top end of the conductive gate path and electrical ground. The first input matching circuit may include, for example, a harmonic termination circuit.

[0019] In some embodiments, the first end of the conductive drain path may be a top end and the second end of the conductive drain path may be electrically connected to the bottom end of a second conductive pad on the interconnect structure through a second contact.

[0020] In some embodiments, the first output matching circuit may include a capacitor coupled between the bottom end of the conductive drain path and electrical ground.

[0021] In some embodiments, the first output matching circuit may include a basic impedance matching circuit, and the RF transistor amplifier may further include a second output matching circuit, which includes a harmonic termination matching circuit connected to the top of the conductive drain path.

[0022] In some embodiments, the first end of the conductive drain path may be electrically connected to the bottom end of a first conductive pad on the interconnect structure through a first contact, and the second end of the conductive drain path may be a top end.

[0023] In some embodiments, the first output matching circuit may include a capacitor coupled between the top of the conductive drain path and electrical ground.

[0024] In some embodiments, the first input matching circuit may include a basic impedance matching circuit.

[0025] In some embodiments, the RF transistor amplifier may further include an interconnect structure, and the group III nitride-based RF transistor amplifier die may be mounted on one of the upper surfaces of the interconnect structure. The RF transistor amplifier may also include a passive RF component comprising a capacitor mounted on the interconnect structure and electrically connected to the additional conductive path through the interconnect structure.

[0026] In some embodiments, the group III nitride-based RF transistor amplifier die includes a plurality of parallel drain fingers and the conductive drain path is one of a plurality of drain paths, wherein at least two conductive drain paths are located below each of the conductive drain fingers. In these embodiments, the at least two conductive drain paths located below a first of the conductive drain fingers may define a first axis, and the at least two conductive drain paths located below a second of the conductive drain fingers adjacent to the first of the conductive drain paths may define a second axis, and when the group III nitride-based RF transistor amplifier die is viewed from above, the conductive gate path may be located between the first axis and the second axis.

[0027] In some embodiments, the semiconductor layer structure may include a growth substrate, a channel layer and a barrier layer, wherein the channel layer is located between the growth substrate and the barrier layer, and wherein the conductive gate path and the conductive drain path are metallized paths extending through all three of the growth substrate, the channel layer and the barrier layer.

[0028] In some embodiments, the conductive gate path, the conductive drain path and the conductive power source path may all have a substantially identical shape and a substantially identical cross-sectional area.

[0029] In some embodiments, the additional conductive path may include a portion of the first matching circuit.

[0030] According to a further embodiment of the present invention, an RF transistor amplifier is provided, comprising: an RF transistor amplifier die based on a group III nitride, comprising a semiconductor layer structure and a conductive path extending through the semiconductor layer structure; a first impedance matching circuit coupled between a first end of the conductive path and a first external electrical connection; and a first harmonic termination circuit coupled between a second opposite end of the conductive path and a second external electrical connection.

[0031] In some embodiments, the conductive path may be a conductive gate path connected to a gate electrode of a group 3 nitride-based RF transistor amplifier die, and the first end of the conductive gate path may be adjacent to a top end of the gate electrode and the second end of the conductive gate path may be a bottom end.

[0032] In some embodiments, the conductive path may be a conductive drain path connected to a drain electrode of the RF transistor amplifier die based on group 3 nitride, and the first end of the conductive drain path may be a bottom end and the second end of the conductive drain path may be adjacent to a top end of the drain electrode.

[0033] In some embodiments, the RF amplifier may further include a conductive drain path connected to one of the drain electrodes of the group III nitride-based RF transistor amplifier die.

[0034] In some embodiments, the RF amplifier may further include a second impedance matching circuit coupled between a first end of one of the conductive drain paths and a third external electrical connection.

[0035] In some embodiments, the first end of the conductive drain path may be a top end.

[0036] In some embodiments, the first end of the conductive drain path may be a bottom end.

[0037] In some embodiments, the RF amplifier may further include a redistribution layer ("RDL") laminate substrate, and the group III nitride-based RF transistor amplifier die may be mounted on one of the upper surfaces of the RDL laminate substrate.

[0038] In some embodiments, the first end of the conductive path may be a top end and the second end of the conductive path may be electrically connected to the bottom end of a first conductive pad on the RDL laminate substrate through a contact.

[0039] In some embodiments, the first harmonic termination circuit may include a capacitor coupled between the bottom end of the conductive path and electrical ground.

[0040] In some embodiments, the capacitor may be part of a passive RF component mounted on the RDL laminate and electrically connected to one of the conductive paths through the RDL laminate.

[0041] In some embodiments, the semiconductor layer structure may include a growth substrate, a channel layer and a barrier layer, wherein the channel layer is located between the growth substrate and the barrier layer, and the conductive gate path and the conductive drain path are metallized paths extending through all three of the growth substrate, the channel layer and the barrier layer.

[0042] In some embodiments, the conductive gate path, the conductive drain path and the conductive power source path may all have a substantially identical shape and a substantially identical cross-sectional area.

[0043] According to a further embodiment of the present invention, an RF transistor amplifier is provided, comprising: an RDL laminate substrate; an RF transistor amplifier die based on a group III nitride, which is located on a top surface of the RDL laminate substrate, the RF transistor amplifier die based on a group III nitride includes a semiconductor layer structure having a plurality of unit transistors in an upper portion, a power supply path, a gate path and a drain path, each of the power supply path, the gate path and the drain path extending through the semiconductor layer structure; and a plurality of contacts, which are located on a bottom surface of the RDL laminate substrate.

[0044] In some embodiments, the contacts are configured as either a fan-in configuration or a fan-out configuration.

[0045] In some embodiments, the RDL laminate substrate may include an upper gate pad electrically connected to one of the conductive gate paths, an upper drain pad electrically connected to one of the conductive drain paths, and an upper source pad electrically connected to one of the conductive power paths.

[0046] In some embodiments, the RDL laminate substrate may further include a lower gate pad electrically connected to the upper gate pad, a lower drain pad electrically connected to the upper drain pad, and a lower source pad electrically connected to the upper source pad, and the contacts may include a gate contact mounted on the lower gate pad, a drain contact mounted on the lower drain pad, and a source contact mounted on the lower source pad.

[0047] In some embodiments, when the RF amplifier is viewed from above, at least one of the gate contacts may be located outside the coverage area of ​​the group 3 nitride-based RF transistor amplifier die.

[0048] In some embodiments, the group III nitride-based RF transistor amplifier die may include a plurality of parallel drain fingers and the conductive drain path is one of a plurality of drain paths, and at least two conductive drain paths may be located below each of the conductive drain fingers. In these embodiments, the at least two conductive drain paths located below a first of the conductive drain fingers may define a first axis, and the at least two conductive drain paths located below a second of the conductive drain fingers adjacent to the first of the conductive drain paths may define a second axis, and when the group III nitride-based RF transistor amplifier die is viewed from above, the conductive gate path may be located between the first axis and the second axis.

Implementation Method

[0049] Cross-Reference to Related Applications This application claims priority to U.S. Provisional Patent Application No. 63 / 004,985, filed April 3, 2020, pursuant to 35 USC § 119, the entire contents of which are incorporated herein by reference.

[0050] Conventional RF transistor amplifiers based on group III nitrides (such as RF transistor amplifier 100 of Figures 1A and 1B) can use bonding wires to connect the RF transistor amplifier die 110 to the gate lead 172 and the drain lead 174. These bonding wires have inherent inductance that can be used to implement some inductors in the impedance matching and / or harmonic termination circuitry of the RF transistor amplifier. The amount of inductance provided can be varied by changing the length and / or cross-sectional area (e.g., diameter) of the bonding wire, so that the bonding wire provides a desired inductance. Unfortunately, as applications extend to higher frequencies, the inductance of the bonding wire may exceed the inductance required by one of the impedance matching and / or harmonic termination circuitry. When this occurs, very short and / or bonding wires with large cross-sectional areas can be used to attempt to reduce the inductance to a suitable level. However, very short bonding wires may be difficult to solder in the proper location, which increases manufacturing costs and / or leads to higher device failure rates. Large junction lines require larger gate and drain pads on the RF transistor amplifier die, increasing the overall die size, which is undesirable. Furthermore, in some higher frequency applications, even very short junction lines with large cross-sectional areas can have excessive inductance, preventing the matching network from properly terminating second or third harmonics, for example. While RF transistor amplifiers can be implemented as MMIC devices to avoid the problem of excessive inductance in the junction lines, MMIC RF amplifiers are more expensive to manufacture and can only be used within the frequency range of the matching circuit, reducing flexibility.

[0051] According to an embodiment of the present invention, a group III nitride-based RF transistor amplifier is provided, comprising an RF transistor amplifier die, wherein at least one of its source terminal and its drain terminal and / or its gate terminal is located on the rear side of the RF transistor amplifier die. The gate, drain, and source terminals may all be connected to corresponding gate, drain, and source pads on an interconnect structure using conductive contacts (such as conductive bumping technology (e.g., solder bumps), die attachment materials, conductive epoxy resin, or other low-inductance electrical connections). In some embodiments, the RF transistor amplifier may not include any bonding wires. The RF amplifier die may include one or more conductive gate paths and / or one or more conductive drain paths, which are used to connect a gate bus and / or a drain bus located on the top side of the RF transistor amplifier die to their respective gate and drain terminals located on the rear side of the RF transistor amplifier die. The length of the conductive path can be a small fraction (e.g., 10% to 30%) of the length of a conventional junction line, thus significantly reducing the inductance of the connections between the gate and drain buses and the interconnect structure. Therefore, impedance matching and / or harmonic termination circuitry can be configured to have the desired inductance without implementing the RF transistor amplifier as an MMIC device. Consequently, the size of the RF transistor amplifier die can be reduced without compromising performance, and the RF transistor amplifier die can be used in applications across various frequency bands because frequency-specific portions of the device (e.g., matching circuitry) can be implemented as discrete chips or circuits.

[0052] Furthermore, wire bonding devices typically used in mass production may have a tolerance of + / -1 mil, meaning that the length of any given wire bond can vary by up to 4 mils (i.e., + / -1 mil at each end of the bonded wire). For high-frequency applications, the inductance variation associated with a 4-mil bonded wire can be significant; therefore, if the bonded wire is 1 to 2 mils shorter or longer than the nominal length, the performance of the matching circuitry will be degraded. Forming the gate and drain terminals on the rear side of the device and using contacts to connect these terminals to corresponding pads on the interconnect structure can substantially eliminate this variation, resulting in improved performance.

[0053] According to some embodiments of the present invention, an RF transistor amplifier is provided, comprising an interconnect structure and a group III nitride-based RF transistor amplifier die mounted on top of the interconnect structure. The group III nitride-based RF transistor amplifier die includes a semiconductor layer structure. A plurality of unit transistors are provided in an upper portion of the semiconductor layer structure, and a gate terminal, a drain terminal, and a source terminal are provided on a lower surface of the semiconductor layer structure adjacent to the interconnect structure. The gate terminal is electrically connected to the unit transistor through one or more conductive gate paths, the drain terminal is electrically connected to the unit transistor through one or more conductive drain paths, and the source terminal is electrically connected to the unit transistor through one or more conductive power paths. The gate, drain, and source paths can extend completely through the semiconductor layer structure.

[0054] In some embodiments, the RF transistor amplifier may include a group III nitride-based RF transistor amplifier die having a semiconductor layer structure having a source region therein, conductive electrode paths extending through the semiconductor layer structure, and an additional conductive path. A first end of one of the additional conductive paths is connected to a first external circuit, and a second opposite end of one of the additional conductive paths is connected to a first matching circuit. The additional conductive path may be a conductive gate path connected to a gate electrode or a conductive drain path connected to a drain electrode of the RF transistor amplifier die.

[0055] In other embodiments, the RF transistor amplifier may include a group 3 nitride-based RF transistor amplifier die, which includes a semiconductor layer structure and a conductive path extending through the semiconductor layer structure. A first impedance matching circuit is coupled between a first end of the conductive path and a first external electrical connection, and a first harmonic termination circuit is coupled between a second opposite end of an additional conductive path and a second external electrical connection.

[0056] In other embodiments, the RF transistor amplifier includes: (1) an interconnect structure, such as (for example) a redistribution layer ("RDL") laminate, a printed circuit board, an interposer, or a substrate having a dielectric layer or pattern on one surface and conductive traces on the dielectric pattern / layer opposite to a substrate; and (2) a group III nitride-based RF transistor amplifier die located on a top surface of the interconnect structure. The group III nitride-based RF transistor amplifier die includes: a semiconductor layer structure having a plurality of unit cell transistors in an upper portion; a conductive power electrode path, a conductive gate path, and a conductive drain path, each of which extends through the semiconductor layer structure; and a plurality of contacts located on a bottom surface of the RDL laminate.

[0057] Embodiments of the present invention will now be discussed in further detail with reference to the accompanying drawings.

[0058] Figures 2A to 2G depict a group III nitride-based RF transistor amplifier 200 according to a specific embodiment of the present invention. Specifically, Figure 2A is a schematic side view of the group III nitride-based RF transistor amplifier 200. Figure 2B is a schematic cross-sectional view of an RF transistor amplifier die 210 taken along line 2B-2B of Figure 2A, which is a portion of the group III nitride-based RF transistor amplifier 200 of Figure 2A. Figures 2C to 2F are schematic cross-sectional views of the RF transistor amplifier die 210 taken along lines 2C-2C to 2F-2F of Figure 2B, respectively. Finally, Figure 2G is a schematic bottom view of the RF transistor amplifier die 210.

[0059] As shown in FIG2A, the group III nitride-based RF transistor amplifier 200 includes an RF transistor amplifier die 210 mounted on the surface of an interconnect structure 270. The RF transistor amplifier die 210 has a top side 212 and a bottom side 214. The RF transistor amplifier die 210 includes a bottom-side metallization structure 220, a semiconductor layer structure 230, and a top-side metallization structure 240 stacked in sequence. The bottom-side metallization structure 220 includes a gate terminal 222, a drain terminal 224, and a source terminal 226. The RF transistor amplifier 200 may be a HEMT-based RF transistor amplifier, in which case the semiconductor layer structure 230 may include at least a channel layer and a barrier layer, as will be discussed in more detail with reference to FIGS. 2C and 2D. The top-side metallization structure 240 will be discussed in more detail with reference to FIG2B.

[0060] Interconnect structure 270 may include any structure electrically connected to RF transistor amplifier die 210 to provide one of the RF transistor amplifier die 210 suitable for mounting surfaces. In some cases, interconnect structure 270 may include an RDL laminate structure. An RDL laminate structure refers to a substrate having conductive layer patterns and / or conductive pathways for electrical and / or thermal interconnection. The RDL laminate structure may be manufactured using semiconductor processing techniques by depositing conductive and insulating layers and / or patterns on a substrate material and by forming pathways and copper routing patterns within the structure for signal transmission through the RDL laminate structure. Other interconnect structures 270 may be used instead, such as (e.g.) a printed circuit board (e.g., a multilayer printed circuit board), a metal core printed circuit board, or a ceramic substrate containing conductive pathways and / or pads. In other embodiments, interconnect structure 270 may include a metal flange having an insulating pattern on one of its top surfaces and conductive traces on the insulating layer providing electrical connections to gate terminal 222 and drain terminal 224. The source terminal 226 can be electrically connected to the metal flange via, for example, a conductive die-attachment material (such as solder). In some embodiments, an insulating pattern formed on the top surface of the metal flange can be a solder mask layer. In any case, it should be understood that the interconnect structure 270 can be any suitable mounting surface for the RF transistor amplifier die 210 that can form an electrical connection to the rear side 214 of the RF transistor amplifier die 210. More than one interconnect structure 270 can be provided in a stacked manner. The RF transistor amplifier die 210 can be mounted on the interconnect structure 270 by the die manufacturer (e.g., on an RDL laminate). In other cases, the RF transistor amplifier die 210 can be directly mounted in a package on a package substrate such as a metal flange, wherein dielectric and traces are formed on the metal flange, such that the metal flange can serve as the interconnect structure 270.

[0061] A gate pad 272, a drain pad 274, and a source pad 276 are provided on the top surface of the interconnect structure 270. Each of these pads 272, 274, and 276 may include, for example, an exposed copper pad. A gate terminal 222 may overlap with the gate pad 272 along a first vertical axis extending perpendicular to the top surface of the semiconductor layer structure 230, a drain terminal 224 may overlap with the drain pad 274 along a second vertical axis extending perpendicular to the top surface of the semiconductor layer structure 230, and a source terminal 226 may overlap with the source pad 276 along a third vertical axis extending perpendicular to the top surface of the semiconductor layer structure 230. "Overlap" means that the axis extends through both the terminal and its corresponding pad, and "perpendicular" means a direction perpendicular to a main surface of the semiconductor layer structure 230. Each overlapping terminal and pad (e.g., gate terminal 222 and gate pad 272) can be physically and electrically connected to each other by any suitable contact (which includes, for example, a conductive bump (e.g., a solder bump or conductive epoxy), a die-attach material, or the like (not shown)). It should be understood that any type of bump grid array technology can be used to connect gate terminal 222, drain terminal 224, and source terminal 226 to their respective gate pad 272, drain pad 274, and source pad 276, while facilitating heat dissipation from the RF amplifier die 210. The interconnect structure 270 may further include a plurality of heat dissipation structures 290. In the depicted embodiment, the heat dissipation structure 290 includes a metal-filled (or partially metal-filled) passage extending through the interconnect structure 270. Heat generated in the RF transistor amplifier die 210 can be dissipated through the metal-filled passage 290.

[0062] The RF transistor amplifier die 210 may include a HEMT RF transistor amplifier based on a group III nitride, comprising a plurality of unit transistors 216 electrically connected in parallel with each other. This is best seen in FIG2B, which schematically depicts a cross-section through a top-side metallization structure 240 of the RF transistor amplifier die 210. As shown in FIG2B, the top-side metallization structure 240 includes a gate bus 242 and a drain bus 244, a plurality of gate fingers 252, a plurality of drain fingers 254, and a plurality of source fingers 256, all of which may be formed on an upper surface of a semiconductor layer structure 230. The gate bus 242 and the gate fingers 252 are portions of a gate electrode of the RF transistor amplifier die 210. The gate bus 242 and the gate fingers 252 may be implemented as a first monolithic metal pattern. Drain bus 244 and drain finger 254 are portions of the drain electrode of the RF transistor amplifier die 210 and can be implemented as a second monolithic metal pattern. Gate finger 252 can be formed of a material (such as Ni, Pt, Cu, Pd, Cr, W and / or WSiN) capable of forming a Schottky contact with a group III nitride-based semiconductor material. Drain finger 254 and source finger 256 can contain a metal, such as TiAlN, capable of forming an ohmic contact with a group III nitride-based material. A dielectric layer (or series of dielectric layers) that helps to isolate the gate metallization 242, 252, drain metallization 244, 254 and source metallization 256 from each other is not shown in Figure 2B to better illustrate the elements of the top-side metallization structure 240. A conductive gate bonding pad 243 and / or a conductive drain bonding pad 253 may be provided on the upper surface of the RF transistor amplifier die 210 as appropriate. Gate bonding pad 243 is electrically connected to gate terminal 222, and drain bonding pad 253 is electrically connected to drain terminal 224.

[0063] Figure 2B also shows one of the unit cell transistors 216. As shown in the figure, the unit cell transistor 216 includes a gate finger 252, a drain finger 254, and a source finger 256, and the portion beneath the semiconductor layer structure 230. Since all the gate fingers 252 are electrically connected to a common gate bus 242, all the drain fingers 254 are electrically connected to a common drain bus 244, and all the source fingers 256 are electrically connected together via a power supply path 266 (discussed below) and a source terminal 226, it can be seen that all the unit cell transistors 216 are electrically connected together in parallel.

[0064] The unit transistor 216 can be a HEMT device. For example, suitable structures for HEMT devices based on Group III nitrides that can utilize embodiments of the present invention are described in the following: U.S. Patent Publication No. 2002 / 0066908A1, published June 6, 2002, entitled "Aluminum Gallium Nitride / Gallium Nitride High Electron Mobility Transistors Having A Gate Contact On A Gallium Nitride Based Cap Segment And Methods Of Fabricating Same"; U.S. Patent Publication No. 2002 / 0167023A1, published November 14, 2002, entitled "Group-III Nitride Based High Electron Mobility Transistor (HEMT) With Barrier / Spacer Layer"; and U.S. Patent Publication No. 2004 / 0061129, published April 1, 2004, entitled "Nitride-Based Transistors And Methods Of Fabrication Thereof Using Non-Etched Contact Recesses". The entire contents of U.S. Patent No. 7,906,799, issued March 15, 2011, entitled "Transistors With A Protective Layer And A Low-Damage Recess," and U.S. Patent No. 6,316,793, issued November 13, 2001, entitled "Nitride Based Transistors On Semi-Insulating Silicon Carbide Substrates," are incorporated herein by reference.

[0065] As further shown in Figure 2B, a plurality of metallized pathways are provided extending from the top metallization structure 240 through the semiconductor layer structure 230. The metallized pathways include a metallized gate pathway 262, a metallized drain pathway 264, and a metallized source pathway 266. The metallized gate pathway 262 physically and electrically connects the gate bus 242 to the gate terminal 222, the metallized drain pathway 264 physically and electrically connects the drain bus 244 to the drain terminal 224, and the metallized source pathway 266 physically and electrically connects the source finger 256 to the source terminal 226.

[0066] As further shown in FIG2B, the conductive gate path 262 and / or conductive drain path 264 may be offset from the conductive power path 266 (along the Y direction of FIG2B). Specifically, two or more conductive power paths 266 may be formed in each source finger 256, and the conductive power path 266 formed in a particular source finger 256 may (at least substantially) extend along a horizontal (X direction) axis. Thus, the conductive power paths 266 contained in each source finger 256 may define their respective horizontal axes in the view of FIG2B, wherein line 2C-2C in FIG2B illustrates one such horizontal axis. As shown in FIG2B, the conductive gate path 262 and / or conductive drain path 264 may be positioned between these horizontal axes (e.g., opposite to alignment along these horizontal axes). In some cases, the conductive gate path 262 and / or conductive drain path 264 may be positioned along a longitudinal axis defined by the respective drain finger 254. Offsetting the conductive gate path 262 and conductive drain path 264 from the conductive power path 266 increases the distance between conductive paths 262, 264, and 266, which reduces the likelihood of wafer or die breakage due to mechanical weaknesses. This configuration also reduces parasitic gate-to-source and / or parasitic source-to-drain couplings that can occur between the various paths 262, 264, and 266. These parasitic couplings can lead to gain loss and / or instability.

[0067] Referring to Figures 2C and 2D, the semiconductor layer structure 230 includes a plurality of semiconductor layers. In the depicted embodiment, a total of two semiconductor layers are shown, namely, a channel layer 234 and a barrier layer 236 on the top side of one of the channel layers 234. The semiconductor layer structure 230 may include additional semiconductor and / or non-semiconductor layers. For example, the semiconductor layer structure 230 may include a growth substrate 232 on which other semiconductor layers are grown. The growth substrate 232 may include, for example, a 4H-SiC or 6H-SiC substrate. In other embodiments, the growth substrate may include a different semiconductor material (e.g., silicon or a group III nitride-based material, GaAs, ZnO, InP) or a non-semiconductor material (e.g., sapphire).

[0068] SiC is a group III nitride with a more compact lattice match than sapphire (Al2O3), and it is a very common substrate material for group III nitride devices. The tighter lattice match of SiC results in group III nitride films of higher quality than those typically used on sapphire. SiC also has very high thermal conductivity, meaning that the total output power of group III nitride devices on silicon carbide is generally not as limited by heat dissipation from the substrate as the same devices formed on sapphire. Furthermore, the availability of semi-insulating SiC substrates provides device isolation and reduces parasitic capacitance.

[0069] Buffer, nucleation, and / or transition layers (not shown) may be provided on the growth substrate 232 below the channel layer 234. For example, an AlN buffer layer may be included to provide a suitable crystal structure transition between the SiC growth substrate 232 and the remainder of the semiconductor layer structure 230. Alternatively, strain balancing transition layers may be provided, such as those described in U.S. Patent Publication 2003 / 0102482A1, published June 5, 2003, entitled "Strain Balanced Nitride Heterojunction Transistors And Methods Of Fabricating Strain Balanced Nitride Heterojunction Transistors," the disclosure of which is incorporated herein by reference as if fully described herein.

[0070] In some embodiments, the channel layer 234 is a Group III nitride material (such as AlxGa1-xN, where 0 ≤ x < 1), provided that the energy at the conduction band edge of the channel layer 234 is lower than the energy at the conduction band edge of the barrier layer 236 at the interface between the channel layer 234 and the barrier layer 236. In a particular embodiment of the invention, x = 0, which indicates that the channel layer 234 is gallium nitride ("GaN"). The channel layer 234 may also be other Group III nitrides, such as InGaN, AlInGaN, or the like. The channel layer 234 may be undoped or unintentionally doped and may be grown to a thickness greater than, for example, about 20 Å. The channel layer 234 may also be a multilayer structure, such as a superlattice or a combination of GaN, AlGaN, or the like.

[0071] The channel layer 234 may have a band gap smaller than at least a portion of the band gap of the barrier layer 236, and the channel layer 234 may also have an electron affinity greater than that of the barrier layer 236. In a particular embodiment, the barrier layer 236 is an AlN, AlInN, AlGaN, or AlInGaN having a thickness between about 0.1 nm and about 10 nm or greater. In a particular embodiment, the barrier layer 236 is sufficiently thick and has a sufficiently high Al composition and is doped to induce a significant carrier concentration at the interface between the channel layer 234 and the barrier layer 236.

[0072] The barrier layer 236 may be a group III nitride and may have a band gap greater than that of the channel layer 234 and an electron affinity less than that of the channel layer 234. In certain embodiments, the barrier layer 236 is undoped or doped with an n-type dopant at a concentration of less than about 10¹⁹ cm⁻³. In some embodiments of the invention, the barrier layer 236 is AlxGa¹⁻¹⁻¹⁻¹N, where 0 < x < 1. In certain embodiments, the aluminum concentration is about 25%. However, in other embodiments of the invention, the barrier layer 236 comprises AlGaN having an aluminum concentration between about 5% and about 100%. In certain embodiments of the invention, the aluminum concentration is greater than about 10%.

[0073] Due to the bandgap difference between the barrier layer 236 and the channel layer 234 and the piezoelectric effect at the interface between the barrier layer 236 and the channel layer 234, a two-dimensional electron gas (2DEG) is induced in the channel layer 234 at a junction between the channel layer 234 and the barrier layer 236. The 2DEG acts as a highly conductive layer that allows conduction between the source region and its associated drain region of each unit cell transistor 216, wherein the source region is a portion of the semiconductor layer structure 230 directly below the source finger 256 and the drain region is a portion of the semiconductor layer structure 230 directly below the corresponding drain finger 254.

[0074] An interlayer insulating layer 238 is formed on the gate finger 252, the drain finger 254, and the source finger 256. The interlayer insulating layer 238 may contain a dielectric material such as SiN, SiO2, etc.

[0075] Figures 2C to 2G illustrate the metal-plated gate path 262, the metal-plated drain path 264, and the metal-plated source path 266 in more detail. As shown in Figures 2C to 2F, the metal-plated gate path 262, the metal-plated drain path 264, and the metal-plated source path 266 can extend completely through the semiconductor layer structure 230 to physically and electrically connect the gate bus 242 to the gate terminal 222, physically and electrically connect the drain bus 244 to the drain terminal 224, and physically and electrically connect the source finger 256 to the source terminal 226.

[0076] In some embodiments, the metal-plated gate path 262, the metal-plated drain path 264, and the metal-plated source path 266 may all have the same shape and horizontal cross-section (i.e., a cross-section obtained by passing through a plane parallel to one of the main surfaces of the semiconductor layer structure 230). For example, all paths 262, 264, and 266 may be substantially cylindrical or elliptical paths with the same diameter, or they may all be frustoconical paths with the same diameter when measured at the same height above the bottom surface 214 of the RF amplifier die 210. This configuration allows all paths 262, 264, and 266 to be easily formed in a single manufacturing step. In other embodiments, the metal-plated gate path 262 and / or the metal-plated drain path 264 may have a larger cross-sectional area than the metal-plated source path 266. This technique can be used to further reduce the inherent inductance of the metal-plated gate path 262 and / or the metal-plated drain path 264 according to specific application requirements.

[0077] The metal-plated gate passage 262, the metal-plated drain passage 264, and the metal-plated source passage 266 can each be implemented by forming an opening through the semiconductor layer structure (e.g., by anisotropic etching) and then by depositing a metal plating layer coating the sidewalls of the opening. In some applications, the metal can completely fill the opening, making the metal-plated passage a metal-filled passage. However, in many applications, the RF transistor amplifier die 210 can operate over a wide temperature range (due to outdoor applications and / or the high heat generated within the RF transistor amplifier die during device operation), which can be attributed to the significantly different coefficients of thermal expansion of the metal and semiconductor materials, resulting in high stress levels in the device. In such cases, the center of the metal-plated passages 262, 264, and 266 can be left open (i.e., air-filled) to reduce stress caused by thermal cycling.

[0078] The cross-sectional areas of channels 262, 264, and 266 may be selected, for example, based on heat dissipation considerations and / or the required series inductance. Whether a metal-plated channel will dissipate more or less heat than a metal-plated channel through which it penetrates the semiconductor material will depend on various considerations, including the heat dissipation quality of the semiconductor material and metal used, the thickness of the metal plating, the (some) cross-sectional areas of the channel, etc. Generally speaking, metals such as copper are more efficient at heat dissipation than group III nitride-based semiconductor materials and silicon carbide semiconductor materials, but any central air-filled opening in the channel will be less efficient at heat dissipation than the semiconductor material.

[0079] As shown in FIG2G, the gate terminal 222, drain terminal 224, and source terminal 226 may each include a metallization pattern on a lower surface of the semiconductor layer structure 230. Gaps may be provided between the gate terminal 222 and the drain terminal 224, and between the drain terminal 224 and the source terminal 226, to electrically insulate the gate terminal 222, drain terminal 224, and source terminal 226 from each other. When the RF transistor amplifier die 210 is viewed from the rear side, these gaps may expose the growth substrate 232. In some embodiments, an insulating pattern (not shown) may be deposited in the gaps. The gate path 262, drain path 264, and source path 266 are each physically and electrically connected to their respective gate terminal 222, drain terminal 224, and source terminal 226.

[0080] FIG3 is a schematic top view of one exemplary embodiment of the interconnect structure 270 included in the RF amplifier 200 of FIGS. 2A to 2G. As discussed above, the interconnect structure 270 may include, for example, an RDL laminate structure or a multilayer printed circuit board. Gate pad 272, drain pad 274 and source pad 276 are implemented on one of the upper surfaces of the interconnect structure 270. Each of these pads 272, 274, 276 may include a respective metal pattern (e.g., a copper pattern). Gate pad 272, drain pad 274 and source pad 276 may have the same or similar size and shape as the respective gate terminal 222, drain terminal 224 and source terminal 226 on the RF amplifier die 210. A plurality of metal-filled passages 290 (or alternatively, a solid conductive block) may be provided under the source pad 276, extending through the interconnect structure 270. The metal-filled path (or conductive block) 290 can act as a heat sink, which will be generated in the RF amplifier die 210 and conduct heat to the bottom side of the interconnect structure 270, whereby the heat is dissipated to the surrounding environment or to a heat sink in a subsequent structure (such as a printed circuit board). As also shown in FIG3, in some embodiments, additional metal-filled paths 290 may be provided under the gate pad 272 and / or source pad 276 to provide additional heat dissipation.

[0081] As further shown in Figure 3, a plurality of additional components 281 may be mounted on interconnect structure 270. These components 281 may include, for example, passive RF components such as integrated passive devices or printed circuit boards, which include resistors, capacitors, and / or inductors. These passive components may form input and / or output matching circuits for (1) matching the impedance of the input and / or output of the RF transistor amplifier chip 210 to the impedance at the fundamental frequency of the respective input and output RF transmission lines or (2) terminating harmonics that may exist at the fundamental frequency of the input or output of the RF transistor amplifier chip 210. Some matching circuit systems may also be implemented in interconnect structure 270. For example, interconnect structure 270 may include a meandering or spiral trace pattern (not shown) implementing inductors included in the input and / or output matching circuits. Other RF circuit systems such as transmit / receive switches, circulators, filters, or the like may also be mounted on interconnect structure 270.

[0082] One advantage of having the gate terminal 222, drain terminal 224, and source terminal 226 all located on the same side of the RF amplifier die 210 is that it allows for more wafer-level processing, resulting in more efficient manufacturing. As shown in FIG4A, in many applications, a plurality of RF transistor amplifier dies 210 are fabricated from a single semiconductor wafer 201. The semiconductor wafer 201 may include, for example, a silicon carbide wafer, and a plurality of gallium nitride-based epitaxial layers may be grown on the silicon carbide wafer 201 using semiconductor epitaxial growth techniques. Next, conventional semiconductor processing techniques such as metal and insulating material deposition, photolithography, masking, and / or etching are performed to form a bottom-side metallization structure 220 and a top-side metallization structure 240, as well as conductive gate paths 262, conductive drain paths 264, and conductive power electrode paths 266, to form a plurality of RF transistor amplifier chips 210 in a silicon carbide wafer 201 (wherein a portion of the silicon carbide wafer 201 forms the growth substrate 232 for each individual RF transistor amplifier chip 210). Finally, the wafer 201 is diced along horizontal and vertical "cut" paths (not shown) to monolithize the individual RF transistor amplifier chips 210. It should be noted that Figure 4A is an illustrative diagram, and typically significantly more RF transistor chips 210 are formed on a single wafer, and the RF transistor chips 210 are typically positioned in a more dense manner.

[0083] FIG4B is a schematic cross-sectional view of one of the RF amplifier chips 210 included in the wafer 201 of FIG4A. As shown in FIG4B, contacts 280 (e.g., solder bumps) are attached to the gate terminal 222, the drain terminal 224, and the source terminal 226. These contacts 280 can be used to mechanically and electrically attach the RF transistor amplifier chip 210 to an interconnect structure (not shown), such as interconnect structure 270. Although not shown in FIG4A and FIG4B, the contacts 280 can be applied as part of a wafer-level processing step, i.e., before the semiconductor wafer 201 is diced into a plurality of individual RF transistor amplifier chips 210. This wafer-level processing is faster and more efficient than applying the contacts 280 to the individual RF transistor amplifier chips 210. Furthermore, because gate terminal 222 and drain terminal 224 can be electrically connected to their corresponding gate pad 272 and drain pad 274 on interconnect structure 270 in the same processing step used to connect source terminal 226 to source pad 276 on interconnect structure 270 (see Figures 2A and 3), all electrical connections to RF transistor amplifier die 210 can be established in a single processing step. In contrast, when using a conventional RF transistor amplifier die (e.g., RF transistor amplifier die 110 of Figures 1A and 1B), an additional time-consuming line bonding process is used to form electrical connections to gate terminal 142 and drain terminal 144. Eliminating these processing steps significantly simplifies the manufacturing process.

[0084] As described above, providing conductive gate path 262 and conductive drain path 264 results in all three gate terminals 222, drain terminal 224, and source terminal 226 of the RF transistor amplifier die 210 being located on the same surface of the die and therefore in the same plane. This allows for the use of various types of wafer-level packaging technologies, such as, for example, various fan-in, fan-out, and interposer topologies. The RF transistor amplifier die according to embodiments of the invention can be directly mounted on interconnect structures or interposer structures (such as RDL laminates or interposers, which may be a custom RDL laminate) using contacts such as, for example, conductive bumps or conductive die attachment materials. When the RF transistor amplifier die according to embodiments of the invention is mounted on, for example, an RDL laminate or interposer, contacts can be pre-mounted on the bottom surface of the RDL laminate / interposer, which allows end users to easily mount the RF amplifier die on other structures. Furthermore, as mentioned above, providing conductive gate path 262 and conductive drain path 264 reduces variations in electrical path length, which improves performance and can reduce or eliminate the need for expensive and time-consuming wire bonding processes. Reducing or eliminating the need for wire bonding also allows for smaller die size in some applications (where the size of the wire bonding pads contributes to the die size), thus the RF transistor amplifier die according to embodiments of the present invention can also exhibit increased integration density. Therefore, the RF amplifier die according to embodiments of the present invention can exhibit improved product assembly consistency, higher yield, improved product integration, reduced cost, and improved RF performance, especially for products operating at high frequencies such as millimeter wave frequencies.

[0085] The techniques disclosed herein are particularly advantageous in higher frequency applications because the inductance required in the matching circuit can be much lower in such applications, thus avoiding the addition of excessive inductance using conventional bonding wires. Furthermore, the tolerance for bonding wire length can have a greater impact at higher frequencies, and in high-frequency applications (especially at lower power), the size of the bonding pads can influence the die size. In some embodiments, any RF transistor amplifier die disclosed herein can be configured to operate at frequencies greater than 1 GHz. In other embodiments, such RF transistor amplifier dies can be configured to operate at frequencies greater than 2.5 GHz. In other embodiments, such RF transistor amplifier dies can be configured to operate at frequencies greater than 3.1 GHz. In additional embodiments, such RF transistor amplifier dies can be configured to operate at frequencies greater than 5 GHz. In some embodiments, these RF transistor amplifier chips can be configured to operate in at least one of the frequency bands of 2.5 GHz to 2.7 GHz, 3.4 GHz to 4.2 GHz, or 5.1 GHz to 5.8 GHz, or a sub-band thereof.

[0086] Figures 4C to 4E illustrate exemplary packaged RF transistor amplifiers including RF transistor amplifier chips according to embodiments of the present invention. Next, Figures 5A to 5C illustrate how the planarization terminal configuration of the RF transistor amplifier chip according to embodiments of the present invention also allows the RF transistor amplifier chip to be used in various different wafer-level package topologies.

[0087] Figure 4C is a schematic cross-sectional view of an RF transistor amplifier 300 packaged in an open-cell package, including the RF transistor amplifier die 210 of Figure 4B. As shown in Figure 4C, the open-cell package 310 includes a substrate 320 (such as a metal flange) and an upper housing 330, which may include, for example, sidewalls 332 and a cap 334. In an exemplary embodiment, the substrate 320 may be a multilayer copper / molybdenum / copper metal flange, including a core molybdenum layer and copper cladding layers on two main surfaces of the core molybdenum layer. The ceramic sidewalls 332 and the cap 334 may be formed of, for example, Al2O3. The ceramic cap 334 may be bonded to the ceramic sidewalls 332 using epoxy resin adhesive. The ceramic sidewalls 332 may be attached to the metal substrate 320 by firing. The RF transistor amplifier die 210 can be mounted on an interconnect structure 270 using, for example, conductive contacts (such as bumps 280 shown in FIG. 4B), and the interconnect structure 270 can be mounted on a substrate 320 using, for example, a conductive die attachment material. The substrate 320 can dissipate heat from the heat dissipation structure 290 in the interconnect structure 270 to the outside of the ceramic package 310.

[0088] Additional components 350, 360 are mounted on interconnect structure 270. These additional components may include, for example, input matching component 350 and output matching component 360 for impedance matching at the fundamental frequency and / or terminating intermodulation products to ground. As discussed above, these matching components 350, 360 may be passive RF components comprising, for example, resistors, capacitors, and / or inductors implemented in an integrated passive device or printed circuit board. Conductive leads 340 extend through housing 310 to allow RF transistor amplifier 300 to be connected to an external device / circuit / power supply. In the depicted embodiment, wire connection 370 is used to connect conductive leads 340 to passive RF components 350, 360 on interconnect structure 270. However, it should be understood that wire connection 370 may be omitted in other embodiments and different electrical connections may be used. An RF signal input to an RF transistor amplifier 300 via a first lead 340-1 can reach an input matching circuit 350 via a wire junction 370-1 and from the input matching circuit 350 to a gate terminal 222 of an RF transistor amplifier chip 210 (see Figure 4B). The amplified output RF signal can be transmitted from the drain terminal 224 of the RF transistor amplifier chip 210 to an output matching circuit 360 and from the output matching circuit 360 to a junction line 370-2, wherein the RF signal is output through lead 340-2.

[0089] FIG4D is a schematic cross-sectional view of a packaged RF transistor amplifier 400 containing the RF transistor amplifier die 210 of FIG4B in a plastic overmolded package. As shown in FIG4D, the packaged RF transistor amplifier 400 includes a substrate 420 at least partially surrounded by a plastic overmolded part 410, such as a metal heat sink as part of a lead frame or metal block. The RF transistor amplifier die 210 is mounted on an interconnect structure 270 using, for example, conductive bumps 280 shown in FIG4B, and the interconnect structure 270 is mounted on the substrate 420. The substrate 420 may include, for example, a metal substrate capable of dissipating heat through the heat dissipation structure 290 in the interconnect structure 270. Additional components 450, 460 are mounted on the interconnect structure 270. These additional components may include, for example, an input matching component 450 and an output matching component 460 for impedance matching at the fundamental frequency and / or terminating intermodulation products to ground. As discussed above, these matching components may be passive RF components that include (at least partially) resistors, capacitors, and / or inductors implemented in, for example, integrated passive devices or printed circuit boards. Conductive leads 440 extend through the plastic overlay molding 410 to allow the RF transistor amplifier 400 to be connected to an external device / circuit / power supply. In the depicted embodiment, wire connections 470 are used to connect the conductive leads 440 to passive RF components 450, 460 on the interconnect structure 270, but wire connections 470 may be omitted in other embodiments.

[0090] Figure 4E is a schematic cross-sectional view of a packaged RF transistor amplifier 300A containing the RF transistor amplifier die of Figure 4B in a printed circuit board-based package. The packaged RF transistor amplifier 300A is very similar to the packaged RF transistor amplifier 300 discussed above with reference to Figure 4C, except that the leads 340-1, 340-2 of the packaged RF transistor amplifier 300 are replaced by a printed circuit board 322 containing traces 342-1, 342-2 serving as input and output leads. The printed circuit board 322 may be attached to a metal substrate 320 via, for example, a conductive adhesive. The printed circuit board 322 includes a central opening, and interconnect structures 270 are mounted in this opening on the substrate (e.g., a metal flange) 320. The RF transistor die 210 and mating networks 350-1, 350-2, 360-1, 360-2 are mounted on the interconnect structures 270.

[0091] It should be understood that any RF transistor amplifier according to the embodiments of the invention discussed herein can be mounted in a package such as the open-mouth and overmolded package shown in Figures 4C to 4E. Therefore, the RF transistor die 210 and interconnect structure 270 shown in Figures 4C to 4E can be replaced by the RF transistor die and interconnect structure according to any embodiment of the invention discussed herein to provide numerous further embodiments of the packaged RF transistor amplifier. Depending on the embodiment, the packaged RF transistor amplifier may include a monolithic microwave integrated circuit (MMIC) as the RF transistor amplifier die, wherein the RF transistor amplifier die incorporates multiple discrete circuits into a single integrated die. Additionally and / or alternatively, the package may include multiple RF transistor amplifier dies connected in series in one path to form a multi-stage RF transistor amplifier and / or multiple RF transistor amplifier dies disposed in multiple paths (e.g., in parallel) to form an RF transistor amplifier (such as in a multi-stage amplifier configuration) with the multiple transistor amplifier dies and multiple paths. In some embodiments, the packaged RF transistor amplifier may include an RF transistor amplifier die according to an embodiment of the present invention having a conductive gate path and / or a conductive drain path providing electrical connections to a rear-side interconnect structure, and a conventional RF transistor amplifier die having a gate and drain terminal connected to other structures via wire bonding, such as the RF transistor die 110 of FIG1A.

[0092] FIG. 5A is a schematic cross-sectional view of an RF transistor amplifier 500 according to one embodiment of the present invention, which includes an RF transistor amplifier die 210 mounted on an RDL laminate structure 510 in a fan-in topology. As is known in the art, integrated circuit chips can be mounted on and electrically connected to various underlying substrates using contacts such as conductive bumps or other conductive attachment mechanisms. Contacts provide electrical connections between terminals on the integrated circuit chip and corresponding electrical connection points (e.g., conductive pads) on the substrate. The substrate can be used to reconfigure the gate, drain, and source terminal configurations to, for example, align with terminals on another substrate.

[0093] As shown in Figure 5A, the RF transistor amplifier die 210 can be mounted on an RDL laminate structure 510. The RDL laminate structure 510 may include an upper gate terminal 522, an upper drain terminal 524, and an upper source terminal 526, which are aligned with their respective gate terminals 222, drain terminals 224, and source terminals 226 on the RF transistor amplifier die 210, such that the gate terminals 222, drain terminals 224, and source terminals 226 can be physically and electrically connected to their respective upper gate terminals 522, upper drain terminals 524, and upper source terminals 526 using, for example, conductive epoxy resin or bumps (not shown). The RDL laminate structure 510 further includes a lower gate terminal 532, a lower drain terminal 534, and a lower source terminal 536. As shown in Figure 5A, one or more conductive gate paths 542, conductive drain paths 544, and conductive power paths 546 are provided to electrically connect the upper gate terminal 522 to the lower gate terminal 532, the upper drain terminal 524 to the lower drain terminal 534, and the upper source terminal 526 to the lower source terminal 536. The conductive gate paths 542 and conductive drain paths 544 are positioned inwardly on the bottom surface of the RF transistor amplifier die 210 of their respective gate terminals 222 and drain terminals 224. Conductive bumps 280 are attached to the lower gate terminal 532, lower drain terminal 534, and lower source terminal 536 to attach the RF transistor amplifier 500 to another substrate, such as a customer printed circuit board. The RF transistor amplifier 500 has a fan-in topology in which the RDL laminate structure 510 repositions the electrical connections of the gate, drain, and source (here, conductive bumps 280) to generally inward toward the center of the bottom surface of the RF transistor amplifier die 210.

[0094] Because the conductive bumps 280 are all located within the "coverage area" of the RF transistor amplifier die 210, the conductive bumps 280 can be applied to the bottom side of the wafer 201 shown in FIG. 4A during wafer-level processing, and then the wafer 201 can be diced after the conductive bumps 280 have been applied to the individual RF transistor amplifier dies 210. Individual RF transistor amplifier dies 210 are typically mounted on a large RDL laminate (or other interconnect structure), which is later diced to provide the plurality of RF transistor amplifiers 500 of FIG. 5A. However, it should be understood that in other embodiments, an RDL laminate may be bonded to the wafer 201 and the wafer 201 may subsequently be diced to provide the plurality of RF transistor amplifiers 500 of FIG. 5A.

[0095] FIG. 5B is a schematic cross-sectional view of an RF transistor amplifier 500' according to an embodiment of the present invention, which includes an RF transistor amplifier die 210 mounted on a redistributed substrate 510' in a fan-out topology. Except for the fan-out topology of the RDL laminate 510' contained therein, in which the lower gate terminal 532 and the lower drain terminal 534 are positioned at their respective gate terminals 222 and drain terminals 224 (when viewed from below), the RF transistor amplifier 500' is very similar to the RF transistor amplifier 500 discussed above. Conductive bumps (or other contacts) 280 are attached to the lower gate terminal 532, the lower drain terminal 534, and the lower source terminal 536 to attach the RF transistor amplifier 500' to another substrate, such as a customer printed circuit board.

[0096] FIG5C is a schematic cross-sectional view of an RF transistor amplifier 500" according to one embodiment of the present invention, which includes an RF transistor amplifier die 210 mounted on a custom interposer 510" in a fan-out topology. The interposer may be a custom RDL laminate design that allows for increased flexibility in the position relative to the contact 280. In addition, in some cases, passive circuitry such as capacitors or inductors (not shown) may be implemented within the interposer 510" to reduce the need for additional components 280 (see FIG3).

[0097] As discussed above, a group III nitride-based RF transistor amplifier typically includes one or more of an input impedance matching network, an input harmonic termination circuit, an output harmonic termination circuit, and an output impedance matching network. Each of these matching circuits may include one or more capacitors and / or inductors. In conventional RF transistor amplifiers, inductors are typically implemented at least partially using junction wires that form the RF transistor amplifier chip, various passive RF components, and the connections between the input / output leads.

[0098] As applications extend to higher frequencies, the inductance required for proper impedance matching and / or termination of specific harmonics (such as second and / or third harmonics) at the fundamental frequency typically decreases. In some applications, even with very short, thick junctions, the inductance of the junction can exceed the optimal inductance required by one or more matching circuits. If the inductance is greater than the optimal inductance of an impedance matching circuit, it increases the return loss of the RF transistor amplifier and / or reduces the operating bandwidth. If the inductance is greater than the optimal inductance of a harmonic termination circuit, it results in less reduction of associated harmonics, which degrades the efficiency, power, and / or gain performance of the RF transistor amplifier and increases the passive intermodulation distortion level, thus degrading other aspects of a communication system using an RF transistor amplifier.

[0099] The RF transistor amplifier based on Group III nitride according to embodiments of the present invention avoids the problem discussed above of having a series inductance greater than the amount required to provide optimal impedance matching. Specifically, in exemplary embodiments, the conductive gate and drain paths in the RF transistor amplifier according to embodiments of the present invention may have lengths of less than 8 mils and typically less than 5 mils, less than 4 mils, or even less than 3 mils. In contrast, the length of the gate and drain junction in conventional RF transistor amplifiers is typically at least 20 mils, and lengths of 30 mils or more are common. Thus, the inductance injected through the gate and drain paths can be a small fraction (e.g., possibly about 15% to about 20% of the inductance injected through the corresponding gate and drain junction) that ensures the inductance is less than or equal to the optimal inductance required by the various matching circuits of the Group III nitride-based RF transistor amplifier. Any additional inductance required to obtain the optimal inductance for the matching network can be added to the RF passive component or the like using inductor chips and / or inductor traces (or other structures) mounted on or implemented in the interconnect structure.

[0100] Mounting the gate and drain terminals on the bottom side of the device also reduces process variations during mass production, because ball joints used to solder the gate and drain terminals to the RF transistor amplifier die typically have a tolerance of + / -1 mil, resulting in variations in the length of each junction wire that can be up to 4 mils. Especially at higher frequencies, the inductance associated with this variation in junction wire length can be large and degrade the performance of the impedance matching circuit and thus the RF transistor amplifier. Furthermore, using conductive bumps, die-attach materials, or the like to connect the gate and drain terminals to corresponding gate and drain pads on the interconnect structure via a surface mount assembly allows for the use of smaller gate and drain terminals than those that would be used when junction wire connections are required. Therefore, in applications where the size of the gate and drain terminals affects the die size, the RF transistor amplifier die according to embodiments of the present invention can be smaller. Additionally, using ball joints instead of junction wires reduces manufacturing costs.

[0101] Another advantage provided by the conductive gate and drain paths included in the RF transistor amplifier according to an embodiment of the present invention is the greater flexibility in implementing the matching network, as connections to both the top and bottom of the conductive gate and drain paths can be formed. This feature of the RF transistor amplifier according to an embodiment of the present invention is schematically illustrated in the circuit diagram of FIG6. As shown in FIG6, the RF transistor amplifier 200 has a pair of RF inputs: a first "top" RF input directly connected to the gate of the RF transistor amplifier die 210 (i.e., directly connected to one of the upper gate terminals of the gate bus) and a "bottom" RF input connected to the bottom of the conductive gate path 262. These RF inputs are electrically connected to each other via an inductor Lgate-via representing the inherent inductance of the conductive gate path 262. Similarly, the RF transistor amplifier 200 has a pair of RF outputs: a first "top" RF output directly connected to the drain of the RF transistor amplifier die 210 (i.e., directly connected to the upper drain terminal of one of the drain buses), and a "bottom" RF output connected to the bottom of the conductive drain path 264. These RF outputs are electrically connected to each other via an inductor Ldrain-via representing the inherent inductance of the conductive drain path 264. This configuration provides increased flexibility to implement specific matching topologies.

[0102] For example, Figure 7A is a circuit diagram of a conventional RF transistor amplifier 600 having an input series impedance matching circuit, an input harmonic termination circuit for terminating harmonic frequencies (e.g., second harmonic or "2f0"), and an output shunt impedance matching circuit. The input series transmission line 610-1 and the output series transmission line 610-2 can be selected to provide appropriate impedance transformation between the RF transistor amplifier die 110 and the RF input (e.g., a gate lead) and output (e.g., a drain lead). These series transmission lines 610-1 and 610-2 can be considered as an extension of a transmission line matching network on a current substrate (not shown) (such as, for example, a customer printed circuit board), and the electrical width can be selected or configured to achieve the desired characteristic impedance for impedance matching. In conventional designs, such matching circuits are implemented through bonding wires (for inductors) and RF passive components (for capacitors). This configuration can lead to parasitic coupling between the input and output junction lines (which impairs RF performance), and as described above, at higher frequencies, the junction lines can inject too much inductance, which impairs impedance matching and / or harmonic termination.

[0103] Figures 7B and 7C illustrate two possible implementations of the matching topology shown in Figure 7A using an RF transistor amplifier die according to an embodiment of the present invention. As shown in Figure 7B, the RF input and input impedance matching network are connected to the upper gate terminal, while the input harmonic termination circuit can be coupled to the lower gate terminal. On the output side, the output impedance matching network is connected to the lower drain terminal as a shunt circuit, and the RF output is connected to the upper drain terminal. As shown in Figure 7C, in an alternative embodiment, the RF input and input impedance matching network are connected to the lower gate terminal, while the input harmonic termination circuit can be coupled to the upper gate terminal as a shunt circuit. On the output side, the output impedance matching network is connected to the upper drain terminal as a shunt circuit, and the RF output is connected to the lower drain terminal.

[0104] Figures 8A and 8B illustrate an RF transistor amplifier 700 according to a further embodiment of the present invention. Specifically, Figure 8A is a schematic cross-sectional view of the RF transistor amplifier 700 showing the circuit components included in the RF transistor amplifier 700 and the electrical interconnections between the circuit components, while Figure 8B is a circuit diagram of the RF transistor amplifier 700.

[0105] As shown in FIG8A, the RF transistor amplifier 700 includes an RF transistor die, which may be implemented, for example, using the RF transistor amplifier die 210 described above or any other RF transistor amplifier die according to embodiments of the present invention. The RF transistor amplifier die 210 is mounted on an RDL laminate structure 710, but in other embodiments other mounting structures such as multilayer printed circuit boards or integrated passive devices or "IPDs" may be used, including capacitors (and possibly other passive devices, such as inductors) formed on thin-film substrates such as silicon, alumina, or glass using semiconductor processing techniques. The RDL laminate structure 710 includes conductive regions 712 and dielectric regions 714. A plurality of RF passive components 720-1 to 720-4 are mounted on the RDL laminate structure 710. The interconnections between the RF transistor amplifier chip 210 and the RF passive components 720-1 to 720-4, and between the RF transistor amplifier chip 210 and the RF passive components 720-1 to 720-4, are formed using bonding wires 730 and through electrical connections in the RDL laminate structure 710.

[0106] Specifically, the RF input 740 and RF output 742 are formed as conductive structures in the RDL laminate structure 710. The RF input 740 can be connected to a first external circuit and the RF output 742 can be connected to a second external circuit. Focusing first on the input (left) side of FIG8A, a first bonding line 730-1 connects the RF input 740 to an upper terminal of an RF passive component 720-1, which includes a grounded shunt capacitor. The RF passive component 720-1 can be implemented as, for example, a capacitor IPD or a surface-mount capacitor chip. A lower terminal of the RF passive component 720-1 is connected to a ground region in the RDL laminate structure 710. The first bonding line 730-1 implements the inductor "Input_L2" shown in FIG8B, and the RF passive component 720-1 implements the shunt capacitor "Input_C1" shown in FIG8B. A second bonding line 730-2 connects the upper terminal of the RF passive component 720-1 to the upper gate terminal 243 of the RF transistor amplifier die 210. The second bonding line 730-2 implements the series inductor "Input_L1" shown in FIG. 8B. The inherent inductance of the conductive gate path 262 in the RF transistor amplifier die 210 is shown as inductor "Lvia_G" in FIG. 8B. The lower gate terminal 222 of the RF transistor amplifier die 210, connected to the lower end of the conductive gate path 262, is connected via a contact 280 to a conductive trace 716-1 on the RDL laminate structure 710. The conductive trace 716-1 connects to the RF passive component 720-2, which may include a capacitor and / or an inductor. The RF passive component 720-2 may be implemented as, for example, an IPD or a surface mount chip. The combination of conductive trace 716-1 and RF passive component 720-2 can implement the series CL circuit "Input_2f" shown in Figure 8B.

[0107] Focusing next on the output (right) side of FIG8A, a third bonding line 730-3 connects the drain terminal 253 on the RF transistor amplifier chip 210 to one of the upper terminals of the RF passive component 720-4, which forms a grounded shunt capacitor. The RF passive component 720-4 may be implemented as, for example, a capacitor IPD or a surface-mount capacitor chip. One of the lower terminals of the RF passive component 720-4 is connected to a ground region in the RDL laminate structure 710 via contact 280. The third bonding line 730-3 implements the series inductor "Output_L1" shown in FIG8B, and the RF passive component 720-4 implements the shunt capacitor "Output_C1" shown in FIG8B. A fourth bonding line 730-4 connects the upper terminal of the RF passive component 720-4 to the RF output 742 in the RDL laminate structure 710. The fourth bonding line 730-4 implements the series inductor "Output_L2" shown in FIG8B. The inherent inductance of the conductive drain path 264 in the RF transistor amplifier die 210 is shown as inductor "Lvia_D" in Figure 8B. The lower drain terminal 224 of the RF transistor amplifier die 210, connected to the lower end of the conductive drain path 264, is connected via a contact 280 to a conductive trace 716-2 on the RDL laminate structure 710. Conductive trace 716-2 is connected to an RF passive component 720-3, which may include a capacitor and / or an inductor. The RF passive component 720-3 may be implemented as, for example, an IPD or a surface mount chip. The combination of conductive trace 716-2 and RF passive component 720-3 can implement the series CL circuit "Output_f0" shown in Figure 8B.

[0108] As can be seen from Figures 8A to 8B, in the RF transistor amplifier 700, the RF input and RF output are routed through the upper gate and drain terminals, respectively, and the input harmonic termination circuit and the output impedance matching circuit are routed through the lower gate and drain terminals, respectively. Figures 9A and 9B are a schematic cross-sectional view and a circuit diagram of an RF transistor amplifier 800, respectively, wherein the RF input and RF output are routed through the lower gate and drain terminals, respectively, and the input harmonic termination circuit and the output impedance matching circuit are routed through their respective upper gate and drain terminals.

[0109] As shown in FIG9A, the RF transistor amplifier 800 includes an RF transistor amplifier die 210 mounted on an RDL laminate structure 810 (which may alternatively be another mounting structure such as a multilayer printed circuit board or an IPD). The RDL laminate structure 810 includes a conductive region 812 and a dielectric region 814. A pair of RF passive components 820-1, 820-2 are mounted on the RDL laminate structure 810. An RF input 840 is implemented as a conductive structure in the RDL laminate structure 810. This RF input 840 can be connected to a first external circuit. The RF input 840 is connected to the gate terminal 222 below the RF transistor amplifier die 210 via a contact 280 and is connected to the gate of the RF transistor amplifier die 210 through a conductive gate path 262. The inherent inductance of the conductive gate path 262 in the RF transistor amplifier die 210 is shown as inductor "Lvia_G" in FIG. 9B. A first bonding line 830-1 connects the upper gate terminal 243 of the RF transistor amplifier die 210 to one of the upper terminals of the RF passive component 820-1. The RF passive component 820-1 may include a lumped capacitor and may be implemented as, for example, a capacitor IPD or a surface mount capacitor chip. The lower terminal of the RF passive component 820-1 is connected to one of the ground regions in the RDL laminate structure 810. The first bonding line 830-1 implements the inductor included in the circuit "Input_2f" shown in FIG. 9B, and the RF passive component 820-1 implements the capacitor included in the circuit "Input_2f".

[0110] A second bonding wire 830-2 connects the drain terminal 253 on the RF transistor amplifier die 210 to one of the upper terminals of the RF passive component 820-2, which forms a grounded shunt capacitor. The RF passive component 820-2 may be implemented as, for example, a capacitor IPD or a surface-mount capacitor chip. One of the lower terminals of the RF passive component 820-2 is connected to a ground region in the RDL laminate structure 810 via a contact 280.

[0111] The second junction line 830-2 and a lumped capacitor implemented in the RF passive component 820-2 are together implemented in the series LC circuit labeled "Output_f0" in FIG9B. The RF output 842 is implemented as a conductive structure in the RDL laminate structure 810 and can be connected to a second external circuit. The RF output 842 is connected to the lower drain terminal 224 of the RF transistor amplifier chip 210 via a contact 280 and is connected to the drain of the RF transistor amplifier chip 210 through a conductive drain path 264. The inherent inductance of the conductive drain path 264 in the RF transistor amplifier chip 210 is shown as an inductor "Lvia_D" in FIG9B.

[0112] Figures 10A and 10B are schematic cross-sectional views illustrating the top metallization structure of two RF transistor amplifier chips according to a further embodiment of the present invention.

[0113] As shown in FIG10A, except that the RF transistor amplifier die 210' does not contain a drain path 264 and the drain terminal in the RF transistor amplifier die 210' can be implemented on the top side of the semiconductor layer structure 230 in the manner discussed above with reference to the RF transistor amplifier 100 of FIG1A to FIG1B and connected to (e.g.) a drain lead via (a number of) bonding wires, the RF transistor amplifier die 210' according to one embodiment of the present invention is very similar to the RF transistor amplifier die 210. For example, the RF transistor amplifier die 210' can be used when the bonding wire does not provide too large an inductance for any output matching network. The remainder of the RF transistor amplifier die 210' may be identical to the RF transistor amplifier die 210, and therefore further description thereof will be omitted.

[0114] As shown in FIG10B, except that the RF transistor amplifier die 210" does not contain a gate path 262 and the gate terminal in the RF transistor amplifier die 210" is implemented on the top side of the semiconductor layer structure 230 and connected to a gate lead via (e.g.) through (a number of) bonding wires in the manner discussed above with reference to the RF transistor amplifier 100 of FIG1A to FIG1B, the RF transistor amplifier die 210" of one embodiment of the present invention is also very similar to the RF transistor amplifier die 210. For example, the RF transistor amplifier die 210" can be used when the bonding wire does not provide too large an inductance for any input matching network. The remainder of the RF transistor amplifier die 210" may be identical to the RF transistor amplifier die 210, and therefore further description thereof will be omitted. In any of the above embodiments of the present invention, the RF transistor amplifier dies 210', 210" may be used in place of the RF transistor amplifier die 210.

[0115] As described above with reference to Figures 8A to 9B, an RF transistor amplifier according to an embodiment of the present invention may include an RF passive component in the form of an IPD mounted on an RDL laminate or other substrate. In the embodiments of Figures 8A to 9B, ground connections to RF passive components 720, 820 are formed using contact 280, while other connections to the IPD are formed using bonding wires. According to a further embodiment of the present invention, all electrical connections to the RF passive components may be formed using conductive bumps or other electrical connections besides bonding wire connections. This can further simplify manufacturing operations, allow for a smaller device coverage area (because large bonding wire pads are no longer needed), and eliminate some RF performance problems that may occur when using bonding wire connections, such as inductance variation (attributed to variations in bonding wire length), parasitic inductance, and excessively high inductance, especially in high-frequency applications.

[0116] FIG11A is a schematic cross-sectional view of an RF transistor amplifier 900 according to one embodiment of the present invention. As shown in FIG11A, the RF transistor amplifier 900 includes an RF transistor amplifier die 210 (or any other RF transistor amplifier die according to an embodiment of the present invention) and an RF passive component 920-1, both of which are mounted on an RDL laminate structure 910. In the embodiment of FIG11A, the RF transistor amplifier 900 includes an input impedance matching circuit and an input harmonic termination circuit, but does not include any output matching circuit. The input matching circuit is mainly implemented in the RF passive component 920-1.

[0117] The RDL laminate 910 includes a plurality of conductive traces 912 and conductive paths 914 formed within a dielectric substrate 916. The conductive traces 912 and conductive paths 914 are used for electrical connections to various terminals on the RF transistor amplifier die 210 and the RF passive component 920-1. The RDL laminate 910 further includes electrical connections to external circuitry, including connections to a gate lead 940, a drain lead 942, and a source connector 944. In some embodiments, the source connector 944 may be connected to electrical ground. The RDL laminate 910 further includes a metal block 946 (or alternatively, a dense array of metal-filled or pre-filled (e.g., at least 75% or at least 85% filled) paths (such as copper-filled paths)) that dissipates heat generated in the RF transistor amplifier die 210 to the outside of a package (not shown) of the RF transistor amplifier 900.

[0118] Electrical connections to the RF transistor amplifier die 210 are formed at the lower ends of the gate path 262, the conductive drain path 264, and the conductive power source path 266 on the rear side of the die 210. The RF transistor amplifier die 210 can be directly attached to the RDL laminate structure 910 using typical die attachment techniques such as eutectic materials, pre-coating (e.g., gold-tin pre-coating), solder pre-forming, sintering (e.g., Ag sintering), and the like.

[0119] An RF passive component 920-1 (which may be, for example, an IPD) is flip-chip attached to an RDL laminate structure 910. The RF passive component 920-1 may have a plurality of terminals on one of its "upper" sides, and a plurality of contacts, such as conductive bumps 280, may be pre-attached to these terminals. Then, the RF passive component 920-1 may be flipped upside down, and the conductive bumps 280 may be mounted on corresponding conductive pads on the RDL laminate structure 910 to physically and electrically attach the RF passive component 920-1 to the RDL laminate structure.

[0120] The RF passive component 920-1 may include one or more capacitors and / or one or more inductors for implementing at least a portion of an input matching network. In the embodiment shown in FIG11A, the RF passive component 920-1 includes a pair of capacitors 922-1, 922-2 and a pair of inductors 924-1, 924-2, which are schematically illustrated in FIG11A. The inductor 924 may be implemented as, for example, a conductive trace, which may be narrowed, elongated, spiraled, or similar to produce a desired inductance. Unlike the inductance produced by the above-described wire bonding process, which may have a wire length variation of up to 4 mils, the inductance produced by these conductive traces must be carefully controlled.

[0121] As shown in Figure 11A, the gate lead 940 on the RDL laminate 910 is connected via a conductive path to a conductive pad 912 on the upper side of the RDL laminate 910. A first contact 280 electrically connects the conductive pad 912 to a first terminal 926-1 of the RF passive component 920-1. The first terminal 926-1 is electrically connected to a first electrode of the first capacitor 922-1. The second electrode of the first capacitor 922-1 can be connected to a second terminal 926-2 of the RF passive component 920-1, which is then connected via a second contact 280 to a corresponding pad on the RDL laminate 910. The second contact 280 can be electrically connected to a source connector on the RDL laminate 910, which can be connected to ground. The first electrode of the first capacitor 922-1 is connected to the first electrode of the second capacitor 922-2 via a first conductive trace segment 924-1. The second electrode of the second capacitor 922-2 can be connected to a third terminal 926-3 of the RF passive component 920-1, which is then connected via a third contact 280 to a corresponding pad on the RDL laminate structure 910. The third contact 280 can be electrically connected to a source connector on the RDL laminate structure 910. The first electrode of the second capacitor 922-2 is connected via a second conductive trace segment 924-2 to a fourth terminal 926-4 of the RF passive component 920-1, which is then connected via a fourth contact 280 to a corresponding pad on the RDL laminate structure 910. The gate terminal 222 on the RF transistor amplifier die 210 is connected via a fifth contact 280 to the same pad 912 on the RDL laminate structure 910, so that the RF signal input at the gate lead 940 on the RDL laminate structure 910 can reach the gate of the RF transistor amplifier die 210 through the RF passive component 920-1. The drain terminal 224 of the RF transistor amplifier chip 210 is connected to the drain lead 942 on the RDL laminate structure 910 via a contact 280 and one of the conductive paths in the RDL laminate structure 910.

[0122] FIG11B is a schematic cross-sectional view of an RF transistor amplifier 900' according to a further embodiment of the present invention. The RF transistor amplifier 900' is similar to the RF transistor amplifier 900 of FIG11A, but further includes an output matching network. The description of the RF transistor amplifier 900' will focus on the output matching network, since the rest of the RF transistor amplifier 900' is the same as the RF transistor amplifier 900.

[0123] As shown in Figure 11B, the RF transistor amplifier 900' includes a second RF passive component 920-2 electrically inserted between the drain terminal 224 of the RF transistor amplifier die 210 and the drain lead 942 on the RDL laminate structure 910. The RF passive component 920-2 may also be, for example, flip-chip attached to one IPD of the RDL laminate structure 910. The RF passive component 920-2 may have a plurality of terminals on one of its "upper" sides, and a plurality of contacts 280 may be pre-attached to the terminals. In the depicted embodiment, the RF passive component 920-2 includes a shunt LC network including a capacitor 922-3 and an inductor 924-3 for impedance matching, and a series transmission line connects the drain terminal 224 of the RF transistor amplifier die 210 to the drain lead 942 of the RDL laminate structure 910. The impedance of a series transmission line can be adjusted, for example, by adjusting the width (or thickness) of the conductive trace to further enhance impedance matching at the output of the RF transistor amplifier 900'.

[0124] Figure 11C is a schematic circuit diagram of the RF transistor amplifier 900' of Figure 11B. In Figure 11C, circuit elements, RF passive components 920-1, 920-2 and RDL laminate structure 910 included in the RF transistor amplifier chip 210 are shown.

[0125] Figure 11D is a schematic top view of an RF transistor amplifier 900" similar to the RF transistor amplifier 900' in Figures 11B to 11C. As shown in Figure 11D, the RF transistor amplifier 900" includes an RDL laminate structure 910 of the RF transistor amplifier 900', an RF transistor amplifier die 210, and RF passive components 920-1 and 920-2. Since these components and their electrical connections have been described above, further descriptions will be omitted. The RF transistor amplifier 900" further includes two additional RF passive components 920-3 and 920-4 in the form of high-density (i.e., high-capacitance) capacitor chips. RF passive component 920-3 is inductorably connected to capacitor 922 in RF passive component 920-1, and RF passive component 920-4 is inductorably connected to capacitor 922 in RF passive component 920-2. The capacitance in RF passive components 920-3 and 920-4 allows the RF transistor amplifier 900" to improve video bandwidth performance compared to RF transistor amplifier 900'. A minimum inductance is required in the connections between RF passive components 920-1 and 920-3 and between RF passive components 920-2 and 920-4 to isolate the RF signal path from resistive losses in the high-density capacitor chips 920-3 and 920-4. In some embodiments, the required inductance may be implemented in RF passive devices 920-1 and 920-2.

[0126] Figure 11D also illustrates the gate lead 940, drain lead 942, and source lead 944 implemented in the RDL laminate structure 910. The gate lead 940 and drain lead 942 may be implemented on the opposite side of the RDL laminate structure 910, and the source lead 944 is located between the gate lead 940 and the drain lead 942. The source lead 944 may be implemented as a dense array of conductive paths and / or a large conductive pad (which may be located on a corresponding conductive pad / block on an interconnect structure (such as a printed circuit board) containing a terminal device of the RF transistor amplifier 900") to electrically connect the source lead 944 to electrical ground and provide a heat dissipation path through the interconnect structure. The gate lead 940 and drain lead 942 may similarly be electrically connected to corresponding pads on the interconnect structure.

[0127] Figures 12A and 12B illustrate an RF transistor amplifier 1000 according to a further embodiment of the present invention. The RF transistor amplifier 1000 is similar to the RF transistor amplifier 900", but has a different output matching circuit. Specifically, as shown in Figure 12A, the drain lead 942 is directly connected to the drain terminal 224 on the RF transistor amplifier die 210, and the shunt LC circuits 922-3 and 924-3 are similarly coupled to the drain terminal 224. Figure 12B is an equivalent circuit diagram of the RF transistor amplifier of Figure 12A.

[0128] FIG13 is a schematic cross-sectional view of an RF transistor amplifier 1100 according to a further embodiment of the present invention. The RF transistor amplifier 1100 of FIG13 is similar to the RF transistor amplifier 900 of FIG11A, and the main difference is that the RF transistor amplifier 1100 includes a multi-stage amplifier comprising two RF transistor amplifier chips 210-1 and 210-2 mounted on an RDL laminate structure 1110, and the RF transistor amplifier 1100 also includes an interstage impedance matching circuit implemented in the RF passive component 1120-2. The input impedance matching RF passive component 1120-1 also has a slightly different design from the corresponding RF passive component 920-1 in FIG11A.

[0129] It should be understood that although in some embodiments the two RF transistor amplifier chips 210-1, 210-2 may be identical, this is not necessarily the case. For example, in other embodiments, one of the RF transistor amplifier chips 210-1, 210-2 may be smaller than the other and may have a different configuration. It should also be understood that one of the two RF transistor amplifier chips 210-1, 210-2 may include a group III nitride-based RF transistor amplifier, while the other may be implemented using a different technology (such as, for example, a silicon LDMOS RF transistor amplifier). Furthermore, although the RF transistor amplifier chips 210-1, 210-2 shown in FIG. 13 each have both a conductive gate path and a conductive drain path, it should be understood that in further embodiments, one or both may have only a conductive gate path or only a conductive drain path, or neither may have both a conductive gate path or a conductive drain path.

[0130] An RF transistor amplifier according to an embodiment of the present invention, comprising an RF transistor amplifier die mounted on an RDL laminate, is particularly suitable for overmolded packaging. FIG14 is a schematic cross-sectional view of a packaged RF transistor amplifier 1200 according to an embodiment of the present invention comprising this overmolded package. As shown in FIG14, a plastic overmolding component 1210 may be formed on the top surface of the RF amplifier die 210 of FIG8A. The plastic overmolding component 1210 may be formed as part of a wafer-level packaging process in which a plurality of RF amplifier dies 210 are mounted on a large RDL laminate (not shown). After the plastic overmolding component is formed on the large RDL laminate and the individual RF transistor amplifier dies 210, the large RDL laminate and the RF transistor amplifier dies 210 mounted thereon may be cut to provide the plurality of packaged RF transistor amplifiers 1200 shown in FIG14. In other embodiments, the plastic overmolding component 1210 can be applied directly to the RF transistor amplifier structure shown in FIG. 8A. In this case, the plastic overmolding component can also be formed to cover the sidewalls of the RDL laminate structure 710. This technique can be applied, for example, when using a fan-out configuration, because the RF transistor amplifier die can be applied to the interconnect structure after wafer dicing and the plastic overmolding component can be applied after the RF transistor amplifier die is mounted on the interconnect structure. It should be understood that, as disclosed herein, any RF transistor amplifier comprising an RF transistor amplifier die mounted on an RDL laminate structure according to embodiments of the present invention can be packaged in any of the above-described plastic overmolding package configurations. It should be noted here that the term "overmolding component" is used broadly to encompass protective plastic coatings and the like deposited on the top of a wafer before dicing a wafer into individual dies, such as those shown in FIG. 14.

[0131] It should be understood that any RF transistor amplifier discussed above according to embodiments of the present invention can be mounted in a package such as the open-mouth and overmolded package shown in Figures 4C and 4D respectively to provide a packaged RF transistor amplifier that can be easily transported to a customer. Therefore, the RF transistor die 210 and interconnect structure 270 shown in Figures 4C to 4D can be replaced by the RF transistor die and interconnect structure discussed herein according to any embodiment of the present invention to provide numerous further embodiments of packaged RF transistor amplifiers.

[0132] It should also be understood that protective plastic encapsulation can be applied to any RF transistor amplifier disclosed herein according to embodiments of the invention. Figures 15A to 15C illustrate additional examples of RF transistor amplifiers according to embodiments of the invention including protective plastic encapsulation. As shown in Figure 15A, the wafer 201 of Figure 4A (only a portion of it is visible in Figure 15A) has a plurality of RF transistor dies 210 formed thereon. The wafer 201 is mounted on a composite RDL laminate substrate 1310. The composite RDL laminate substrate 1310 includes a plurality of individual RDL laminate substrates 1312 positioned below the respective RF transistor amplifier dies 210. Each individual RDL laminate substrate 1312 includes a metal gate block 1342, a metal drain block 1344, and a metal source block 1346 provided within a dielectric of the composite RDL laminate substrate 1310. The wafer 201 can be mounted on the composite RDL laminate substrate 1310 by any suitable method, such as using contacts (e.g., conductive solder or die attachment material).

[0133] The metal gate block 1342 in each individual RDL laminate 1312 is electrically connected to the conductive gate path 262 of its associated RF transistor amplifier die 210, the metal drain block 1344 in each individual RDL laminate 1312 is electrically connected to the conductive drain path 264 of its associated RF transistor amplifier die 210, and the metal source block 1346 in each individual RDL laminate 1312 is electrically connected to the conductive source path 266 of its associated RF transistor amplifier die 210. A protective plastic coating 1301 may be applied to the top surface of the wafer 201 (before or after the wafer 201 is mounted on the composite RDL substrate 1310). Next, the wafer 201 and its protective plastic coating 1301 can be diced along the vertical dashed dicing line shown in Figure 15A to form individual RF transistor amplifiers 1300, each including an RF transistor die 210 mounted on a separate RDL laminate substrate 1312. One such individual RF transistor amplifier 1300 is schematically depicted in Figure 15B. The examples in Figures 15A and 15B illustrate an exemplary manner in which individual RF transistor amplifiers 1300 can be formed using wafer-level processing.

[0134] The wafer-level processing technology described above with reference to Figures 15A to 15B is particularly suitable for use with individual RDL laminates 1312 having a fan-in design, since each individual RDL laminate 1312 will have a “coverage area” (i.e., the area when viewed from above) that is substantially the same as that of its associated RF transistor amplifier die 210.

[0135] When an individual RDL laminate substrate 1312 has a fan-out topology and therefore has a coverage area larger than that of the individual RDL laminate substrate 1312, it is not always possible to attach the composite RDL laminate structure 1310 discussed above to the wafer 201 and then cleave them together, because this requires that the individual RF transistor chips 210 be more spaced on the wafer 201 so that an RF transistor amplifier chip 210 is positioned above the individual RDL laminate structure 1312. Therefore, for this fan-out RDL laminate substrate 1312, a plastic coating 1301 can be applied as a wafer-level processing step, and then the wafer 201 can be cleaved into individual RF amplifier chips 210 (each having a plastic coating on one of its top surfaces). Subsequently, the individual RF transistor amplifier chips 210 can be mounted on the composite RDL laminate substrate 1310, and then the composite RDL laminate substrate 1310 can be cleaved. Alternatively, each RF transistor amplifier die 210 may be mounted on a separate RDL laminate substrate 1312.

[0136] Referring again to FIG. 15C, in other embodiments, a protective plastic encapsulation may be applied after the wafer 201 of FIG. 4A is diced into individual RF transistor amplifier dies 210. When a protective plastic encapsulation is applied after dicing, it may be applied as a plastic overlay molding 1402 covering the top surface and sidewalls of each RF amplifier die 210. In the embodiment of FIG. 15C, the RF amplifier die 210 and the plastic overlay molding 1402 thereon are mounted on a separate RDL laminate substrate 1410 using any suitable contacts such as, for example, die attachment material to provide an RF transistor amplifier 1400.

[0137] As another example, a protective plastic coating may be applied to an RF transistor amplifier die according to an embodiment of the present invention, mounted on a custom interposer. FIG16A illustrates this exemplary embodiment in which an RF transistor die 210 is coated with a protective plastic coating 1501 as part of a wafer-level processing step. The coated RF transistor amplifier die 210 is then mounted on a custom interposer 1510 to provide an RF transistor amplifier 1500, as shown in FIG16A. The interposer 1510 included in the RF transistor amplifier 1500 includes a conductive gate connector 1542, a conductive drain connector 1544, and a conductive power electrode connector 1546 implemented as a large metal block. In other embodiments, a protective plastic overmolding 1502 may be applied after the wafer 201 of FIG4A is diced into individual RF transistor amplifier dies 210. When a protective plastic overmolding 1502 is applied after cutting, it can cover both the upper surface and sidewalls of the RF transistor amplifier die 210 to provide one of the RF transistor amplifiers 1500' shown in FIG. 16B. It should be understood that in the embodiments of FIG. 16A and FIG. 16B, the interposers 1510, 1510' may have fan-in or fan-out topologies. For illustration, interposer 1510 is shown as having a fan-in topology, while interposer 1510' is shown as having a fan-out topology.

[0138] Alternatively, the RF transistor amplifier die can be provided as a separate component that can be mounted by a customer onto an interconnect structure such as a customer's printed circuit board. The separate RF transistor amplifier die may include a protective plastic package. In some embodiments, the protective plastic package may be applied as part of a wafer-level package. Using the RF transistor die 210 of Figures 4A and 4B as an example, a protective plastic coating 211 may be applied to the top surface of the wafer 201 of Figure 4A as part of a wafer-level package step. The wafer 201 and the protective plastic coating 211 thereon may be diced to monolithize the individual RF transistor dies 210. As shown in Figure 17A, this would provide RF transistor amplifier dies 210A each having a protective plastic coating 211 on one of their upper surfaces. A customer can then mount the RF transistor amplifier dies 210A onto, for example, a customer's printed circuit board or other interconnect structure.

[0139] In other contexts, a protective plastic encapsulation can be advantageously applied as a die-level process. Again, using the wafer 201 of FIG4A as an example, the wafer 201 can be monolithized into individual RF transistor amplifier dies 210, as discussed above and illustrated in FIG4B. Subsequently, a protective plastic overmolding 213 can be applied to the individual RF transistor amplifier dies 210. When the protective plastic overmolding 213 is applied after monolithization, the protective plastic overmolding 213 can cover both the upper surface and the side surface of the RF transistor amplifier die 210 to provide an RF transistor amplifier die 210B. This is schematically illustrated in FIG17B. A customer can then mount the RF transistor amplifier die 210B on, for example, a customer printed circuit board or other interconnect structure.

[0140] Depending on the embodiment, the packaged RF transistor amplifier may include a monolithic microwave integrated circuit (MMIC) as the RF transistor amplifier die, wherein the RF transistor amplifier die incorporates multiple discrete devices into a single integrated die. Alternatively or concurrently, the package may include multiple RF transistor amplifier dies connected in series in a path to form a multi-stage RF transistor amplifier and / or multiple RF transistor amplifier dies disposed in multiple paths (e.g., in parallel) to form an RF transistor amplifier (such as in a multi-stage amplifier configuration) with the multiple RF transistor amplifier dies and the multiple paths. In any of these multiple RF transistor amplifier die embodiments, one or more (including all) RF transistor amplifier dies may be RF transistor amplifier dies according to any of the above embodiments.

[0141] Although the exemplary embodiments discussed above include a single RF amplifier die having a single-stage amplifier, it should be understood that embodiments of the invention are not limited thereto. In other embodiments, the amplifier may include multiple stages, may have a multi-stage configuration, etc.

[0142] Compared with conventional RF transistor amplifiers, the RF transistor amplifier according to embodiments of the present invention has many advantages. Providing conductive gate and drain paths in the RF transistor amplifier die reduces or eliminates the need for bonding wires. Eliminating bonding wire connections reduces costs and simplifies manufacturing, and improves the RF performance of the device because the inductance in the impedance matching network can be precisely controlled, and the problem of excessively large inductance in the matching network can be avoided. In addition, eliminating bonding wires reduces the size of the device. Furthermore, the RF transistor amplifier according to embodiments of the present invention makes it possible to increase wafer-level packaging, which can further simplify manufacturing and / or reduce production costs.

[0143] Embodiments of the present invention can be used, for example, in RF power products and radar applications for 5G and base station and / or mobile phone applications.

[0144] The embodiments of the present invention have been described above with reference to the accompanying drawings, which illustrate embodiments thereof. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the invention thorough and complete and to fully convey the scope of the invention to those skilled in the art. Identical element symbols refer to all identical elements.

[0145] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, such elements should not be limited to these terms. These terms are used only to distinguish elements from one another. For example, a first element may be referred to as a second element without departing from the scope of the invention, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated items.

[0146] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the terms "comprising" and / or "including" specifically mean the presence of the stated features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or groups thereof.

[0147] It should be understood that when an element, such as a layer, region, or substrate, is considered "on another element" or extends "to another element," it may be directly on or directly to that other element, or an intervening element may be present. In contrast, when an element is considered "directly on another element" or "directly to another element," no intervening element is present. It should also be understood that when an element is considered "connected" or "coupled" to another element, it may be directly connected or coupled to that other element, or an intervening element may be present. In contrast, when an element is considered "directly connected" or "directly coupled" to another element, no intervening element is present.

[0148] Relative terms such as “below” or “above” or “up” or “down” or “horizontal” or “lateral” or “vertical” may be used herein to describe the relationship between one element, layer or region and another element, layer or region, as illustrated in the figures. It should be understood that, in addition to the orientation depicted in the figures, these terms are intended to cover different orientations of the device.

[0149] Typical embodiments of the invention have been disclosed in the drawings and description, and although specific terms have been used, they are used only in a general and descriptive sense and are not intended to be limiting. The scope of the invention is set forth in the following claims. [Simplified Explanation of the Diagram]

[0150] FIG1A is a schematic side view of a conventional RF transistor amplifier based on group III nitrides. FIG1B is a schematic cross-sectional view taken along line 1B-1B of FIG1A, showing the top metallization structure of an RF transistor amplifier die included in the RF transistor amplifier of FIG1A.

[0151] Figure 1C is a schematic side view of another known RF transistor amplifier based on group III nitrides.

[0152] FIG2A is a schematic side view of an RF transistor amplifier based on a group III nitride according to an embodiment of the present invention.

[0153] Figure 2B is a schematic cross-sectional view taken along line 2B-2B of Figure 2A, showing the top metallization structure of an RF transistor amplifier die included in the RF transistor amplifier of Figure 2A.

[0154] Figure 2C is a cross-sectional view obtained along line 2C-2C of Figure 2B.

[0155] Figure 2D is a cross-sectional view obtained along line 2D-2D of Figure 2B.

[0156] Figure 2E is a cross-sectional view obtained along line 2E-2E of Figure 2B.

[0157] Figure 2F is a cross-sectional view obtained along line 2F-2F in Figure 2B.

[0158] Figure 2G is a schematic rear view of one of the RF transistor amplifier chips included in the group III nitride-based RF transistor amplifier in Figure 2A.

[0159] Figure 3 is a plan view of one embodiment of an interconnect structure that can be used in the RF transistor amplifiers of Figures 2A to 2G.

[0160] Figure 4A is a schematic plan view of one of the wafers on which a plurality of RF transistor amplifier chips are formed.

[0161] Figure 4B is a schematic cross-sectional view of an RF transistor amplifier die according to an embodiment of the present invention, with solder bumps attached for attachment to an interconnect structure.

[0162] Figure 4C is a schematic cross-sectional view of a packaged RF transistor amplifier containing the RF transistor amplifier die of Figure 4B in a ceramic package.

[0163] Figure 4D is a schematic cross-sectional view of an RF transistor amplifier package containing one of the RF transistor amplifier chips of Figure 4B in a molded plastic package.

[0164] Figure 4E is a schematic cross-sectional view of a packaged RF transistor amplifier containing the RF transistor amplifier die of Figure 4B in a printed circuit board-based package.

[0165] Figure 5A is a schematic cross-sectional view of an RF transistor amplifier die according to an embodiment of the present invention, which is mounted on a multilayer substrate according to a fan-in topology.

[0166] Figure 5B is a schematic cross-sectional view of an RF transistor amplifier die according to an embodiment of the present invention, which is mounted on a multilayer substrate according to a fan-out topology.

[0167] Figure 5C is a schematic cross-sectional view of an RF transistor amplifier die according to an embodiment of the present invention, which is mounted on a custom interposer according to a fan-out topology.

[0168] Figure 6 is a circuit diagram of an RF transistor amplifier chip according to one embodiment of the present invention, illustrating how multiple connection points can be used for both gate and drain connections, which can improve the flexibility of connecting impedance matching and / or harmonic termination circuits to the RF transistor amplifier chip.

[0169] Figure 7A is a circuit diagram of a conventionally packaged RF transistor amplifier.

[0170] Figure 7B is a circuit diagram of an RF transistor amplifier packaged according to an embodiment of the present invention.

[0171] Figure 7C is a circuit diagram of a packaged RF transistor amplifier according to a further embodiment of the present invention.

[0172] FIG8A is a schematic cross-sectional view of an RF transistor amplifier according to a further embodiment of the present invention.

[0173] Figure 8B is a circuit diagram of one of the RF transistor amplifiers in Figure 8A.

[0174] FIG9A is a schematic cross-sectional view of an RF transistor amplifier according to a further embodiment of the present invention.

[0175] Figure 9B is a circuit diagram of one of the RF transistor amplifiers in Figure 9A.

[0176] Figures 10A and 10B are schematic cross-sectional views showing the top metallization structure of two RF transistor amplifier chips according to a further embodiment of the present invention.

[0177] FIG11A is a schematic cross-sectional view of an RF transistor amplifier according to a further embodiment of the present invention.

[0178] Figure 11B is a schematic cross-sectional view of one of the modified versions of the RF transistor amplifier in Figure 11A.

[0179] Figure 11C is a circuit diagram of one of the RF transistor amplifiers in Figure 11B.

[0180] Figure 11D is a schematic plan view of one of the RF transistor amplifiers in Figure 11B.

[0181] FIG12A is a schematic cross-sectional view of an RF transistor amplifier according to an additional embodiment of the present invention.

[0182] Figure 12B is a circuit diagram of one of the RF transistor amplifiers in Figure 12A.

[0183] FIG13 is a schematic cross-sectional view of an RF transistor amplifier according to a further embodiment of the present invention.

[0184] FIG14 is a schematic cross-sectional view of an RF transistor amplifier according to an embodiment of the present invention, including an overmolded package.

[0185] Figures 15A to 17B are schematic cross-sectional views of an RF transistor amplifier according to a further embodiment of the present invention, including a protective plastic package.

Claims

1. A radio frequency ("RF") transistor amplifier, comprising: An interconnect structure having at least a first conductive structure and a second conductive structure on one of its upper surfaces; and a group III nitride-based RF transistor amplifier die mounted on the upper surface of the interconnect structure, the group III nitride-based RF transistor amplifier die comprising: a semiconductor layer structure; at least one conductive electrode path connected to a source region of the group III nitride-based RF transistor amplifier die, the at least one conductive electrode path extending through the semiconductor layer structure; and an additional conductive path extending through the semiconductor layer structure, wherein a first end of the additional conductive path is connected to the first conductive structure via a contact inserted between the interconnect structure and the group III nitride-based RF transistor amplifier die, wherein the additional conductive path is at least one of a conductive gate path and a conductive drain path.

2. The RF transistor amplifier of claim 1, wherein a second terminal of the additional conductive path opposite to the first terminal is connected to a first external circuit.

3. The RF transistor amplifier of claim 1, wherein the additional conductive path is a conductive drain path.

4. The RF transistor amplifier of claim 3 further includes a second additional conductive path, wherein the second additional conductive path is a conductive gate path.

5. The RF transistor amplifier of claim 1, further comprising: A passive RF component comprising a capacitor mounted on the interconnect structure and electrically connected to one of the additional conductive paths through the interconnect structure.

6. The RF transistor amplifier of claim 1, wherein a plastic overmolding component covers the upper surface and sidewall of one of the group III nitride-based RF transistor amplifier chips.

7. A radio frequency ("RF") transistor amplifier, comprising: An RF transistor amplifier die based on a group III nitride includes a semiconductor layer structure and a conductive path extending through the semiconductor layer structure; a first impedance matching circuit coupled between a first end of the conductive path and a first external electrical connection; and a first harmonic termination circuit coupled between a second end of the conductive path and a second external electrical connection, wherein the second end of the conductive path is opposite to the first end.

8. The RF transistor amplifier of claim 7, wherein the conductive path is connected to a conductive gate path of a gate electrode of a group III nitride-based RF transistor amplifier die, and the first end of the conductive gate path is adjacent to a top end of the gate electrode and the second end of the conductive gate path is a bottom end.

9. The RF transistor amplifier of claim 7, wherein the conductive path is connected to a conductive drain path of a drain electrode of a group III nitride-based RF transistor amplifier die, and the first end of the conductive drain path is a bottom end and the second end of the conductive drain path is adjacent to a top end of the drain electrode.

10. The RF transistor amplifier of claim 8, further comprising a conductive drain path connected to a drain electrode of the group 3 nitride-based RF transistor amplifier die.

11. The RF transistor amplifier of claim 10, further comprising: A second impedance matching circuit is coupled between a first end of one of the conductive drain paths and a third external electrical connection.

12. The RF transistor amplifier of claim 7, further comprising a redistribution layer ("RDL") laminate substrate, wherein the group III nitride-based RF transistor amplifier die is mounted on one of the upper surfaces of the RDL laminate substrate.

13. The RF transistor amplifier of claim 12, wherein the first end of the conductive path is a top end and the second end of the conductive path is electrically connected to the bottom end of a first conductive pad on the RDL laminate through a first contact.

14. The RF transistor amplifier of claim 10, wherein the conductive gate path, the conductive drain path and the conductive power source path all have a substantially identical shape and a substantially identical cross-sectional area.

15. A radio frequency (“RF”) transistor amplifier, comprising: An interconnect structure; a group III nitride-based RF transistor amplifier die located on a top surface of the interconnect structure, the group III nitride-based RF transistor amplifier die comprising a semiconductor layer structure having a plurality of unit transistors in an upper portion, a power supply path, a gate path, and a drain path, each of the power supply path, the gate path, and the drain path extending through the semiconductor layer structure; and a plurality of conductive contacts located on a bottom surface of the interconnect structure.

16. The RF transistor amplifier of claim 15, wherein the interconnect structure includes a redistribution layer ("RDL") laminate substrate, the RDL laminate substrate including an upper gate pad electrically connected to one of the conductive gate paths, an upper drain pad electrically connected to one of the conductive drain paths, and an upper source pad electrically connected to one of the conductive power paths.

17. The RF transistor amplifier of claim 16, wherein the RDL laminate further includes a lower gate pad electrically connected to the upper gate pad, a lower drain pad electrically connected to the upper drain pad, and a lower source pad electrically connected to the upper source pad, and wherein the contacts include a gate contact mounted on the lower gate pad, a drain contact mounted on the lower drain pad, and a source contact mounted on the lower source pad.

18. The RF transistor amplifier of claim 17, wherein, when viewed from above, at least one of the gate contacts is located outside the coverage area of ​​the group III nitride-based RF transistor amplifier die.

19. The RF transistor amplifier of claim 15, wherein the group III nitride-based RF transistor amplifier die comprises a plurality of parallel source fingers and the power supply path is one of a plurality of source paths, wherein at least two power supply paths are located below each of the power supply fingers.

20. The RF transistor amplifier of claim 19, wherein at least two conductive electrode paths located below a first of the conductive electrode fingers define a first axis, and at least two conductive electrode paths located below a second of the conductive electrode fingers adjacent to the first of the conductive electrode paths define a second axis, wherein when the group III nitride-based RF transistor amplifier die is viewed from above, the conductive gate path is located between the first axis and the second axis.

21. A radio frequency ("RF") transistor amplifier, comprising: An RF transistor amplifier die based on a group III nitride includes: a semiconductor layer structure; a power supply electrode path connected to a source region of the group III nitride-based RF transistor amplifier die, the power supply electrode path extending through the semiconductor layer structure; and an additional conductive path extending through the semiconductor layer structure, wherein a first end of the additional conductive path is connected to a first external circuit and a second end of the additional conductive path opposite to the first end is connected to a first matching circuit.

22. The RF transistor amplifier of claim 21, wherein the additional conductive path is connected to a conductive gate path of a gate electrode of a group 3 nitride-based RF transistor amplifier die, and the first matching circuit is a first input matching circuit.

23. The RF transistor amplifier of claim 22, wherein the group III nitride-based RF transistor amplifier chip further includes a conductive drain path connected to a drain finger of the group III nitride-based RF transistor amplifier chip, wherein a first end of the conductive drain path is connected to a second external circuit and a second end of the conductive drain path opposite to the first end of the conductive drain path is connected to a first output matching circuit.

24. The RF transistor amplifier of claim 21, wherein the additional conductive path is connected to a conductive drain path of a drain finger of the group 3 nitride-based RF transistor amplifier chip, and the first matching circuit is a first output matching circuit.

25. The RF transistor amplifier of claim 22, further comprising an interconnect structure wherein the group III nitride-based RF transistor amplifier die is mounted on an upper surface of one of the interconnect structures.

26. The RF transistor amplifier of claim 25, wherein the first end of the conductive gate path is a top end and the second end of the conductive gate path is electrically connected to the bottom end of a first conductive pad on the interconnect structure via a first contact.

27. The RF transistor amplifier of claim 26, wherein the first input matching circuit includes a capacitor coupled between the bottom end of the conductive gate path and electrical ground.

28. The RF transistor amplifier of claim 26, wherein the first input matching circuit includes a harmonic termination circuit, and the RF transistor amplifier further includes a second input impedance matching circuit, the second input impedance matching circuit including a basic matching circuit connected to the top of the conductive gate path.

29. The RF transistor amplifier of claim 25, wherein the first end of the additional conductive path is electrically connected to the bottom end of a first conductive pad on the interconnect structure via a first contact, and the second end of the additional conductive path is a top end.

30. The RF transistor amplifier of claim 25, wherein the first end of the conductive drain path is a top end and the second end of the conductive drain path is electrically connected to the bottom end of a second conductive pad on the interconnect structure via a second contact.

31. The RF transistor amplifier of claim 25, wherein the first end of the conductive drain path is electrically connected to the bottom end of a first conductive pad on the interconnect structure via a first contact and the second end of the conductive drain path is a top end.

32. The RF transistor amplifier of claim 21, wherein the first input matching circuit includes a basic impedance matching circuit.

33. The RF transistor amplifier of claim 21, further comprising: An interconnect structure wherein the RF transistor amplifier die based on a group nitride is mounted on one of the upper surfaces of the interconnect structure; and a passive RF component comprising a capacitor mounted on the interconnect structure and electrically connected to one of the additional conductive paths through the interconnect structure.

34. The RF transistor amplifier of claim 21, wherein the RF transistor amplifier die based on group 3 nitride includes a plurality of parallel source fingers, wherein at least two power supply paths are located below each of the power supply fingers.

35. The RF transistor amplifier of claim 21, wherein the additional conductive path includes a portion of the first matching circuit.

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