Method of forming crystallographically stabilized ferroelectric hafnium zirconium based films for semiconductor devices

Abstract

A method for forming a crystal-stable ferroelectric hafnium-zirconium film for semiconductor devices is described. The hafnium-zirconium film may be doped or undoped. The method includes: depositing a hafnium-zirconium film with a thickness greater than 5 nanometers on a substrate; depositing a capping layer on the hafnium-zirconium film; and heat-treating the substrate to crystallize the hafnium-zirconium film into a non-centrosymmetric orthorhombic phase, a tetragonal phase, or a mixture thereof. The method further includes: removing the capping layer from the substrate; and thinning the heat-treated hafnium-zirconium film to a thickness less than 5 nanometers, wherein the thinned heat-treated hafnium-zirconium film retains the crystalline non-centrosymmetric orthorhombic phase, a tetragonal phase, or a mixture thereof.

Description

Technical Field

Background Art

Implementation Method

Claims

1. A substrate processing method, comprising: depositing a hafnium-zirconium base film with a thickness greater than 5 nanometers on a substrate; depositing a capping layer on the hafnium-zirconium base film; heat-treating the substrate to cause the hafnium-zirconium base film to crystallize in the form of a non-centrosymmetric orthorhombic phase, a tetragonal phase, or a mixture thereof; removing the capping layer from the substrate; and thinning the heat-treated hafnium-zirconium base film to a thickness of less than 5 nanometers, wherein the thinned heat-treated hafnium-zirconium base film retains the crystalline non-centrosymmetric orthorhombic phase, a tetragonal phase, or a mixture thereof.

2. The substrate processing method of claim 1, wherein the heat-treated hafnium zirconium base film is thinned to a thickness of less than 3 nm.

3. The substrate processing method according to claim 1, wherein the cover layer comprises TiN, TaN, TiAlN, TaAlN, AlN, or a combination thereof.

4. The substrate processing method as described in claim 1, wherein the cover layer comprises Ge, or Ge and Si.

5. The substrate processing method of claim 1, wherein the heat treatment step includes heating the substrate to a temperature between about 300°C and about 850°C.

6. The substrate processing method of claim 1, wherein the thinning step is performed by atomic layer etching (ALE).

7. The substrate processing method of claim 6, wherein the ALE includes alternating exposure to a gas containing B or an Al gas and a gas containing fluorine.

8. The substrate processing method of claim 6, wherein the ALE includes alternating exposure to BCl3 gas and HF gas.

9. The substrate processing method of claim 1 further includes: depositing an amorphous or polycrystalline silicon layer on the hafnium zirconium base film before depositing the capping layer.

10. The substrate processing method of claim 9 further includes: removing the amorphous or polycrystalline silicon layer from the heat-treated hafnium zirconium substrate film.

11. The substrate processing method of claim 1 further includes: further processing the substrate to form a MOSFET, tunneling junction, diode, resistive memory, or capacitor comprising a thinned, heat-treated hafnium zirconium base film.

12. The substrate processing method of claim 1, wherein the hafnium-zirconium base film comprises a hafnium-zirconium oxide film, a hafnium-zirconium nitride film, a hafnium-zirconium nitride film, a doped hafnium-zirconium oxide film, a doped hafnium-zirconium nitride film, or a doped hafnium-zirconium nitride film.

13. The substrate processing method of claim 12, wherein the doped hafnium zirconium oxide film, the doped hafnium zirconium nitride film, or the doped hafnium zirconium nitride film comprises a dopant element selected from the following elements: Be, Mg, Ca, Sr, Ba, Ra, B, Al, Ga, In, Tl, Si, Y, Lu, La, Ce, Pr, Nd, Sm, Eu, Gd, Th, Dy, Ho, Er, Tm, and Yb.

14. A substrate processing method comprising: depositing a hafnium zirconium oxide film with a thickness greater than 5 nanometers on a substrate; depositing a capping layer on the hafnium zirconium oxide film, wherein the capping layer comprises TiN, TaN, TiAlN, TaAlN, AlN, or combinations thereof; heat-treating the substrate at a temperature between about 300°C and about 850°C to crystallize the hafnium zirconium oxide film into a non-centrosymmetric orthorhombic phase, a tetragonal phase, or a mixture thereof; removing the capping layer from the substrate; and thinning the heat-treated hafnium zirconium oxide film to a thickness of less than 5 nm by atomic layer etching (ALE), wherein the thinned heat-treated hafnium zirconium oxide film retains the crystalline non-centrosymmetric orthorhombic phase, a tetragonal phase, or a mixture thereof.

15. The substrate processing method of claim 14, wherein the heat-treated hafnium zirconium oxide film is thinned to a thickness of less than 3 nanometers.

16. The substrate processing method of claim 14, wherein the ALE includes alternating exposure to a gas containing B or an Al gas and a gas containing fluorine.

17. The substrate processing method of claim 14, wherein the ALE includes alternating exposure to BCl3 gas and HF gas.

18. The substrate processing method of claim 14 further includes: depositing an amorphous or polycrystalline silicon layer on the hafnium zirconium oxide film before depositing the capping layer.

19. The substrate processing method of claim 18 further includes: removing the amorphous or polycrystalline silicon layer from the heat-treated hafnium zirconium oxide film.

20. The substrate processing method of claim 14 further includes: further processing the substrate to form a MOSFET, tunneling junction, diode, resistive memory, or capacitor comprising a thinned, heat-treated hafnium zirconium oxide film.

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