Memory device and operation method thereof

Abstract

This invention discloses a memory device and its operation method. The memory device includes multiple memory cells and a control logic circuit. The memory cells can be configured as TLC, MLC, or SLC. The control logic circuit is configured to program MLC and SLC in a TLC programming manner.

Description

[Technical Field]

[0001] This invention relates to a memory device and its operating method. [Previous Technology]

[0002] In addition to the array structure in the XY plane, 3D NAND flash memory typically has a stacked structure in the Z-axis direction. Due to limitations in process technology, the characteristics of memory cells located at the two ends (top and bottom) of the Z-axis are generally worse than those in the middle. Component characteristics affect the reliability of the data stored in the memory cell. Therefore, memory cells at the two ends of the Z-axis are usually configured such that each memory cell stores fewer bits than those in the middle. Traditionally, memory cells storing different numbers of bits must be programmed using different circuits. Therefore, memory devices need to be configured with multiple circuits to handle the programming operations when writing different numbers of bits to memory cells, which is wasteful of hardware space and increases costs. [Summary of the Invention]

[0003] One embodiment of the present invention discloses a memory device. The memory device includes a memory controller and a memory. The memory controller is configured to receive a write request and a first data from a master controller, and send a write command indicating a first parameter according to the write request, wherein the first parameter represents the number of bits of binary data to be written to each memory cell. The memory is coupled to the memory controller and includes a memory array, at least one buffer, and a control logic circuit. The memory array includes a plurality of memory cells. Each memory cell is configured to store up to N bits of binary data, where N is a positive integer greater than 1. The control logic circuit is coupled to the memory array and buffer and is used to perform the following: In response to a write command, when the first parameter is a positive integer K less than N, the first data is divided into sub-data for every K bits, a pseudo data corresponding to each sub-data (NK) bits is generated, and the sub-data and pseudo data are stored in the buffer; and for each memory cell to be programmed, the memory cell is programmed according to the K bits of sub-data to be written to the memory cell and the pseudo data corresponding to the sub-data (NK) bits to be written to the memory cell, such that a threshold voltage of the memory cell falls within one of 2K voltage ranges selected from 2N voltage ranges, wherein the 2N voltage ranges correspond one-to-one to 2N data patterns included in the binary data of N bits.

[0004] Another embodiment of the present invention discloses a method for operating a memory device. The operation method includes: receiving a write request and a first data from a master controller; sending a write command indicating a first parameter according to the write request, wherein the first parameter represents the number of bits of binary data to be written to each memory cell, wherein each memory cell is configured to store up to N bits of binary data, where N is a positive integer greater than 1; in response to the write command, when the first parameter is a positive integer K less than N, dividing the first data into sub-data for every K bits, generating pseudo-data corresponding to each sub-data (NK) bits, and storing the sub-data and pseudo-data to at least one buffer; and for each memory cell to be programmed, programming the memory cell according to the sub-data of K bits to be written to the memory cell and the pseudo-data corresponding to the sub-data (NK) bits to be written to the memory cell in the at least one buffer, such that a threshold voltage of the memory cell falls within one of 2K voltage ranges selected from 2N voltage ranges, wherein the 2N voltage ranges are one-to-one corresponding to the 2K bits of binary data. N types of data formats.

[0005] In order to better understand the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings:

Implementation Method

[0006] Please refer to Figure 1, which illustrates a block diagram of a memory device according to an embodiment of the present invention. The memory device 10 includes a memory controller 102 and one or more memory chips (memory chips) 104. The memory controller 102 is coupled to an external main controller 112, wherein the main controller 112 is, for example, a central processing unit (CPU). The memory chips 104 are coupled to the memory controller 102.

[0007] The memory chip 104 includes a memory array 106, buffers 108-1 to 108-3, and a control logic circuit 110. The memory array 106 can be any non-volatile memory array, such as NAND flash memory, resistive random access memory (RRAM), phase change memory (PCM), magnetoresistive RAM (MRAM), charge-capture memory (e.g., SONOS), etc. In this embodiment, the memory array 106 is a three-dimensional NAND flash memory. Buffers 108-1 to 108-3 are implemented, for example, by means of latches. The control logic circuit 110 is coupled to the memory controller 102, the memory array 106, and the buffers 108-1 to 108-3. The control logic circuit 110 may include an equivalent logic circuit of a finite state machine corresponding to the programming of a Triple Level Cell (TLC), and the control logic circuit 110 is used to execute the programming actions of the TLC.

[0008] The memory array 106 can be used to store data in multiple pages. Each memory cell can be configured to store at least one bit of binary data. For example, the memory cell can be configured as a Single Level Cell (SLC), a Multi Level Cell (MLC), or a TLC. A memory cell configured as an SLC (hereinafter referred to as an SLC memory cell) can store one bit of binary data, such as 0 or 1. A memory cell configured as an MLC (hereinafter referred to as an MLC memory cell) can store two bits of binary data, such as 00, 01, 10, or 11. A memory cell configured as a TLC (hereinafter referred to as a TLC memory cell) can store three bits of binary data, such as 000, 001, 010, 011, 100, 101, 110, or 111. The three bits of binary data stored in a TLC memory cell are, for example, the low page bits, the middle page bits, and the high page bits.

[0009] Traditionally, memory chips are typically configured with three independent control logic circuits to perform programming operations corresponding to SLC memory cells, MLC memory cells, and TLC memory cells, respectively.

[0010] In one embodiment of the present invention, by using a control logic circuit for programming the TLC memory cell, in conjunction with the mechanism described below, the programming operations of the MLC memory cell and the SLC memory cell can be performed using the control logic circuit for programming the TLC memory cell. This effectively reduces the required cost and the hardware space occupied.

[0011] Please refer to Figure 2, which illustrates a flowchart of an operation method of a memory device according to an embodiment of the present invention. In step S201, the memory controller 102 receives a write request and first data to be written from an external main controller. The first parameter represents the number of bits to be written to each memory cell. The write request includes the first parameter. The first data to be written is one or more bits of binary data.

[0012] In step S202, the memory controller 102 determines the number of bits to be written to each memory cell in this write request, that is, obtains the value of the first parameter. When the first parameter is 3 (that is, each memory cell to be programmed is configured as a TLC memory cell to store three bits of data), step S203 is executed, the memory controller 102 sends a TLC write command indicating that the first parameter is 3, and sends the first data to be written to the control logic circuit 110.

[0013] When the first parameter is 2 (that is, each memory cell to be programmed is configured as an MLC memory cell to store two bits of data), step S204 is executed, the memory controller 102 sends an MLC write command indicating that the first parameter is 2, and sends the data to be written to the control logic circuit 110.

[0014] When the first parameter is 1 (that is, each memory cell to be programmed is configured as an SLC memory cell to store one bit of data), step S205 is executed, the memory controller 102 sends an SLC write command indicating that the first parameter is 1, and sends the first data to be written to the control logic circuit 110.

[0015] In step S206 (state: TLC), the control logic circuit 110 stores the first data to be written into buffers 108-1 to 108-3. As shown in Figure 3, assuming the first data 300 to be written is 110011001010 (12 bits in total), the control logic circuit 110 configures the first data 300 into sub-data in every three bits from left to right. The first data to be written can be divided into four sub-data: 110, 011, 001, and 010. Each sub-data needs to be stored using one TLC memory unit, and a total of four TLC memory units are needed to store this first data. The first data 110011001010 will be divided into 1100, 1100, and 1010, and stored into buffers 108-1, 108-2, and 108-3 respectively.

[0016] In step S207 (state: MLC), the control logic circuit 110 stores the first data to be written into two of the buffers 108-1 to 108-3, and generates pseudo data based on the data to be written, storing this pseudo data into the other of the buffers 108-1 to 108-3. As shown in Figure 4, assuming the first data 400 to be written is 110011001010 (12 bits in total), the control logic circuit 110 configures the first data 400 into a sub-data unit every two bits from left to right. The first data to be written can be divided into six sub-data units: 11, 00, 11, 00, 10, and 10. Each sub-data unit needs to be stored using one MLC memory unit, and a total of six MLC memory units are needed to store this first data unit. The first data 110011001010 will be divided into 110011 and 001010, and stored in buffers 108-1 and 108-2 respectively. In one embodiment, the control logic circuit 110, for example, inputs each piece of sub-data to an XNOR (anti-mutually exclusive OR) logic gate to generate dummy data. The XNOR logic gate outputs a logic value of 0 when the input values ​​of the two input terminals are different, and outputs a logic value of 1 when the input values ​​of the two input terminals are the same. In this example, the control logic circuit 110 inputs each piece of sub-data to an XNOR logic gate to generate dummy data. For example, when the input values ​​of the two input terminals of an XNOR logic gate are 1 and 0, the output terminal of the XNOR logic gate outputs 0; when the input values ​​of the two input terminals of an XNOR logic gate are 0 and 1, the output terminal of the XNOR logic gate outputs 0; when the input values ​​of the two input terminals of an XNOR logic gate are 0 and 0, the output terminal of the XNOR logic gate outputs 1; and when the input values ​​of the two input terminals of an XNOR logic gate are 1 and 1, the output terminal of the XNOR logic gate outputs 1. In this example, the six sub-data points 11, 00, 11, 00, 10, and 10 are respectively input to the XNOR logic gate to generate pseudo-data. Taking the first sub-data point 11 as an example, performing an XNOR operation on 1 and 1 results in 1, and so on. In this way, pseudo-data points 1, 1, 1, 1, 0, 0 corresponding to the six sub-data points 11, 00, 11, 00, 10, and 10 can be generated. The generated pseudo data 1, 1, 1, 1, 0, 0 is temporarily stored in buffer 108-3.

[0017] It is worth mentioning that the XNOR logic gate is usually an inherent circuit element of the control logic circuit 110 or other circuits of the memory chip 104, so it does not require additional cost or hardware space.

[0018] In step S208 (state: SLC), the control logic circuit 110 stores the first data to be written into one of the buffers 108-1 to 108-3, and generates pseudo data, storing the pseudo data into the other two of the buffers 108-1 to 108-3 respectively. As shown in Figure 5, assuming the first data 500 to be written is 110011001010 (12 bits in total), the control logic circuit 110 configures each bit of the first data 500 from left to right as a sub-data, resulting in twelve sub-data entries, requiring twelve SLC memory units for storage. The control logic circuit 110 temporarily stores the sub-data into buffer 108-1, and generates two-bit pseudo data corresponding to each sub-data entry, temporarily storing the two bits of the pseudo data into buffers 108-2 and 108-3 respectively. In the example shown in Figure 5, the generated pseudo data is an example of two-bit binary values ​​of 11.

[0019] In step S209, the control logic circuit 110 programs the memory array 106 according to the contents of buffers 108-1 to 108-3 in the manner of programming TLC memory cells. It should be noted that regardless of whether the target memory cell to be programmed is SLC, MLC, or TLC, step S209 will always program the target memory cell in the manner of programming TLC memory cells. The principle will be explained in detail below.

[0020] First, it should be noted that "programming" involves applying a programming bias voltage to the memory cell to inject electrons into the memory cell, thereby changing the threshold voltage of the memory cell. This causes the threshold voltage of the programmed memory cell to fall within one of several voltage ranges, where different voltage ranges represent different data types. "Reading" involves applying a read bias voltage to the memory cell one or more times and observing whether the memory cell allows current to pass through to determine the voltage range of the memory cell's threshold voltage, thereby determining the stored data type.

[0021] Please refer to Figure 6, which illustrates the data and threshold voltage distribution of a TLC memory cell according to an embodiment of the present invention. Figure 6 corresponds to a (1, 2, 4) TLC scramble. The (1, 2, 4) TLC scramble refers to the following when reading the TLC memory cell: the first applied read voltage is one (e.g., PVD), the second applied read bias voltage is two (e.g., PVB and PVF), and the third applied read bias voltage is four (e.g., PVA, PVC, PVE, and PVG). The first applied read bias voltage can be used to determine whether the low page bit of the three-bit data stored in the TLC memory cell is 0 or 1. The second applied read bias voltage can be used to determine whether the middle page bit of the three-bit data stored in the TLC memory cell is 0 or 1. The third applied read bias voltage can be used to determine whether the high page bit of the three-bit data stored in the TLC memory cell is 0 or 1.

[0022] A TLC memory cell can store three bits of binary data. The data patterns of the three bits of binary data include 111, 110, 100, 101, 001, 000, 010, and 011. Eight voltage ranges ER~PVA, PVA~PVB, PVB~PVC, PVC~PVD, PVD~PVE, PVE~PVF, PVF~PVG, and greater than PVG correspond one-to-one with these eight data patterns. For example, the voltage range ER~PVA corresponds to binary data 111, the voltage range PVA~PVB corresponds to binary data 110, and so on. Here, ER is the initial voltage, that is, the voltage after the memory cell is erased. In this disclosure, the correspondence between voltage ranges and data patterns in Figures 7-12 also follows this pattern. Distribution 610 represents the distribution of threshold voltages of a specific number of TLC memory cells within the voltage range ER~PVA after programming. Distributions 62ER~680 represent the distribution of threshold voltages of a specific number of TLC memory cells within the voltage ranges PVA~PVB, PVB~PVC, PVC~PVD, PVD~PVE, PVE~PVF, PVF~PVG, and values ​​greater than PVG, respectively, after programming. By changing the threshold voltage of the TLC memory cells, the threshold voltage of the TLC memory cells can be made to fall within one of these eight voltage ranges, which can also be considered as falling within one of distributions 61ER~680. This means that the programmed TLC memory cells store data corresponding to that voltage range (or distribution). During reading, the control logic circuit 110 applies three read bias voltages to determine the range within which the threshold voltage of the TLC memory cells falls, thereby determining the stored data. The first read bias applied is PVD to determine whether the most significant bit (or the bit data of the lower page) is 0 or 1. The second read bias applied is PVB and PVF to determine whether the middle bit (or the bit data of the middle page) is 0 or 1. The third read bias applied is PVA, PVC, PVE, and PVG to determine whether the least significant bit (or the bit data of the higher page) is 0 or 1. Taking Figure 3 as an example, in step S209, the control logic circuit 110 programs a first TLC memory cell based on the first piece of sub-data (i.e., bit data 110) in buffers 108-1 to 108-3, so that the threshold voltage of the first TLC memory cell falls within the voltage range PVA to PVB (corresponding to distribution 620). Based on the second piece of sub-data (i.e., bit data 011) in buffers 108-1 to 108-3, a second TLC memory cell is programmed, so that the threshold voltage of the second TLC memory cell falls within the voltage range greater than PVG (corresponding to distribution 680), and so on.

[0023] Please refer to Figure 7, which illustrates a schematic diagram of the data stored in an MLC memory cell and the threshold voltage distribution according to an embodiment of the present invention. An MLC memory cell can store two bits of binary data, and the data patterns of the two bits of binary data include 11, 10, 00, and 01. When programming the MLC memory cell, four threshold voltage ranges are selected from eight ranges used for programming the TLC memory cell, and each range corresponds one-to-one with one of the four data patterns of the two bits of binary data. In this embodiment, the selected voltage ranges are ER~PVA, PVB~PVC, PVD~PVE, and PVF~PVG (corresponding to distributions 610, 630, 650, and 670). The function of the pseudo-data is to add one bit to each two-bit sub-data to form a three-bit data, suitable for the operation of TLC programming. Taking Figure 4 as an example, in step S209, the control logic circuit 110 programs a first MLC memory cell based on the combination of the first piece of sub-data (11) in buffers 108-1 to 108-3 and a bit of pseudo-data (1) (i.e., bit data 111), so that the threshold voltage of the first MLC memory cell falls within the voltage range ER~PVA (i.e., it is located in distribution 710, which corresponds to distribution 610). The pseudo-data is chosen to be 1 because the data 11 corresponding to distribution 710 corresponds to the most significant bit and the middle bit (i.e., the low page bit data and the middle page bit data) of the bit data 111 corresponding to distribution 610, and an extra bit of 1 is needed to correspond to the least significant bit (high page bit) of the data 111 corresponding to distribution 610. The control logic circuit 110 programs a second MLC memory cell based on the combination of the second sub-data (00) in buffers 108-1 to 108-3 and a one-bit pseudo-data (1) (i.e., bit data 001), so that the threshold voltage of the second MLC memory cell falls within the voltage range PVD to PVE (i.e., located in distribution 750, which corresponds to distribution 650). The pseudo-data is chosen to be 1 because the data 00 corresponding to distribution 750 corresponds to the most significant bit and the middle bit (i.e., the low-page bit data and the middle-page bit data) of the bit data 001 corresponding to distribution 650, and an additional bit of 1 is needed to correspond to the least significant bit (high-page bit) of the data 001 corresponding to distribution 650. When designing pseudo data, first determine the correspondence between the four data patterns formed by two-bit binary data and the four selected voltage ranges. Then, find the difference between each two-bit data pattern and the corresponding three-bit data pattern for the voltage range. Finally, determine the pseudo data corresponding to each two-bit data pattern based on this difference.During reading, the control logic circuit 110 can apply two reading bias voltages. The first reading bias voltage applied is PV2 to determine whether the most significant bit in the two stored bits is 0 or 1. The second reading bias voltage applied is PV1 and PV3 to determine whether the least significant bit in the two stored bits is 0 or 1.

[0024] Please refer to Figure 8, which illustrates a schematic diagram of the data stored in an SLC memory cell and the threshold voltage distribution according to an embodiment of the present invention. An SLC memory cell can store one bit of binary data, where the data pattern of one bit of binary data includes 0 and 1. When programming the SLC memory cell, two threshold voltage ranges are selected from eight threshold voltage ranges used for programming the TLC memory cell, corresponding to two data patterns of one bit of binary data. In this embodiment, the voltage range ER~PVA (corresponding to distribution 610) and the voltage range greater than PVG (corresponding to distribution 680) are selected. The function of the pseudo data is to supplement each one-bit sub-data with two bits to form a three-bit data, suitable for the operation of TLC programming. Taking Figure 5 as an example, in step S209, the control logic circuit 110 programs a first SLC memory cell based on the combination (i.e., 111) of the first sub-data (1) and two-bit pseudo-data (11) in buffers 108-1 to 108-3, so that the threshold voltage of the first SLC memory cell falls within the voltage range ER~PVA (corresponding to distribution 810). Similarly, it programs a second SLC memory cell based on the combination (i.e., 111) of the second sub-data and two-bit pseudo-data in buffers 108-1 to 108-3, so that the threshold voltage of the second SLC memory cell falls within the voltage range ER~PVA (corresponding to distribution 810), and so on. When designing pseudo-data, the correspondence between the two data patterns formed by a single-bit binary data and the two selected voltage ranges can be determined first. Then, the difference between each single-bit data pattern and the three-bit data patterns corresponding to the corresponding voltage range can be identified. Based on this difference, the pseudo-data corresponding to each single-bit data pattern can be determined. During reading, the control logic circuit 110 can apply a read bias voltage, namely read bias voltage PV4, to determine a stored bit.

[0025] Please refer to Figure 9, which illustrates a schematic diagram of the data and threshold voltage distribution stored in a TLC memory cell according to another embodiment of the present invention. Figure 9 corresponds to the (2, 3, 2) TLC symmetric code. The (2, 3, 2) TLC symmetric code means that when reading the TLC memory cell, the number of read voltages applied for the first time is two (e.g., PVA and PVE), the number of read bias voltages applied for the second time is three (e.g., PVB, PVD, and PVF), and the number of read bias voltages applied for the third time is two (e.g., PVC and PVG).

[0026] For ease of explanation, the following uses the distribution of threshold voltages to represent the corresponding voltage ranges. For example, distribution 910 represents the voltage range ER~PVA, distribution 920 represents the voltage range PVA~PVB, and so on. In this embodiment, when programming the MLC memory unit, distributions 910, 930, 950, and 970 are selected to correspond to 00, 01, 10, and 11, as shown in Figure 10. Buffer 108-1 can be used to temporarily store the most significant bit of each sub-data, buffer 108-3 can be used to temporarily store the least significant bit of each sub-data, and buffer 108-2 can be used to temporarily store pseudo-data corresponding to one bit of each sub-data, wherein the pseudo-data is generated by performing an XNOR operation on each two-bit sub-data. When programming the SLC memory unit, distributions 910 and 960 are selected to correspond to 0 and 1, as shown in Figure 11. Buffer 108-3 can be used to temporarily store sub-data, and buffers 108-1 and 108-2 can be used to temporarily store two bits of pseudo-data corresponding to each sub-data. In Figure 11, each sub-data is used as the least significant bit of the three bits of data required for TLC programming, while the two bits of pseudo-data corresponding to each sub-data are used to fill the most significant bit and the middle bit of the three bits of data required for TLC programming. It should be noted that the position filled by the pseudo-data can also be different depending on the selected distribution (voltage range). As shown in Figure 12, in an alternative embodiment, when programming the SLC memory cell, distributions 910 and 980 are selected to correspond to 0 and 1. In this alternative embodiment, buffer 108-2 is used to temporarily store the middle bit of the data that is used as the three-bit data required by the TLC programming method, while buffers 108-1 and 108-3 are used to temporarily store the most significant bit and least significant bit of the pseudo data that is used as the three-bit data required by the TLC programming method.

[0027] In different embodiments, the memory unit may be further configured as a quad-level cell (QLC) or higher, and the present invention can be applied to these embodiments. In a general embodiment, a memory unit may be configured to store up to N bits of binary data, where N is a positive integer greater than 1. The operation method shown in Figure 2 can be applied to this general embodiment with appropriate modifications.

[0028] Please refer to Figure 13, which illustrates a flowchart of an operation method of a memory device according to another embodiment of the present invention.

[0029] In step S1301, the memory controller receives a write request and first data from the external main controller.

[0030] In step S1302, the memory controller determines the number of bits to be written to each memory cell in this write request (i.e., the first parameter). When the first parameter is N, S1303 is executed, and the memory controller sends a write command instructing each memory cell to write N bits to the control logic circuit, and sends the first data to be written to the control logic circuit; when the first parameter is K (K is a positive integer less than N), S1304 is executed, and the memory controller sends a write command instructing each memory cell to write K bits to the control logic circuit, and sends the first data to be written to the control logic circuit.

[0031] In step S1305, the control logic circuit stores the first data to be written into a sub-data block every N bits and stores it into at least one buffer.

[0032] In step S1306, the control logic circuit divides the first data to be written into a sub-data piece of K bits and stores it in the buffer, and generates (NK) bits of pseudo data corresponding to each sub-data piece and stores the pseudo data in the buffer.

[0033] In step S1307, for each memory cell to be programmed, the control logic circuit programs the memory cell according to the sub-data of N bits to be written into the memory cell in the buffer, so as to change the threshold voltage of the memory cell so that the threshold voltage of the memory cell falls into one of the 2N voltage ranges.

[0034] In step S1308, for each memory cell to be programmed, the control logic circuit programs the memory cell according to the K bits of sub-data to be written to the memory cell in the buffer and the (NK) bits of pseudo-data corresponding to the sub-data, so as to change the threshold voltage of the memory cell so that the threshold voltage of the memory cell falls into one of the 2K selected from the 2N voltage ranges.

[0035] It should be noted that the 2N voltage ranges correspond one-to-one to the 2N data patterns included in the N-bit binary data. The 2K voltage ranges selected from the 2N voltage ranges can be predetermined and recorded in the control logic circuit. In one embodiment, the 2K voltage ranges selected from the 2N voltage ranges are discontinuous, that is, there is at least one unselected voltage range between any two selected voltage ranges, such as the embodiments in Figures 7, 8, 10, 11, and 12, to reduce the probability of misjudgment during reading. In different embodiments, the 2K voltage ranges selected from the 2N voltage ranges may be partially continuous, for example, distributions 610 and 620 are selected from distributions 61ER~680 in Figure 6 to correspond to 1 and 0 during SLC programming, respectively.

[0036] Please refer to Figure 14, which illustrates a schematic diagram of the data and threshold voltage distribution stored in a QLC memory cell according to another embodiment of the present invention. Figure 14 corresponds to the (1, 2, 4, 8) QLC symmetric code. The (1, 2, 4, 8) QLC symmetric code refers to the number of read voltages applied in the first reading of the QLC memory cell being one, the number of read bias voltages applied in the second reading being two, the number of read bias voltages applied in the third reading being four, and the number of read bias voltages applied in the fourth reading being eight. These correspond one-to-one with the sixteen voltage ranges distributed from 141ER to 1425, representing sixteen data patterns of four-bit binary data. Next, referring to Figure 15, which illustrates a schematic diagram of the data and threshold voltage distribution stored in an MLC memory cell according to another embodiment of the present invention. In this embodiment, voltage ranges corresponding to distributions 1410, 1414, 1418, and 1422 are selected as four voltage ranges (or distributions 1510, 1514, 1518, and 1522) for MLC programming, and each corresponds one-to-one with a data pattern of two bits of binary data. Using the operation method illustrated in Figure 13 according to the embodiments in Figures 14 and 15, the control logic circuit used to program the QLC memory cell can be used to program the MLC memory cell.

[0037] It should be noted that the number of buffers can be one or more, and the present invention does not limit the number.

[0038] By means of the present invention, for a memory device that can support writing up to N bits per memory cell, the area of ​​(N-1) control logic circuits can be saved.

[0039] In summary, although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of this invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0040] Figure 1 illustrates a block diagram of a memory device according to an embodiment of the present invention; Figure 2 illustrates a flowchart of an operation method of the memory device according to an embodiment of the present invention; Figures 3-5 illustrate schematic diagrams of storing first data into a buffer; Figure 6 illustrates a schematic diagram of the data stored in a TLC memory cell and the threshold voltage distribution according to an embodiment of the present invention; Figure 7 illustrates a schematic diagram of the data stored in an MLC memory cell and the threshold voltage distribution according to an embodiment of the present invention; Figure 8 illustrates a schematic diagram of the data stored in an SLC memory cell and the threshold voltage distribution according to an embodiment of the present invention; Figure 9 illustrates a schematic diagram of the data stored in a TLC memory cell and the threshold voltage distribution according to another embodiment of the present invention; Figure 10 illustrates a schematic diagram of the data stored in an MLC memory cell and the threshold voltage distribution according to another embodiment of the present invention; Figure 11 illustrates a schematic diagram of the data stored in an SLC memory cell and the threshold voltage distribution according to another embodiment of the present invention; Figure 12 illustrates a schematic diagram of the data stored in an SLC memory cell and the threshold voltage distribution according to yet another embodiment of the present invention; Figure 13 illustrates a flowchart of an operation method of a memory device according to another embodiment of the present invention. Figure 14 illustrates a schematic diagram of the data stored in a QLC memory cell and the threshold voltage distribution according to another embodiment of the present invention; Figure 15 illustrates a schematic diagram of the data stored in an MLC memory cell and the threshold voltage distribution according to another embodiment of the present invention.

Claims

1. A memory device, comprising: A memory controller is configured to receive a write request and a first data from a master controller, and send a write command indicating a first parameter according to the write request, wherein the first parameter represents the number of bits of binary data to be written to each memory cell. And a memory coupled to a memory controller, and including: a memory array including a plurality of memory cells, each memory cell being configured to store up to N bits of binary data, where N is a positive integer greater than 1; and at least one buffer; A control logic circuit, coupled to the memory array and the at least one buffer, is configured to: respond to the write command, when the first parameter is a positive integer K less than N, divide the first data into sub-data for every K bits, generate pseudo-data corresponding to each sub-data (NK) bits, and store the sub-data and pseudo-data in the at least one buffer; and for each memory cell to be programmed, program the memory cell according to the sub-data of K bits to be written to the memory cell and the pseudo-data corresponding to the sub-data (NK) bits to be written to the memory cell in the at least one buffer, such that a threshold voltage of the memory cell falls within one of 2K voltage ranges selected from 2N voltage ranges, wherein the 2N voltage ranges are 2N data patterns included in the binary data of N bits in a one-to-one correspondence.

2. The memory device as claimed in claim 1, wherein the 2K voltage ranges selected from the 2N voltage ranges are discontinuous.

3. The memory device as described in claim 1, wherein N is 3 and K is 2, and the control logic circuit inputs each of the sub-data to an XNOR logic gate to generate the pseudo-data corresponding to each of the sub-data.

4. The memory device as described in claim 1, wherein N is 3, K is 1, and the control logic circuit generates pseudo data of two bits (11) corresponding to each of the sub-data.

5. The memory device as claimed in claim 1, wherein the control logic circuitry is further configured to: in response to the write command, when the first parameter is N, divide the first data into sub-data of N bits and store the sub-data in the at least one buffer; and for each memory cell to be programmed, program the memory cell according to the sub-data of N bits to be written to the memory cell in the at least one buffer, such that a threshold voltage of the memory cell falls within one of the 2N voltage ranges.

6. A method of operating a memory device, comprising: Receive a write request and first data from a master controller; A write command is sent according to the write request, indicating a first parameter, wherein the first parameter represents the number of bits of binary data to be written to each memory cell, wherein each memory cell is configured to store up to N bits of binary data, where N is a positive integer greater than 1; in response to the write command, when the first parameter is a positive integer K less than N, the first data is divided into sub-data for every K bits, a pseudo-data corresponding to each sub-data (NK) bits is generated, and the sub-data and the pseudo-data are stored in at least one buffer; and for each memory cell to be programmed, the memory cell is programmed according to the sub-data of K bits to be written to the memory cell and the pseudo-data corresponding to the sub-data (NK) bits to be written to the memory cell in the at least one buffer, such that a threshold voltage of the memory cell falls within one of 2K voltage ranges selected from 2N voltage ranges, wherein the 2N voltage ranges correspond one-to-one to 2N data patterns included in the N bits of binary data.

7. The operating method as described in claim 6, wherein the 2K voltage ranges selected from the 2N voltage ranges are discontinuous.

8. The operation method as described in claim 6, wherein N is 3, K is 2, and each of the sub-data is input to an XNOR logic gate to generate the pseudo-data corresponding to each of the sub-data.

9. The operation method as described in claim 6, wherein N is 3, K is 1, and the pseudo data generated for each of the sub-data is two-bit binary data 11.

10. The operating method as described in claim 6 further includes: In response to the write command, when the first parameter is N, the first data is divided into N bits as a sub-data and the sub-data is stored in the at least one buffer; and for each memory cell to be programmed, the memory cell is programmed according to the N bits of sub-data to be written to the memory cell in the at least one buffer, such that a threshold voltage of the memory cell falls within one of the 2N voltage ranges.

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