Display system and a voltage controller thereof

Abstract

A voltage controller for a display system includes a gate high voltage detector for detecting a gate high voltage and a gate low voltage detector for detecting a gate low voltage. The gate high voltage and gate low voltage are provided to a gate driver, and the gate high voltage is greater than the gate low voltage.

Description

[Technical Field]

[0001] This invention relates to a display system, and more particularly to a display system suitable for electronic shelf labels. [Previous Technology]

[0002] Electronic shelf labels (ESLs) can be used in retail stores to display the prices of goods on shelves. When prices change, a central server automatically updates the prices on the labels. Electronic shelf labels use electronic paper (E-paper) technology to display prices, and the displayed content does not require power; power is only used when updating prices, thus significantly reducing power consumption.

[0003] A boost converter is a DC-to-DC power converter used to increase the input voltage. Boost converters are commonly used in electronic shelf labels to provide the required power voltage to the driver. For larger display panels, two boost converters are usually required to ensure that the power voltage remains at its rated value regardless of the load, but this increases cost and circuit area.

[0004] Therefore, there is an urgent need to propose a novel mechanism to overcome the shortcomings of traditional electronic shelf labels. [Summary of the Invention]

[0005] In view of the above, one of the objectives of the embodiments of the present invention is to provide a display system that is applicable to electronic shelf labels and can effectively maintain the power supply voltage at the rated voltage value.

[0006] According to an embodiment of the present invention, a display system includes a display panel, a gate driver, a source driver, a power converter, and a voltage controller. The display panel includes a plurality of pixels arranged in a matrix. The gate driver enables a pixel column of the display panel, and the source driver provides image data to a pixel row of the display panel. The power converter generates a power supply voltage to the gate driver. The voltage controller detects the power supply voltage generated by the power converter to generate a control signal for controlling the power converter.

[0007] In one embodiment, the voltage controller includes a gate high voltage detector and a gate low voltage detector. The gate high voltage detector detects a gate high voltage, and the gate low voltage detector detects a gate low voltage. The gate high voltage and gate low voltage are provided to the gate driver, and the gate high voltage is greater than the gate low voltage.

Implementation Method

[0008] The first figure shows a block diagram of the display system 100 of the present invention, which can be applied to electronic shelf labels, but is not limited thereto.

[0009] In this embodiment, the display system 100 may include a display panel 11 (e.g., electronic paper), which includes a plurality of pixels arranged in a matrix. The display system 100 may include a gate driver 12 for turning on the pixel columns of the display panel 11; and a source driver 13 for providing image data to the pixel rows of the display panel 11. The display system 100 may include a timing controller 14 for coordinating the control of the gate driver 12 and the source driver 13.

[0010] The display system 100 may include a power converter 15 for generating a power supply voltage to the gate driver 12. In this embodiment, the power converter 15 may include a boost converter 151 for generating a gate high voltage VGH to the gate driver 12; and a charge pump circuit 152 for generating a gate low voltage VGL to the gate driver 12. The gate high voltage VGH (typically a positive voltage) is greater than the gate low voltage VGL (typically a negative voltage).

[0011] The display system 100 may include a voltage regulator 16, such as a low-dropout (LDO) regulator, which receives the power supply voltage generated by the power converter 15 to generate a regulated voltage for the source driver 13.

[0012] The display system 100 may include a voltage controller 17 that detects the power supply voltage generated by the power converter 15 to generate a control signal GDRP to control the power converter 15 so that the gate high voltage VGH and gate low voltage VGL are maintained at rated voltage values. In this embodiment, the voltage controller 17 may include a gate high voltage detector 171 for detecting the gate high voltage VGH. According to one feature of this embodiment, the voltage controller 17 further includes a gate low voltage detector 172 for detecting the gate low voltage VGL.

[0013] The second figure shows the circuit diagram of the power converter 15 in the first figure. In this embodiment, the boost converter 151 mainly includes an inductor L, a switch SW, a first diode D1, and a first capacitor C1. Specifically, the inductor L and the switch SW (e.g., an N-type metal-oxide-semiconductor (NMOS) transistor) are connected in series between the (system) power supply VDD and ground, wherein the inductor L and the first end of the switch SW are connected to the first node LX, and the switch SW (e.g., the gate of the NMOS transistor) is controlled by the control signal GDRP (of the voltage controller 17). The first diode D1 and the first capacitor C1 are connected in series between the first node LX and ground, wherein the anode of the first diode D1 is connected to the first node LX, and one end of the first capacitor C1 is connected to ground. The other end of the first diode D1 and the first capacitor C1 is connected to the second node VGH to provide the gate high voltage VGH.

[0014] In this embodiment, the charge pump circuit 152 mainly includes a second diode D2, a third diode D3, a second capacitor C2, and a third capacitor C3. Specifically, the second diode D2 and the third diode D3 are connected in series in the forward direction between a third node VGL and ground. This third node provides a gate low voltage VGL, wherein the anode of the second diode D2 is connected to the third node VGL, and the cathode of the third diode D3 is connected to ground. The connection point of the second diode D2 and the third diode D3 is connected to the first node LX via the second capacitor C2. The third capacitor C3 is connected between the third node VGL and ground.

[0015] During operation, when the switch SW is turned on, the current mainly flows from the inductor L to the switch SW, causing the inductor L to store energy. When the switch SW is turned off, the current mainly flows from the inductor L to the first capacitor C1, causing the inductor L to lose energy, thus providing a gate high voltage VGH at the second node VGH.

[0016] During operation, when the switch SW is open, the current mainly flows from the second capacitor C2 to the third diode D3, causing the second capacitor C2 to store energy. When the switch SW is closed, the current mainly flows from the third capacitor C3 through the second diode D2 to the second capacitor C2, causing the second capacitor C2 to release energy, thus providing a gate low voltage VGL at the third node VGL.

[0017] Figure 3 shows the circuit diagram of the voltage controller 17 in Figure 1. In this embodiment, the gate high voltage detector 171 may include a first voltage divider 1711 to obtain a first voltage division of the gate high voltage VGH. The gate high voltage detector 171 may include a first comparator 1712, which compares the first voltage division with a first reference voltage V1 to generate a first enable signal EN1. Thereby, when the gate high voltage VGH is less than a preset first threshold value, the first comparator 1712 (of the gate high voltage detector 171) generates an active first enable signal EN1.

[0018] The gate low voltage detector 172 of this embodiment may include a second voltage divider 1721 to obtain a second voltage divider for the gate low voltage VGL. The gate low voltage detector 172 may include a second comparator 1722, which compares the second voltage divider with a second reference voltage V2 to generate a second enable signal EN2. Thereby, when the gate low voltage VGL is greater than a preset second threshold value, the second comparator 1722 (of the gate low voltage detector 172) generates an active second enable signal EN2.

[0019] The voltage controller 17 in this embodiment may include a logic circuit 173, such as an OR gate. When the first enable signal EN1 or the second enable signal EN2 is active, the first enable signal EN1 or the second enable signal EN2 passes through the logic circuit 173 (to turn on the switch SW) to control the power converter 15, so that the gate high voltage VGH and the gate low voltage VGL are maintained at the rated voltage values.

[0020] The voltage controller 17 of this embodiment may further include a control signal generation circuit 174, which generates a control signal GDRP based on the first enable signal EN1 or the second enable signal EN2 output by the logic circuit 173 and the detection signal RESEP of the power converter 15 (e.g., the second terminal voltage of the switch SW, e.g., the source voltage of an N-type metal-oxide-semiconductor transistor). In one embodiment, when the detection signal RESEP is greater than a (third) preset threshold value, the conducting switch SW is turned off.

[0021] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of the patent application of the present invention; any equivalent changes or modifications made without departing from the spirit disclosed in the invention shall be included in the scope of the patent application below. [Simplified Explanation of the Diagram]

[0022] Figure 1 shows a block diagram of the display system according to an embodiment of the present invention. Figure 2 shows a circuit diagram of the power converter in Figure 1. Figure 3 shows a circuit diagram of the voltage controller in Figure 1.

Claims

1. A display system comprising: a display panel including a plurality of pixels arranged in a matrix; a gate driver for turning on a pixel column of the display panel; a source driver for providing image data to a pixel row of the display panel; a power converter for generating a power supply voltage to the gate driver; and a voltage controller for detecting the power supply voltage generated by the power converter and generating a control signal for controlling the power converter; wherein the power converter includes: a boost converter for generating a gate high voltage to the gate. A driver; and a charge pump circuit for generating a gate low voltage to the gate driver, wherein the gate high voltage is greater than the gate low voltage; wherein the boost converter includes: an inductor; a switch, the inductor and the switch being connected in series between a power source and ground, a first terminal of the inductor and the switch being connected to a first node, and the switch being controlled by a control signal; a first diode; and a first capacitor, the first diode and the first capacitor being connected in series between the first node and ground, the anode of the first diode being connected to the first node, and the first diode... The body is connected to the first capacitor at the second node to provide the gate high voltage; wherein the voltage controller includes: a gate high voltage detector for detecting the gate high voltage; and a gate low voltage detector for detecting the gate low voltage; wherein the gate high voltage detector includes: a first voltage divider for obtaining a first voltage division of the gate high voltage; and a first comparator that compares the first voltage division with a first reference voltage, and when the gate high voltage is less than a preset first threshold value, the first comparator generates an active first enable signal; wherein the gate... The ultra-low voltage detector includes: a second voltage divider for obtaining a second voltage division of the gate low voltage; and a second comparator for comparing the second voltage division with a second reference voltage. When the gate low voltage is greater than a preset second threshold value, the second comparator generates an active second enable signal. The voltage controller further includes: a logic circuit that, when the first enable signal or the second enable signal is active, can be used to turn on the switch to control the power converter, so that the gate high voltage and the gate low voltage are maintained at the rated voltage value.

2. The display system of claim 1, wherein the display panel includes electronic paper.

3. The display system of request item 1 further includes a timing controller for coordinating the control of the gate driver and the source driver.

4. The display system of claim 1 further includes: a voltage regulator that receives the power supply voltage generated by the power converter to generate a regulated voltage for the source driver.

5. The display system of claim 1, wherein the charge pump circuit comprises: a second diode; a third diode connected in series with the second diode and the third diode in a forward direction between a third node and ground, the third node providing the gate low voltage; a second capacitor connected to the first node via the second capacitor at the connection node of the second diode and the third diode; and a third capacitor connected between the third node and ground.

6. The display system of claim 1, wherein the switch comprises an N-type metal-oxide-semiconductor transistor.

7. The display system of claim 1, wherein the voltage controller further comprises: a control signal generating circuit that generates the control signal based on a first enable signal or a second enable signal output by the logic circuit and based on a detection signal of the power converter.

8. The display system as requested in item 7, wherein the detection signal is the voltage at the second terminal of the switch.

9. The display system of request item 8, wherein when the detection signal is greater than the third preset threshold, the activated switch is turned off.

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