Multi-loop signal processing

Abstract

A signal processing circuit includes a first signal loop having a first signal processing block and a first feedback path extending around the first signal processing block. The first signal processing block has a frequency dependence that causes a passband to be generated in the first signal loop. A second signal processing block is downstream of the first signal loop. A second feedback path extends from downstream of the second signal processing block to upstream of the first signal processing block. In operation, the first feedback path amplifies a signal in the passband, and the second feedback path modulates the signal at an output downstream of the first signal processing block.

Description

Technical Field

[0001] This invention relates to radio frequency signal processing, and more specifically, to a multi-loop signal processing architecture. Prior Technology

[0002] Tunable radio frequency (RF) filters are used in wireless communications as part of the overall processing of received RF signals to extract signal information. Conversely, such tunable filters have been used as part of the process of encoding information onto RF signals, and as part of wireless communication.

[0003] One type of resonator is the LC tank, although other types of resonators are also known. Within an LC tank, the resonant frequency can be controlled by varying the capacitance, for example, via a continuously adjustable capacitor (such as a variable capacitor controlled by a variable bias voltage), or via a set of discrete capacitors (such as a set of switched capacitors), or a combination of continuous and discrete capacitors. Implementations of other LC resonators with variable capacitance (L) are also applicable, as the resonator can also be composed of distributed components. The foundation of a resonator is a structure capable of storing energy in multiple modes, and the characteristics of the resonator are a result of mechanisms for exchanging energy between these modes.

[0004] Tunable RF filters are typically characterized by control inputs that adjust the center frequency and bandwidth of a resonator, which contains the filter. Operating center frequency, bandwidth, tuning range, resonator stability, and inherent noise sources are just a few important aspects describing the performance of these tunable RF filters. Additional control over external factors such as temperature- or time-dependent component aging needs to be considered.

[0005] RF signals typically refer to relatively narrow-band signals, allowing them to be associated with relatively high carrier frequencies. The baseband frequency (BB) is used to imply any relatively low frequency. Typically, the RF frequency is at least 10 times the BB frequency.

[0006] Available radio architectures primarily consist of interchangeable discrete modules designed to meet the required radio frequency (RF) bands and process incoming RF signals. These modules are designed for discrete frequency ranges. Typically, carrier frequencies can be set at any frequency from 1 MHz at the low end to 100 GHz at the high end, but are not limited to this.

[0007] Currently, discrete-band radio (RF) modules deploy direct-sampling software to process incoming RF signals, and are commonly referred to as Software Defined Radio (SDR). The Direct-Sampling Software Defined Radio (DSDR) 10 shown in Figure 1 is a state-of-the-art SDR architecture that eliminates the need for system processing components such as RF filtering, down-conversion circuits, intermediate frequency (IF) analog processing, and baseband analog processing. The DSDR 10 includes an antenna 12, an analog-to-digital converter (ADC) 14, a digital signal processing (DSP) block 20, a digital-to-analog converter (DAC) 16, and an amplifier 18. It is a direct RF-to-baseband architecture, as shown in Figure 1, and is a universal receiver adaptable to any radio signal architecture, appropriately tuned to the desired RF signal band, and adjustable for the signal center frequency and signal frequency bandwidth.

[0008] For ease of illustration, antenna 12, as shown in Figure 1, has separate connections for the receiver and transmitter. A broadband RF method can be implemented to accommodate a single-port antenna.

[0009] This existing SDR 10 architecture is implemented using state-of-the-art ADC 14 and DSP 20 signal processing hardware, which can provide clock rates up to tens of GHz. Therefore, DSDR 10 can be implemented for a radio frequency range from 1 MHz to 40 GHz, and the firmware can be changed simply by plugging in a band-specific module.

[0010] In the ideal DSDR 10 of Figure 1, the ADC 14 maps the entire RF spectrum into a digitized signal. This requires a large number of high-speed DSDR 10 systems, i.e., the DSP 20 connected after the ADC 14 in the DSDR 10 system. Therefore, while the efficiency of the recently available multi-Gsps ADC 14, up to 60 Gsps, is indeed impressive (although power consumption is high), the DSP 10 needs to perform multiple processing steps at a very high clock rate and a moderate word width before it can downsample the signal to an integer multiple of the clock rate.

[0011] One problem with the DSP 20 series, but usually a bigger problem is that the ADC 14 must have sufficient dynamic range so that quantization noise at the lower end does not affect the receiver's NF, while at the upper end, it does not saturate due to a large amount of unwanted interference mixed into the desired signal.

[0012] This situation has been somewhat alleviated with the recent emergence of chip-type bandpass filters (BPFs) 22 in front-end modules (as shown in Figure 2). Currently available tunable BPFs 22 cover a discontinuous frequency range up to 40 GHz, with their tunable responses offering only relatively discrete but wide bandpass performance. Additional fine-tuning is degraded to off-chip discrete-frequency surface acoustic wave (SAW) or bulk acoustic wave (BAW) filtering with narrower bandwidth and higher Q performance, although difficulties are typically encountered above approximately 6 GHz. As fixed, narrow-bandwidth, fine-tuning off-chip components, these devices occupy a significant amount of space on mobile device circuit boards. While SAW / BAWs are typically 10 square millimeters in size, modern mobile devices can contain more than 30 SAW / BAW devices. Not only the size of the SAW / BAWs, but also the connection terminals and the distribution of collective SAW / BAW ground planes increase the overall circuit board size. However, given the inevitable trend toward higher frequencies above 6 GHz, SAW / BAW is unlikely to participate in the trend toward higher operating frequencies. Summary of the Invention

[0013] According to one embodiment, a signal processing circuit for processing a signal is provided, comprising: a bandpass filter having a passband; a signal processing block downstream of the bandpass filter; a first feedback path extending from between the bandpass filter and the signal processing block to an upstream position of the bandpass filter; and a second feedback path extending from the downstream position of the signal processing block to the upstream position of the bandpass filter, wherein, in operation, the first feedback path amplifies the signal in the passband, and the second feedback path modulates the signal at one of the outputs downstream of the bandpass filter.

[0014] According to other embodiments, the signal processing unit may individually or in combination include one or more of the following features: the first feedback path may be a positive feedback path, the second feedback path may be a negative feedback path, and wherein the negative feedback path can suppress internal noise generated downstream of the bandpass filter; one center frequency, one frequency selectivity, or both of the center frequency and frequency selectivity of the bandpass filter may be tunable; the signal processing circuit may further include an adjustable scaling block in the first feedback path, the second feedback path, or both of the first and second feedback paths; the signal processing block may be subject to a first domain variable... The negative feedback path may include a second processing block applying a second domain transform, which is the inverse of the first domain transform; the signal processing block may include an analog-to-digital converter (ADC), and the second processing block may include a digital-to-analog converter (DAC); the internal noise may include quantization noise from the ADC; the signal processing circuit may further include a digital signal processor that modulates one of the signals in the negative feedback path; an output of the ADC may be connected to a digital signal processor as a receiving channel for a software-defined radio; the signal processing circuit may be included in the first feedback path, the second feedback path, and the second processing block. The signal processing circuit may include a phase control element in one of the first feedback path and the second feedback path; the signal processing circuit may include a plurality of bandpass filters and a plurality of first feedback paths connected in series, each bandpass filter including a corresponding first feedback path; the signal processing circuit may include a plurality of second feedback paths connected in parallel from downstream of the signal processing block to upstream of the plurality of bandpass filters and between adjacent bandpass filters; each of the first feedback path and the second feedback path may further include a gain element; the first feedback path may be a positive feedback path, the second feedback path may be a negative feedback path, and the signal processing circuit may include a phase control element in one of the first feedback path and the second feedback path; ... The signal processing circuit may further include a controller programmed with instructions to adjust the gain block of the positive feedback path to induce self-oscillation of the bandpass filter, and then adjust the gain block of the negative feedback path to stabilize the bandpass filter; the signal processing circuit may include a plurality of bandpass filters and positive and negative feedback paths; the signal processing block may be controlled to control one or more poles of a transfer function of the signal processing circuit; the bandpass filter may include an acoustic resonator and an adjustable phase control element; and the signal processing may include a plurality of acoustic filters and a switch for selecting one of the plurality of acoustic filters.

[0015] According to one embodiment, a signal processing circuit is provided, comprising a first signal loop having a first signal processing block and a first feedback path extending around the first signal processing block. The first signal processing block has a frequency dependence that causes the first signal loop to generate a passband. A second signal processing block is located downstream of the first signal loop. A second feedback path extends from downstream of the second signal processing block to upstream of the first signal processing block. In operation, the first feedback path amplifies a signal in the passband, and the second feedback path modulates the signal at an output downstream of the first signal processing block.

[0016] According to other embodiments, the signal processing circuit may include one or more of the following embodiments: the first feedback path may be a positive feedback path, the second feedback path may be a negative feedback path, and the negative feedback path can suppress internal noise generated downstream of the first signal processing block; the first signal processing block may include a resonator; one center frequency, one frequency selectivity, or both of the center frequency and frequency selectivity of the resonator may be tunable; it may have an adjustable scaling block in the first feedback path, the second feedback path, or both the first and second feedback paths; the second signal processing... The processing block may apply a first domain transform, and the second feedback path may include a third processing block applying a second domain transform, the second domain transform being the inverse of the first domain transform; the second signal processing block may include an analog-to-digital converter (ADC), and the third processing block may include a digital-to-analog converter (DAC); the internal noise may include quantization noise from the ADC; a digital signal processor may be present to adjust one of the signals in the second feedback path; an output of the ADC may be connected to a digital signal processor as a receiving channel for a software-defined radio; the first processing block, the third... The second processing block, or both the first and second processing blocks, may include at least one phase control element; the first processing block may include a plurality of bandpass filters connected in series, each bandpass filter including a corresponding first feedback path; one or more additional second feedback paths may exist, connected in parallel downstream of the second signal processing block between adjacent bandpass filters; the first feedback path may be a positive feedback path, the second feedback path may be a negative feedback path, and a controller may exist, the controller being programmed with instructions to adjust a positive gain region of the positive feedback path. The first signal processing block can cause the bandpass filter to oscillate, and then adjust one of the negative gain blocks of the negative feedback path to stabilize the bandpass filter; the second signal processing block can be controlled by a controller; the first signal processing block can include an acoustic resonator and an adjustable phase control element; the first signal processing block can include a plurality of acoustic filters and a switch to select one of the plurality of acoustic filters; there can be a signal input upstream of the first signal loop; there can be a signal input between the first signal processing block and the second signal processing block, and the second feedback path includes a negative gain block.

[0017] A method for processing a signal using a signal processing circuit, the signal processing circuit comprising: a first signal loop including a first signal processing block and a first feedback path extending around the first signal processing block, such that the first signal loop includes a passband; a second signal processing block downstream of the bandpass filter; and a second feedback path extending from downstream of the signal processing block to upstream of the first signal processing block, the method comprising the steps of: This causes the first signal loop to generate a filtered signal in the passband; The filtered signal is processed by the second signal processing block downstream of the bandpass filter, thereby adjusting an output signal at the output of the bandpass filter.

[0018] According to one embodiment, a dual-loop signal processing architecture is provided, which can be used, for example, for data acquisition in a front-end module (FEM), or for other suitable applications. The dual-loop architecture may include a set of fixed components whose configuration and operation are controllable by software. For some instances of an FEM connected to an antenna, this architecture may be suitable for both reception and transmission functions.

[0019] According to one embodiment, a signal processing circuit for processing a signal is provided, comprising: a bandpass filter having a passband; a signal processing block downstream of the bandpass filter; a first feedback path extending from between the bandpass filter and the signal processing block to an upstream position of the bandpass filter; and a second feedback path extending from the downstream position of the signal processing block to the upstream position of the bandpass filter. In operation, the first feedback path amplifies the signal in the passband, and the second feedback path modulates the signal at one of the outputs downstream of the bandpass filter.

[0020] In other embodiments, the signal processing circuit may include, individually or in combination, one or more of the following embodiments: the first feedback path may be a positive feedback path, the second feedback path may be a negative feedback path, and the negative feedback path may suppress internal noise generated downstream of the bandpass filter; a center frequency and a frequency selectivity, or both a center frequency and a frequency selectivity, of the bandpass filter may be tunable; an adjustable scaling block may be included in the first feedback path, the second feedback path, or both the first and second feedback paths; the signal processing block may apply a first domain transform, and the negative feedback path may include a second processing block applying a second domain transform, the second domain transform being the inverse transform of the first domain transform; the signal processing block may include an analog-to-digital converter (ADC), the second processing block may include a digital-to-analog converter (DAC); the internal noise may include quantization noise from the ADC; a digital signal processor may be present to adjust one of the signals in the negative feedback path, and an output of the ADC may be connected to a digital signal processor. As a receiving channel of a software-defined radio, it may have a phase control element in the first feedback path, the second feedback path, or each of the first and second feedback paths; it may have a plurality of bandpass filters and a plurality of first feedback paths connected in series, each bandpass filter may include a corresponding first feedback path, and it may have a plurality of second feedback paths connected in parallel from downstream of the signal processing block to upstream of the plurality of bandpass filters and between adjacent bandpass filters, each of the first and second feedback paths may further include a gain element, wherein the first feedback path is a positive feedback path and the second feedback path is a negative feedback path, and the signal may further include a controller programmed with instructions to adjust the gain block of the positive feedback path to cause the bandpass filter to self-oscillate, and then adjust the gain block of the negative feedback path to stabilize the bandpass filter; it may have a plurality of bandpass filters and positive and negative feedback paths; the signal processing block may be controlled to control one or more poles of a transfer function of the signal processing circuit.

[0021] According to one embodiment, a method is provided for processing a signal using a signal processing circuit, the signal processing circuit comprising: a bandpass filter having a passband; a signal processing block downstream of the bandpass filter; a first feedback path extending from between the bandpass filter and the signal processing block to an upstream position of the bandpass filter; and a second feedback path extending from a downstream position of the signal processing block to an upstream position of the bandpass filter. The method includes the steps of: filtering a signal in the bandpass filter and amplifying the signal within the passband using the first feedback path; processing the filtered signal using the signal processing block downstream of the bandpass filter; and adjusting an output signal at one of the downstream outputs of the bandpass filter.

[0022] According to other embodiments, the method may further include, individually or in combination, one or more of the following elements: the first feedback path may be a positive feedback path, the second feedback path may be a negative feedback path, and wherein adjusting the output signal may include suppressing internal noise generated downstream of the bandpass filter; enhancing the signal and adjusting the output signal may include controlling a gain factor, a phase, or a gain factor and a phase in each of the first and second feedback paths; the method may further include the step of controlling the bandpass filter by tuning a center frequency, a frequency selectivity, or both a center frequency and a frequency selectivity; the signal processing block may apply a domain transform, and the negative feedback path may include a second processing block applying a second domain transform. The second domain transform is the inverse transform of the first domain transform. The signal processing block may be an analog-to-digital converter (ADC), and the second processing block includes a digital-to-analog converter (DAC). The internal noise may include quantization noise from the ADC. A plurality of bandpass filters may be connected in series with a plurality of positive feedback paths. Each bandpass filter includes a corresponding positive feedback path, and there may be a plurality of negative feedback paths connected in parallel from the downstream of the signal processing block to the upstream of the plurality of bandpass filters and between adjacent bandpass filters. The method may further include the steps of adjusting the gain of one of the positive feedback paths to cause the bandpass filter to self-oscillate, and then adjusting the gain of one of the negative feedback paths to stabilize the bandpass filter. It may have a plurality of bandpass filters and positive and negative feedback paths.

[0023] According to one embodiment, a receiving module for a digital communication device is provided. The receiving module includes: a bandpass filter having a passband; an analog-to-digital converter (ADC) downstream of the bandpass filter, the ADC having an output connected to a processor of the digital communication device; a positive feedback path extending from between the bandpass filter and a signal processing block to an upstream location of the bandpass filter; and a negative feedback path extending from downstream of the signal processing block to upstream of the bandpass filter, the negative feedback path including a digital-to-analog converter (DAC); wherein, in operation, the positive feedback path amplifies the signal in the passband, and the negative feedback path suppresses internal noise generated downstream of the bandpass filter. The digital communication device may include a software-defined radio.

[0024] According to one embodiment, a signal processing circuit for a digital communication device is provided, comprising: an outer signal loop including an input, an output, and a conversion block adapted to perform a signal conversion operation on a signal being processed; and an inner signal loop including a tunable bandpass filter, the inner signal loop being nested within the outer signal loop such that the tunable bandpass filter is connected in both the inner and outer signal loops, and the conversion block is connected outside the inner signal loop.

[0025] According to other embodiments, the signal processing circuit may individually or in combination include one or more of the following: a center frequency, a frequency selectivity, a Q factor, or a combination thereof of the bandpass filter may be adjustable; the bandpass filter may include a plurality of resonator outputs; the transform block may include a processor block programmed with instructions to individually control the poles of a transfer function of the outer signal loop; the transform block may be adapted to apply a domain transfer to at least one of the resonator outputs; the transform block may receive the plurality of resonator outputs in parallel; the outer signal loop may be a negative feedback loop, and the inner feedback loop may be a positive feedback loop; the transform block may be in a signal path of the outer signal loop, or in a feedback path of the outer signal loop; the inner signal loop may include a positive feedback path, and the outer signal loop... The system includes a negative feedback loop that amplifies the signal in the passband and suppresses internal noise generated downstream of the bandpass filter. The signal processing block may apply a first domain transform, and the negative feedback path includes a second processing block applying a second domain transform, which is the inverse of the first domain transform. The signal processing block may include an analog-to-digital converter (ADC), and the second processing block may include a digital-to-analog converter (DAC). The internal noise may include quantization noise from the ADC. A digital signal processor may be included to adjust one of the signals in the negative feedback path. The external signal loop may include an output connected to a transmission device, and the internal signal loop may include an input upstream of the external signal loop of the tunable bandpass filter, which is connected to a receiving device.

[0026] Other embodiments of the circuits and methods described above will become apparent from the following discussion. Simple Explanation of the Diagram

[0027] These and other features will become more apparent from the following description with reference to the accompanying drawings, which are for illustrative purposes only and are not intended to be limiting in any way, wherein: Figure 1 is a schematic diagram of the prior art direct sampling software-defined radio. Figure 2 is a schematic diagram of a direct sampling SDR with interchangeable front-end bandpass filter modules. Figure 3 is a schematic diagram of the signal processing circuit. Figure 4 is a schematic diagram of the inner loop of the signal processing circuit. Figure 5 is a schematic diagram of the inner loop of the signal processing circuit. Figure 6 shows the response curve of the inner loop in Figure 5. Figure 7 is a schematic diagram of the sample-and-hold circuit. Figure 8 is a schematic diagram of the signal processing circuit for the processing. Figure 9 is a schematic diagram of the signal processing circuit. Figure 10 is a schematic diagram of a signal processing circuit with an additional post-processing block. Figure 11 is a schematic diagram of the signal processing circuit. Figure 12 is a schematic diagram of a signal processing circuit with multiple upstream loops. Figure 13 is a schematic diagram of a signal processing circuit with multiple upstream and downstream loops. Figure 14 is a diagram showing the pole placement of the signal processing circuit in Figure 5. Figure 15 is a schematic diagram of the signal processing circuit. Figure 16 shows the frequency response plot of the DPLP compared to a non-DPLP circuit. Figure 17 is a schematic diagram of a signal processing circuit with multiple feedback path processing. Figure 18 is a schematic diagram of the signal processing path of wireless signals through the signal processing circuit. Figure 19 is a plot showing the placement of poles that have shifted due to feedback processing. Figure 20 is a schematic diagram of the signal processing circuit. Figure 21 is a schematic diagram of the signal processing circuit. Figure 22 is a schematic diagram of the signal processing circuit. Figure 23 is a schematic diagram of an inner loop signal processing circuit with a switched capacitor bank. Figure 24a shows the NRC Bode plot of a digital resonator with a frequency five percent lower than that of the RF resonator. Figure 24b shows the NRC Bode plot of a digital resonator with the same frequency as the RF resonator. Figure 24c shows the NRC Bode plot of a digital resonator with a frequency 5 percent higher than that of the RF resonator. Figure 25 is a schematic diagram illustrating the cascade of two transfer functions. Figure 26 is a schematic diagram of the signal processing circuit. Figure 27 is a plot of the clock cycle for the circuit processing circuit. Figure 28 is a schematic diagram of the state-space model of a signal processing circuit. Figure 29 is a schematic diagram of the state-space model of a signal processing circuit. Figure 30 shows a Simulink model of the signal processing circuit. Figure 31 is a plot of the simulation output of the model in Figure 30. Figure 32 shows the Simulink model of the signal processing circuit. Figure 33 is a plot of the simulation output of the model in Figure 32. Figure 34 is a schematic diagram of a signal processing circuit with delay in the feedback path. Figure 35 is a plot of the frequency response difference of a signal processing circuit with time delay as a function of the normalized frequency. Figure 36 shows a Simulink model of a signal processing circuit with time delay. Figure 37 is a plot of the simulation output of the model in Figure 36. Figure 38 shows a Simulink model of the signal processing circuit. Figure 39 shows a comparison of continuous and discrete Bode plots. Figure 40 shows a Simulink model of a signal processing circuit with a bandpass phase shifter. Figure 41 is a plot of the simulation output of the model in Figure 40. Figure 42 shows the Simulink model of the signal processing circuit. Figure 43 is a plot of the Nyquist resonator (NRC) curve of the model in Figure 42. Figure 44 shows a Simulink model of the signal processing circuit. Figure 45 is a plot of the Nyquist resonator curve (NRC) of the model in Figure 44. Figure 46 is a schematic diagram of a signal processing circuit with a resonator containing a fixed capacitance value. Figure 47 is a plot of the normalized frequency response of the signal processing circuit. Figure 48 is a plot of the normalized frequency response of the signal processing circuit before and after DPLP processing. Figure 49 is a plot of the NRC segment surrounding the resonance point. Figure 50 is a plot of an example of NRC optimized for a relatively flat passband around the desired bandwidth throughout the closed-loop resonant frequency range. Figure 51 shows a simulated NRC diagram of a dual-pole resonator providing a flat passband response near the closed-loop resonant frequency and an optimized feedback DSP. Figure 52a shows a signal processing circuit with analog processing. Figure 52b shows a signal processing circuit with DSP state-space processing. Figure 53 shows a Simulink model of the signal processing circuit. Figure 54 shows the Simulink model of the signal processing circuit. Figure 55 is a plot of the simulation output of the model in Figure 54. Figure 56 shows the signal processing circuit configured for down-conversion and up-conversion. Figure 57 shows a signal processing circuit with a notch filter. Figure 58 shows a signal processing circuit with a notch filter and fundamental frequency processing. Figure 59 is a plot of the frequency response of a commercial variable filter. Figure 60 is a plot of the NRC of the commercial variable filter shown in Figure 59. Figure 61 is a plot of the NRC of a commercial variable filter. Figure 62 is a plot of the frequency response of a tunable bandpass filter. Figure 63 shows the frequency response plots of STF and QNTF. Figure 64 shows a signal processing circuit with a SAW filter. Figure 65 shows a signal processing circuit with multiple SAWs. Figure 66 is a plot showing the zeros and poles of a tunable bandpass filter Δ∑. Figure 67 is a plot showing the frequency response of the TSMC SAW filter. Figure 68 is a plot of the NRC of the TSMC SAW filter. Figure 69a is a plot of NRC with G = 0.5. Figure 69b is a plot of NRC with G = 0.7. Figure 69c is a plot of NRC with G = 0.9. Figure 70 is a plot of the NRC of the Q-enhanced SAW with G = 9 at 1.75 GHz. Figure 71 is a plot of the frequency response of Q-enhanced SAW at 1.75 GHz. Figure 72 is a plot of the frequency response of NTF and STF for the complex negative feedback loop gain with Go = 1j. Figure 73 is a plot of the frequency response of NTF and STF for the complex negative feedback loop gain with Go = 2j. Figure 74 is a plot of the frequency response of NTF and STF for the complex negative feedback loop gain with Go = 4j. Figure 75 is a plot of the NRC of a Q-enhanced SAW with inner loop signal enhancement G = 0.93 at 1.75 GHz. Figure 76 shows the frequency response of NTF and STF for the outer loop complex negative feedback loop gain Go = 4j and the inner loop signal enhancement G = 0.93. Figure 77 is a schematic diagram of typical direct scanning receiver processing. Figure 78a is a schematic diagram of the receiver. Figure 78b is a schematic diagram of a receiver with a bandpass filter. Figure 79 is a schematic diagram of a circuit with two inner loops. Figure 80 is a schematic diagram of a circuit with two inner loops and negative feedback. Figure 81 is a schematic diagram of a circuit with two inner loops and negative feedback. Figure 82 is a schematic diagram of a circuit with N inner loops. Figure 83 is a schematic diagram of the signal processing circuit. Figure 84 is a schematic diagram illustrating the signal processing circuit for inserting quantization noise. Figure 85 is a schematic diagram illustrating the signal processing circuit for inserting noise. Figure 86 is a schematic diagram of a signal processing circuit with output processing and feedback processing. Figure 87 is a schematic diagram of a cascaded integrator comb low-pass filter and integer multiple reduction sampling. Figure 88 is a schematic diagram of the anti-aliasing design of the prototype transceiver. Figure 89 is a schematic diagram of the receiver-side circuit. Figure 90a is a plot showing noise and the desired signal. Figure 90b is a plot showing the folded frequency band with and without a filter. Figure 91 is a schematic diagram of a circuit with analog downconversion. Figure 92 is a schematic diagram of a BPSK receiver with a unity element comparator. Figure 93 is a schematic diagram of a high-speed flash converter. Figure 94 is a schematic diagram of a sample-and-hold circuit. Figure 95 is a diagram of the Manchester code. Figure 96 is a schematic diagram of the signal processing circuit. Figure 97 is a schematic diagram of the signal processing circuit. Figure 98 is a plot showing the poles of a signal processing circuit. Figure 99 shows a Simulink model of the signal processing circuit. Figure 100 is a plot of the simulation results of the Simulink model in Figure 99. Figure 101 is a plot of the simulation results of the Simulink model of Figure 99 with different values. Figure 102 shows the Simulink model of the signal processing circuit. Figure 103 is a plot of the simulation results of the Simulink model in Figure 102. Figure 104 is a schematic diagram of the signal processing circuit. Figure 105a is a schematic diagram of the signal processing circuit. Figure 105b is a Simulink model of the signal processing circuit in Figure 105a. Figure 106 is a plot of the simulation results of the Simulink model in Figure 105b. Figure 107 is a schematic diagram of the signal processing circuit. Figure 108 is a schematic diagram of the signal processing circuit. Figure 109 is a schematic diagram of the signal processing circuit. Figure 110 is a schematic diagram of the signal processing circuit. Figure 111 is a schematic diagram of a first-order Δ∑ loop. Figure 112 shows a Simulink model of the signal processing circuit. Figure 113 is a plot of the simulation results of the Simulink model in Figure 112. Figure 114 shows a Simulink model of the signal processing circuit. Figure 115 is a plot of the simulation results of the Simulink model in Figure 114. Figure 116 is a schematic diagram of a signal processing circuit with a second-order negative feedback loop. Figure 117 is a schematic diagram of the equivalent fundamental frequency model of the signal processing circuit in Figure 116. Figure 118 is a plot of the trajectory of the closed-loop poles. Figure 119a is a schematic diagram of the signal processing circuit. Figure 119b is a Simulink model of the signal processing circuit in Figure 119a. Figure 120 is a plot of the simulation results of the Simulink model in Figure 119b. Figure 121 is a plot of the spectrum of the intermodulation output of the VBP-DSM, where the signal and interference are added to the quantization noise substrate. Figure 122 shows a Simulink model of the signal processing circuit. Figure 123 is a plot of the simulation results of the Simulink model in Figure 122. Figure 124 shows a Simulink model of the signal processing circuit. Figure 125 is a plot of the simulation results of the Simulink model in Figure 124. Figure 126 is a plot of the simulation results of the Simulink model of Figure 124 with different values. Figure 127 is a schematic diagram of a signal processing circuit with taps. Figure 128 is a schematic diagram of the signal processing circuit as part of the SDR. Figure 129 is a schematic diagram of the signal processing circuit as part of the SDR. Figure 130 is a schematic diagram of a signal processing circuit with two processing paths. Figure 131 is a schematic diagram of a signal processing circuit with multiple processing paths. Implementation

[0028] The signal processing circuit, typically identified by reference numeral 30, will now be described with reference to the accompanying drawings.

[0029] Referring to Figure 3, the signal processing circuit 30 has an input 32 and an output 34, and has a signal processing loop architecture that simultaneously utilizes the inner loop 40 and the outer loop 50 in parallel.

[0030] The inner loop 40 (also referred to herein as the upstream loop) includes a frequency-dependent upstream processing block 42 and an inner feedback path 45 extending around the upstream processing block 42. In many practical embodiments, the upstream processing block 42 may be a resonator or a bandpass filter. Other frequency-dependent components may also be used, which, in combination with the feedback path 45, produce a passband. The bandpass filter 42 may be a continuously time-tunable RF bandpass filter, implemented using Q-control to independently tune the filter center frequency and / or filter bandwidth. The inner loop 40 may have a positive feedback variable gain block 44 on the inner feedback path 45 as an active feedback filter (AFF) to amplify the input signal. Various components in the inner loop 40, such as the processing block 42 and the variable gain block 44, may be variable or tunable to control the output of the inner loop 40.

[0031] The outer loop 50 has a second or downstream signal processing block 54 and an external feedback path 55 extending downstream of the inner loop 40 and upstream of the processing block 42. In one example, signal processing may be performed by a discrete-time digital signal processing (DSP) block 52 that may involve domain transfer (ADC 54 and DAC 56). The outer loop 50 is also incorporated into the inner processing block 42 as a branch of the outer loop 50. There may be more than two outer loops 50, but these loops are parallel to the inner loop 40, and each of the possible multiple outer loops 50 shares the same inner loop tunable RF bandpass filter 42. The outer loop 50 may include a gain block (not shown).

[0032] In some embodiments, a dual-loop architecture, which may be referred to as Dual Parallel Loop Processing (DPLP), can be used to suppress internally generated noise. In this embodiment, the inner loop 40 may be a positive feedback loop that amplifies the signal within the desired passband, while the outer loop 50 may be a negative feedback loop that is tuned to negatively interfere with internally generated noise in the passband. In other embodiments, the DPLP architecture may be designed with or without a gain block in the outer loop. The signal processing circuit 30 may have a top-level architecture that provides a digitized signal output 34, as shown in FIG3. This output signal may undergo further processing. It should also be understood that the signal processing circuit 30 may have more than two loops (upstream or downstream loops) and these loops may be connected in parallel or in series. Therefore, although the terms dual-loop or DPSP may be used, possible designs may include more than two loops, as long as these loops include an inner (or upstream) loop and an outer (or downstream) loop.

[0033] The dual-loop architecture 30 can be a parallel combination of mixed-signal processing, which can combine both analog RF processing and digital RF processing. The illustrated embodiment includes a digital signal output 34. In some embodiments, such mixed-signal, dual parallel-loop processing (DPLP) can be implemented in a front-end module (FEM) of a wireless communication architecture and can be used in software-defined radio (SDR).

[0034] In the case where there is or is no gain block in the outer loop 50, the function of the inner loop 40 will be considered first, and then the function of the outer loop 50 will be considered.

[0035] [Inner Ring Road Treatment]

[0036] While various filter designs can be used in the inner loop 40, for the sake of simplicity, this document will only consider the configuration of the inner loop 40 shown in FIG. 4. It should be understood that, generally, the inner loop 40 has a bandpass filter 42 and a feedback path 45 having an inner feedback path processing block 44, which may be a variable gain block. It should be understood that the inner feedback path 45 of the inner loop 40 shown in FIG. 4 may be incorporated as part of a resonator element (such as an active feedback filter), or the feedback path 45 may be separate from or different from the processing block 42, such as if the processing block 42 is a different design that does not include the feedback path as an inherent component.

[0037] In some embodiments, the processing block 42 may be a resonator (such as a tunable bandpass filter (BPF)), which typically relies on resonator processing control to refine the frequency selectivity of the filter when processing the signal. Generally, this processing concerns the ability to adjust the center frequency and bandpass region. Furthermore, in general, active feedback in the form of a feedback gain element has been widely used to provide such bandwidth control in a manner known as Q-enhancement in order to control the bandwidth of signal processing.

[0038] As will be understood, bandwidth control methods typically refer to the movement of one or more resonator poles in the s-plane, which is the focus of design analysis. It should also be recognized that a resonator can have more than one pole.

[0039] For example, the context of this invention will be the more complex active feedback resonator signal processing. While the discussion focuses primarily on such active feedback filters (AFFs) in signal processing, other tunable filters, such as filters without active feedback, or other types of processing blocks, alone or in combination with the resonator, may also be used.

[0040] Referring to Figure 4, processing block 42 is a continuous-time, tunable bandpass resonator network 42, having a feedback processing block 44 within a feedback path 45. Control block 49 can be used to control the bandpass network 42 and the feedback processing block 44. Referring to Figure 5, the tunable resonator network 42 may include several tunable resonators 46, which may be LC combinations, although other resonator types are also possible. The resonators 46 in processing block 42 may also be packaged tunable resonators, such as resonator modules and SAW / BAW components. Although not shown, each resonator 46 may include a feedback path and a gain block, or a feedback path may exist around the resonator network 42.

[0041] Referring again to Figure 4, a relatively simple form of the feedback processing element is shown as a gain block 44 with a scaling factor applied. By setting this scaling factor, the dominant resonator pole can be moved toward the jω axis in the s-plane (Q-boost) or away from the jω axis (Q-suppression). Using variable feedback gain, the degree of Q-boost or Q-suppression can be controlled. Furthermore, by making the resonator poles variable, the frequency of the Q-modified poles can be tuned. The characteristics and control of the inner loop 40 can be modified by using one or more filter segments.

[0042] In one embodiment, the bandpass filter 42 may be an active positive feedback filter (PFF) within the signal loop 40, which 1) tunes the center passband frequency and 2) allows for Q-boost or Q-suppression of the resonator. Q-control is sufficient to allow for narrowband RF, microwave, and RF millimeter wave (RFMM) bandpass filters. This can be used in conjunction with the resonator 46 in the network discussed with respect to Figure 5. Alternatively, multiple signal loops 40 may exist, each with an individual resonator 42 or a resonator network. Additional signal loops may also be incorporated around these multiple signal loops. This versatility enables robust and stable operation and practical circuit implementations for moderate to high levels of Q-boost. One implementation may include multiple filter sections cascaded in a series topology resulting in an all-pole filter and a DC zero, but there are feasible applications for filter sections connected in parallel and in series.

[0043] [Variations of positive feedback filters]

[0044] The relevant variants of PFF in Figure 4 include: 1. As a resonator network, the bandpass filter 42 may contain more than one pole, and one or more of these poles may be Q-enhanced (moved toward the jω axis) or Q-suppressed (moved away from the jω axis). 2. Feedback processing 44 may include phase adjustments. These phase adjustments may be fixed or variable. 3. Components can be reordered in loop 40. 4. The input and output ports may be located at different points in loop 40.

[0045] Referring to Figure 5, active feedback can cause one or more poles of resonator 42 to be translated in the complex s-plane. Other filter architectures may include multiple network resonators 46 within bandpass filter 42, wherein each network resonator 46 may have one or more poles different from the other resonators 46 in the architecture.

[0046] When more than one pole exists in the s-plane, a dominant pole nominally located at the center of the passband may exist. Other poles tend to become less significant when determining the response of the resulting bandpass filter, but they are still important. Here, when referring to a single pole in the response of resonator network 46, it means the dominant pole.

[0047] Next, consider a resonator with P > 1 poles, where P = 3 is shown in Figure 5. Three variable filters 46 can be cascaded to implement the third-order Chebyshev tunable bandpass filter response shown in Figure 6. In this embodiment, the center frequencies are tuned sequentially to 1745, 1825, and 1930 MHz. Each variable filter 46 implements one pole of a multi-pole Chebyshev filter, with individual filters having a Q exceeding 1000. Such filters 42 can be designed to be stable using simple and robust tuning and calibration.

[0048] [Timing jitter and signal sampling]

[0049] Now consider the minimum sampling rate achievable using a multi-pole bandpass filter 42. Consider a data communication signal consisting of a sequence of consecutive symbols. The parameters of these symbols (e.g., amplitude or phase) contain data bits or information. Theoretically, if an analog filter is provided that "matches" the communication signal in terms of symbol shape and the Nyquist condition of "zero inter-symbol interference" (ISI), only one sample per symbol is needed. Other components can be incorporated, such as fixed-frequency upconversion and downconversion that can reduce the required sampling rate.

[0050] To reduce the demands on the ADC and subsequently the DSP, the sampling rate is a critical consideration, as the ADC's transition time must be small compared to the period of the highest frequency component being digitized. Referring to Figure 7, a general sample-and-hold circuit 70 is shown. The sample-and-hold circuit 70 has a FET gate 72 acting as a switch, which connects the input signal 74 to a capacitor 76 charged to a level close to the calibrated fraction of the signal amplitude. The current in capacitor 76 is significant, and the input signal driver 74 can have a low source impedance. Switch 72 then opens, and the capacitor voltage is buffered and becomes available to the ADC 78, which may require a longer transition time. The challenge lies in making the switch fast enough and the input signal have a sufficiently low impedance to drive the current in capacitor 76. For GHz signals, transition times can be on the order of tens of picoseconds (psec).

[0051] Another issue is the nonlinearity of FET gate 72, as the channel resistance depends on the input signal voltage and the voltage of capacitor 76. Furthermore, timing jitter of FET gate 72 is significant. The gate originates from a clock synthesizer, where the output comes from a logic gate. Timing jitter in dt increases the uncertainty of the final sampled (dv / dt)dt, where dv / dt is the slope of the input voltage. This leads to sampling uncertainty, which is related to the slope of the signal passing through noisy signals. Therefore, jitter-related noise can be mitigated by a low-phase-noise clock synthesizer and high-current logic; this is a dissipation problem. If the sampling is highly redundant, resulting in a sampling rate far exceeding the Nyquist rate commensurate with the signal bandwidth, a DSP can be used to reduce jitter. If the sampling redundancy is not significant, a DSP may not be able to improve noise caused by timing jitter.

[0052] The shorter the SH transition time, the fewer signal-related electrons enter the capacitor. The space charge in the FET channel of the switch is an additional source of electrons, which contributes to the capacitor charge depending on the drain and source voltages of the transition time, thus contributing to switching noise.

[0053] [Mixed-signal external parallel loop signal processing]

[0054] The following will cover the complex concepts of signal processing loops involving both real-time and digital-time processing. This will show that, among other features, the dual-loop processing concept reduces or eliminates spontaneous noise from the processing, such as quantization noise. Figure 8 illustrates these concepts, depicting the flow of signal path 80 through the dual loops of signal processing circuitry 30. However, the signal enhancement loop (inner loop 40) is real-time, while the noise processing loop (outer loop 50) is discrete-time, which can be difficult to reconcile in thought. In the embodiment shown in Figure 8, noise processing 82 passes through negative gain block 84 before being processed in bandpass filter 42. The desired signal 85 and interference, along with noise 86, enter the circuit at summing block 88, where noise processing 82 enters again. The signal may flow through the signal enhancement loop multiple times before it appears and destructively combines with the noise processing. When the initial noise processing is canceled out by the recycle noise, no further noise processing is output to the signal.

[0055] [Inner Ring Road Nyquist Resonator Curve Shaping]

[0056] The inner loop 40 has been discussed previously, primarily highlighting the benefits achieved through the positive feedback filter architecture. However, the positive feedback loop also serves another purpose: modifying the Nyquist resonator curve (NRC) of the resonator in the upstream signal loop (which can be called the upstream receiver). In this way, the negative feedback gain of the outer loop can be set to a higher negative gain value. This results in a controllable suppression of noise processing capabilities by the downstream receiver.

[0057] However, the negative feedback of the outer loop 50 effectively reduces the amplification of the desired signal 85 in the positive feedback of the inner loop 40. Therefore, to compensate for this effective reduction in the gain of the inner loop 40 due to the negative feedback gain of the outer loop 50, the positive feedback within the inner loop 40 can be made stronger. In fact, the gain of the inner loop 40 can be Ginner > 1 without loss of stability, and when the effective gain of the inner loop 40 is reduced by the negative feedback gain Gouter < 0, the effective Ginner again becomes Geffective < 1.

[0058] Therefore, these two loops interact. For a given signal bandwidth, the net signal enhancement is commensurate with the signal bandwidth. The inner loop enhancement is strong enough to alter the shape of the upstream receiver's NRC, allowing for sufficient negative feedback without the risk of loop instability.

[0059] [Overview and Significance of Mixed-Signal Dual-Loop Processing]

[0060] Figure 9 illustrates a typical dual-loop architecture 90 for the signal processing circuit 30. In Figures 9 through 13, the input signal is V(s) + I(s), block 92 corresponds to A(s) and represents the bandpass filter 42 of the upstream processing segment 91 of the receiver, block 96 corresponds to B(s) and represents the downstream processing segment 94 of the receiver, and Y(s) is the output of block 96. The upstream processing 91 relates to the inner loop 40 described above, which is configured as an active positive feedback filter for enhancing the input signal as described above. The upstream processing 91 includes a positive processing gain G1 in the gain block 93. The downstream processing 94 relates to the outer processing loop 50 described above, which may include a gain element represented by the gain block 97 with a gain G2. It should be noted that the gain element may be incorporated as part of the DSP, although not explicitly shown.

[0061] As used in this invention, s represents a complex frequency, such that A(s) in block 92 represents the frequency response processed by the upstream inner loop filter. Tap 98 is shown between upstream segment 91 and downstream segment 94 for reference. Tap 98 can be used as a nominal input for any noise 99 that may be introduced by the downstream outer loop processing 94. Noise 99 is denoted by Q(s).

[0062] The discussion of outer loop 50 above has mentioned that a gain element may or may not be present, although Figure 9 includes a gain element 97 as shown, allowing the feedback path of outer loop 50 to apply a G2 processing gain that can be positive or negative. In this embodiment, both feedback loops terminate at the summation point on the input side of the upstream receiver. The input signal 95 is V(s) + I(s), where V(s) is considered to be the desired bandpass signal, and I(s) is the noise and interference within the bandwidth of the desired signal. The output of the downstream receiver is 100-digitized signal content Y(s).

[0063] A(s) can refer to many different things. A(s) can be a resonator with a fixed or tunable frequency. A(s) can be a group of multiple resonators A(s) can be a filter or any network with some form of frequency dependence. A(s) can be a delay line, where the frequency dependence is the phase shift that increases with frequency. A(s) is a subsystem comprising filters and / or frequency translation stages and / or gain blocks.

[0064] B(s) includes components for domain transformation. Domain transformation can, for example, transform an input continuous-time signal into an output containing digitized samples, such as by using an ADC, or B(s) can be frequency-transformed so that the input to B(s) differs from the frequency at the output. The processing portion in the feedback path of the outer loop 50 may include domain transformation (not shown in Figure 9), which is the inverse of the domain transformation implicit in B(s). At the tap point, an additional signal of Q(s) is added to the signal flowing between the upstream and downstream receiver sections. This signal Q(s) is assumed to be very close to being independent of the input signals V(s) and I(s). This will be represented as equivalent noise injected at the input of B(s) during the processing of B(s).

[0065] The output 100 of the receiver (labeled Y(s)) is a frequency spectrum representation. This only indicates that the output may be a discrete-time sampled signal. Furthermore, since I(s) and Q(s) are stochastic procedures, strictly speaking, only the statistical properties of Y(s) are definable. Therefore, Y(s) should be understood as a representation of output, which facilitates discussion and does not mean a precise description of output.

[0066] In one embodiment, the processing of FIG. 9 may be used to transmit the desired signal of V ( s ) to the digitized output of Y ( s ) without deteriorating the information content of the detected desired signal. More formally, the loss of mutual information between V(s) and Y(s) can be reduced or minimized when the domain transformation of the desired signal is achieved in the downstream receiver. As an example, B(s) may include an ADC for quantifying an input signal sample. This is the domain transformation.

[0067] Thus, the output signal Y(s) indicates the meridional-domain transform variant of the input signal V(s), which is accompanied by some residual aliasing. It should be understood that additional post-detection processing is required in order to retrieve and extract relevant information from digitized Y(s) data as contained in V(s). Therefore, the post-detection processing block D was increased, as shown in Figure 10 . Here D denotes the post-detection processing block 102 , and I denotes the extracted information 104 . The post-detection processing block 102 may be implemented such that the loss of mutual information of the procedure from Y(s) to I is little or negligible.

[0068] Below, the architecture of Figure 10 can be implemented in a receiver front-end module. The treatment of D is beyond the scope of the invention. It is assumed that the processing of the front-end receiver and the domain transform can render the signal in a form compatible with the processing that can be effectively implemented in D . In summary, the upstream and downstream signal processing subsystems combined with the feedback path implementation enables the optimization of mutual information between the input desired signal V(s) and the transformed output Y(s) under the constraints of compatible embodiments of Y(s) and D in the presence of aliasing I(s).

[0069] In an important embodiment to the receiver, the inner loop 40 is a positive feedback loop with a gain G 1 , and the outer loop 50 has a negative feedback loop gain G The purpose of the positive loop is to enhance the desired signal V(s) with noise and interference relative to I(s) by narrowing the effective signal bandwidth through upstream processing so that it is more compatible with the V(s) bandwidth. This should indicate that the purpose of the negative feedback loop around the upstream and downstream receiver sections is to reduce the presence of the aliasing source of Q(s) in the output Y(s). This operation is obvious if the transfer function is considered.

[0070] When Q(s) = 0, the signal transfer function is defined as When V(s) = 0, the "quantization noise" transfer function is defined as follows: The noise of the downstream receiver is referred to in this invention as quantization noise, as it is generally associated with the quantizer / sampler. However, it is not limited to quantization noise and may include any noise that can be roughly estimated, as added as described above.

[0071] To simplify the calculation of the transfer function, the loop is reorganized as shown in Figure 11, where block 110 is... therefore, and

[0072] For example, let A(s) represent a single pole of the equivalent composite bandpass. This is a valid approximation if the response of the front-end receiver has a relatively narrow bandwidth. This simplification allows for a closed-form expression of the transfer function, facilitating the current discussion. Therefore, the form of A(s) is... Where p is a positive real value. With this C(s), block 110 becomes Then, substituting C(s) back into the transfer function, we get... as well as The zero appears in In, and not tied to Therefore, if the narrow bandwidth of V(s) is actually commensurate with the bandwidth of p, then first-order noise cancellation is obvious. This is the basis for the function of the feedback receiver in Figure 9. The internal positive feedback loop reduces the value of p, causing the pole of A(s) to move towards the jω axis (Q enhancement), and the bandwidth narrows to make it compatible with the bandwidth of V(s). The larger G1 is, the narrower the bandwidth. Conversely, it can be seen that the effect of the negative feedback gain of the outer loop is to establish a passband zero from this "Q enhancement" passband pole, thereby suppressing the equivalent noise generated by the downstream receiver.

[0073] In sum, both the internal and external feedback loops configured in the manner shown in Fig. 9 are necessary to process the input signal simultaneously. The phase mutual information can be shown to be optimally preserved by the joint cooperation of two feedback loops with the optimum return values ​​selected for G 1 and G 2 .

[0074] Evidently, A(s) may be any processing function with some frequency dependence near the frequency band center of the desired signal V(s). In this way, the positive feedback from the inner loop can be used to narrow the bandwidth of A(s). For example, A(s) may be any fixed or tunable bandpass filter as will be shown.

[0075] These expressions can be extended with the assumed transfer function B(s). However, the point is to insert the zero point Medium is the key feature.

[0076] The concept of dual-loop feedback can also be extended to the architecture shown in Figure 12 , where the upstream receiver contains a complex number of bandpass filters in series, each having a positive feedback loop for bandwidth narrowing. In Figure 12 , gain blocks 93a and 93b correspond to g1 and g2, respectively, and gain block 97 corresponds to g3.

[0077] Making A1(s) and A2(s) corresponding to blocks 92a and 92b, respectively, two first-order bandpass filters, the given composite bandpass is equivalent to it can be indicated of the closed loop will have corresponding to the q-enhanced poles and of the two zeros.

[0078] 13 , the pair can be achieved by adding additional negative feedback loops 55a and 55b and Further flexibility in the control of zero and extreme points of the transfer function. In Figure 13 , gain blocks 93a and 93b correspond to g1 and g2, respectively, and gain blocks 97a and 97b correspond to g3 and g4, respectively.

[0079] Closed expressions become more inefficient. However, the general structure of the positive and negative feedback paths may lead to the general architecture in There are multiple zero points in the passband.

[0080] Additional modifications can be made to enhance the performance and flexibility of the embodiments. The gain blocks 97a and 97b of {g1, g2, ...} in FIG13 can be expanded to include general processing blocks, as noted above, relative to purely scalar gain blocks. These may include domain transformations that are inverse to the transformation occurring in the downstream direction. For example, the transformation may be signal digitization or frequency shifting.

[0081] Further flexibility is achieved by converting the outer loop negative feedback path into a positive feedback path. Then, by processing the feedback path, any set of passband poles can be achieved. In this way, the passband frequency response can be arbitrarily shaped. Therefore, the resulting frequency response from the upstream and downstream receivers along with the feedback path can be spectrally shaped with sufficient frequency selectivity, eliminating the need for further post-detection processing.

[0082] The generalized feedback transfer functions {g1, g2, ...} can be dynamically configured so that the receiver can optimally respond to a variety of different input signal formats and noise. These transfer functions {g1, g2, ...} can be implemented in a DSP processor or an FPGA feedback processor, resulting in a very flexible form of software-defined radio.

[0083] [Generalized Feedback Loop in Radio Frequency Signal Domain and Control Processing]

[0084] The feedback processing proposed in this invention can be used to control the position of P-pole 140 on a pole-by-pole basis, as shown in Figure 14. Note that the resonator pole can be moved along the real axis to change Q, and / or moved along the jω axis to change the frequency. P-pole 140 can be moved from an initial closed-loop position 142 to a final closed-loop position 144. In this way, the resonator's P-pole 140 can be positioned to provide an arbitrary bandpass transfer function response. This is desired for implementing a bandpass filter with specified passband characteristics and out-of-band rejection. Since the active feedback affects all P-pole 140 in the desired manner, a generalized dual parallel loop processing (DPLP) can be produced.

[0085] As should be understood from the discussion in this paper, it is feasible to use feedback processing to place each resonator pole individually in the s-plane and to individually control the bandwidth (pole moves parallel to the horizontal axis) and frequency (pole moves parallel to the vertical axis) of the resonator.

[0086] We will now consider feedback processing for active filter (AFF), which can be used to achieve active multipole placement of the AFF. Generalized control theory concepts will be introduced and applied to the feedback processing function, and control systems can be implemented in different processing domains that characterize external observables of the resonator, such as frequency or phase. The signal in the AFF loop resides in the RF analog domain. The resonator output will be referred to as the RF analog signal, which also has domain A.

[0087] The characteristics of the signal processing circuit 30 (or DPLP) may include state-space domain transformation within the feedback loop, as shown in Figure 15. The input signal 32, inner loop 40, and output signal 34 will be considered in domain A. Within the outer loop 50, a transformation to another domain B may exist within the first transformation block 150, wherein the feedback processing 152 in domain B is subsequently transformed back to domain A in the second transformation block 154.

[0088] As will be shown in detail below, the result of enabling a three-pole resonator with DPLP can be used to provide a significant increase in bandwidth, as shown in Figure 16.

[0089] In DPLP, domain A can be considered radio frequency analog. Domain B may differ from domain A, with several possibilities including, but not limited to: The frequency of the radio frequency analog domain B is different from that of domain A. Low-frequency fundamental analog domain Discrete-time sampling domain (analogous to discrete-time samples of the signal) Digital domain (digitized discrete-time samples of a signal)

[0090] One advantage of this domain transformation is that feedback processing in a domain different from the RF signal domain A is generally easier and more practical to implement. For example, if domain B is digital, the feedback processing can be implemented in a digital signal processing (DSP) 52. Complex processing functions can be easily implemented in a DSP, which is impractical in analog RF.

[0091] Common applications of AFF (Area-of-Fluid) include narrow-bandwidth filtering of the wireless signal intercepted by the antenna before down-conversion and digitization. Interference and noise outside the desired signal bandwidth can overwhelm the desired signal, potentially causing irreversible damage during down-conversion and digitization. Therefore, a bandpass filter commensurate with the desired signal bandwidth is needed to suppress this interference and noise. Using DPLP (Digital Peripheral Filtering), more complex feedback signals can be robustly implemented.

[0092] Furthermore, with increased pole energy storage, the DPLP can withstand the large signal amplitudes that may exist in high-Q pole filters. This allows feedback synthesis to be based on multidimensional state-space processing. As will be developed, this allows multiple resonator poles to be Q-enhanced simultaneously and arbitrarily placed in the s-plane with a single feedback loop. Therefore, complex tunable multi-pole bandpass filter responses can be synthesized.

[0093] As mentioned above, although this invention discusses a dual-loop architecture, this is for convenience, because multiple linearly independent observations can be emitted from the resonator, and these observations may be simultaneously transformed in parallel to multiple domains and acted upon by a plurality of feedback domain processors. This can be called Multiple Parallel Loop Processing (MPLP). It should be understood that DPLP is described and depicted here for ease of understanding, and these principles can also be incorporated into the MPLP architecture. These multiple linearly independent signals generated by multiple parallel feedback processing paths can be simultaneously fed back to the resonator after being transformed back to domain A. For example, a low Q value requires low latency in the DSP, but this is not always feasible. However, low latency can be achieved in the analog domain.

[0094] Figure 17 illustrates an example of an MPLP, depicting multiple parallel feedback processing paths 55a and 55b. In this embodiment, feedback processing path 170a is similar to the feedback paths 170b in Figure 15. Following the inner loop 40 in the state space domain A, each independent processing path is fed state information Nj; In the third transformation block 150b, the state information is transformed to domain j; The status information of field j in the second feedback process 152b; In the fourth transformation block 154b, the processed state information is transformed back into domain A; Post-processing status information in domain A is fed back to the inner loop 40 input.

[0095] An embodiment of the signal processing circuit 30 in Figure 17 is shown in Figure 18, illustrating the processing of the radio processing block. The radio signal is first received by the antenna 172, processed by the initial BPF 174, then amplified by the initial amplifier 176 and fed into a processing loop including an inner feedback path 45 and an outer feedback path 55. The inner feedback path has an RF feedback gain 178 and a bandpass filter 42, while the outer feedback path has an ADC 54, a DAC 56, and a DSP 52.

[0096] An RF feedback gain of 178 is used for delay mitigation and low-Q enhancement of the received input signal. A loop with DSP 52 is used for higher Q enhancement of data acquisition and general signal processing.

[0097] [Resonator and Processing Block]

[0098] Referring to Figure 3, in the discussion of this invention, the signal processing circuit 30 can generally be described as having a resonator 42 (in the inner loop 40) and a processing block 52 (in the outer loop 50) in a dual parallel signal loop 30. It should be understood that the resonator 42 and the processing block 52 can be varied to achieve the desired result. For example, the resonator 42 can be any suitable resonator, such as a single-pole resonator, a multi-pole resonator, a SAW filter, a BAW filter, an active feedback filter (AFF), a fixed-frequency filter, a variable-frequency filter (continuously variable or with discrete frequencies), etc. Alternatively, the resonator 42 can be a complex circuit with multiple resonant components, multiple feedback and / or feedback paths, etc. These design configurations are obvious to those skilled in the art and will not be described further. The processing block 52 can be a separate component and may not be contained within a common housing, or even on a common substrate. It should be understood that the processing block 52 can be defined as including different components acting on the output from the resonator 42. In some cases, a specific signal path within a DPLP can be defined as part of the resonator or a processing block. This is primarily to facilitate understanding and control of the DPLP's operation without altering its overall function, or to maintain the overall effect of individual components or single signal paths on the DPLP.

[0099] [use] [DPLP] [Resonator pole placement]

[0100] The number of poles of a P-type resonator (with positive complex natural mode frequencies). Setting P poles to arbitrary positions represents 2P constraints, because each pole has a real part and an imaginary part, and the feedback process has a minimum of 2P degrees of freedom (DOF) when acting on N inputs to produce M outputs.

[0101] Furthermore, it is assumed that the resonator at pole P can be adjusted by externally setting the natural resonant frequency of individual poles. Therefore, this is P DOF, meaning that feedback processing requires P additional DOFs.

[0102] Regardless of the details of the feedback processor, it requires forming approximate derivatives and integrals of N observables and a linear superposition of the variable sets to generate M outputs. If domain B is a DSP, then providing such linear operations is negligible. However, if domain B is a fundamental or radio frequency analog processing, the implementation of linear analog operations quickly becomes inefficient as P increases beyond P = 1. Similarly, the domain transformation within the DPLP feedback loop between domains A and B allows domain A to be radio frequency and domain B to be a DSP. The DSP allows for practical implementations of the feedback processing such that the P poles can be placed arbitrarily and simultaneously.

[0103] Based on this, for example, a multi-pole resonator with P = 3 may exist in a DPLP. The feedback processor operation places these three poles as the feedback signal for a third-order Chebyshev bandpass filter. The Chebyshev poles can be placed close to the jω axis to provide a high-frequency selective narrowband filter, as shown in Figure 19.

[0104] [generally] [DPLP] [Formal Theory of Resonator Analysis]

[0105] A discussion of an example analysis of signal processing circuit 30 (or DPLP) will now be provided, as shown in the closed loop of Figure 20.

[0106] The resonator has a transfer function with respect to poles and zeros, which can be expressed as: The numerator polynomial of N(s) is a complex frequency of continuous time. The denominator polynomial of D(s) is a complex frequency of continuous time.

[0107] In DPLP, an active feedback filter (AFF) is added, which has a transfer function. Hfp(s) may include active gain elements. Figure 20 illustrates the closed loop, where block 202 corresponds to H res(s), and some or all of the processing is performed in the inner loop 40, and block 204 has a transfer function Hfp(s), and some or all of the processing is performed in the outer loop 50. []

[0108] The closed loop is given as [] The denominator polynomial (DB-NA) has the roots of the closed-loop poles. By designing the A and B feedback polynomials, the poles can be moved to any desired location.

[0109] Therefore, the goal of DPLP is to solve for A and B, such that... The root is located at the desired position in the s-plane.

[0110] The situation is that, Such implementations are not easily achieved in continuous-time radio frequency space. However, domain transformations in discrete-time space (typically from radio frequency to digital) can be implemented in discrete time. China achieves continuous time An equivalent version is provided, where coefficients A and B can be easily changed for different tunings because this is a digital implementation. This procedure is shown in Figure 21, where ADC 54 and DAC 56 are shown in the closed loop and represent continuous and discrete time-domain transformations. Other domain transformations, as described in this invention, can also be used.

[0111] Given H res(s), the feedback transfer function of H fb(z) can be determined to obtain the desired passband response of the closed loop.

[0112] Referring to the DPLP block diagram in Figure 22, the front end has an antenna 222 (which is a matched LNA bandpass filter) and some form of variable gain (which is set to optimize the final output SNR). This is a trade-off between a) the quantization noise generated by the ADC 54 and b) the saturation risk of the ADC 54. The filter of the wideband but finitely tunable front end protects the ADC 54 from excessive noise, and H res(s) can be tuned by varying the resonator LC value. The ADC can also be replaced with a standard Δ-∑, which is another way to shift the quantization noise out of the passband.

[0113] The DPLP 30 has two parallel feedback paths: 1. Feedback path 55a is a continuous-time direct RF path H fbrf(s) (represented by block 206) for feedback where delay is intolerable. 2. The slower feedback path 55b is the H fb(z) path (represented by block 204), which is then converted back to analog and loops through H res(s) (represented by block 202).

[0114] In this way, some preliminary Q-enhancement systems of H res(s) block 202 are feasible, providing additional mitigation for the nonlinearity of potential ADC blocks.

[0115] [use] [DPLP] [Continuous frequency transformation]

[0116] The inner loop 40 may include a tunable resonator with a variable capacitor or a switched capacitor bank for resonant frequency tuning based on the resonant LC resonant cavity. However, a variable capacitor with high Q-factor and linearity may be difficult to integrate into the chip circuit. The bias tuning voltage may also be problematic, potentially being excessively high to minimize distortion effects. Therefore, one implementation for changing the capacitance of the analog LC resonant cavity may be via the switched capacitor bank 233. Other types of resonators with different considerations may be used.

[0117] The DPLP domain transform provides the ability to adapt a resonator that can only be tuned in discrete steps. One embodiment is a resonator tuned using switched capacitors.

[0118] A switched capacitor resonator with K switches uses different combinations of switch positions to provide 2^K discrete natural frequencies of an analog resonator. For example, suppose there are capacitors (values ​​C, 2C, and 4C) connected in parallel with three switches. Then, by appropriately setting the three switches, a set of capacitance values ​​{C, 2C, 3C, 4C, ..., 7C} can be achieved. A common problem with switched capacitor resonators is that tuning frequencies are not allowed beyond the eight discrete steps.

[0119] However, using DPLP domain feedback processing 3, the poles of the switched capacitor resonator may move within a small range relative to the capacitor switching setting, but this may be sufficient to use the next switching setting in the RF resonator, making the continuous frequency variation slightly larger than the bandwidth covered by each basic switched capacitor setting.

[0120] As will be demonstrated, this results in continuous frequency tuning across a wide range and continuous variation in the DPLP feedback processing.

[0121] A digital resonator can be used as a phase shifter and slightly change the resonance frequency, but this can be sufficient to use the next switch setting in an RF resonator. An example of a block diagram of an analog resonator switching capacitor bank 232 , feedback processing 48 , and gain block 234 with four capacitors is shown in Figure 23 .

[0122] One specific embodiment of feedback processing is a digital resonator. Although digital resonators can be implemented in a variety of ways, DPLP can provide digital resonators within the outer loop 50 . In one embodiment, the DPLP may use feedback processing having digital domain B to generate a feedback signal from the superposition of state variables, thereby continuously tuning the DPLP poles in frequency. This can be extended to resonators consisting of P poles along with K sets of switching capacitors.

[0123] This principle can be further summarized. A resonator with a complex number of poles with N different switching settings is considered, which enables the attachment of reactive components to or from the multipole resonator at different and arbitrary points in the resonator. There can be 2 N switch combinations and therefore 2 N different configurations of analog resonator pole positions. In principle, the feedback processor function can be judged for each requirement of the DPLP pole position of each of the 2 N resonator configurations. However, specific resonator configurations with the smallest feedback signal amplitude can exist. This is the switch configuration selected for the desired output DPLP pole position type.

[0124] The open-loop podogram is plotted in Figure 24a , where, the frequency of the digital resonator is 5% lower than that of the radio frequency resonator. In Figure 24b , the frequencies are the same, and in Figure 24c , the digital frequency is 5% higher. In each case, the RF resonator frequency was 0.2 rad / sec. Note that the zero-phase crossover means that the DPLP center frequency will be at the medium Q-enhanced level.

[0125] A 10% change in the digital resonator will result in a DPLP center frequency change of about 4%. Thus, if there are 4 switching capacitors used for the 16 states, this is about 64% variation in the DPLP tuning frequency.

[0126] Finally, it can be noted that the amplitude decreases slightly when the digital resonator is deharmonized away from the RF resonator. This may require a small increase in G to compensate for this to maintain the precision of Q enhancement, which is adjusted by the DPLP.

[0127]

DPLP

[0128] This section considers the state-space formulation of a DPLP feedback processing circuit 30 capable of simultaneously placing multiple poles. In general, a multi-pole resonator structure is implemented as a dual-port subsystem with a single input and a single output (referred to in this invention as a Single Input Single Output (SISO) network). From the single output, the DPLP processing can make sufficient observations to form a single feedback that enhances Q or to place multiple poles at once. While a single feedback is theoretically sufficient to move multiple poles to the desired location, practical implementations of DPLP will allow simultaneous tuning of the resonator. This reduces the amplitude of the necessary feedback signal. However, the resonator frequency does not need to be precisely tuned or have high resolution. Therefore, switched capacitors can be used for tunable resonators.

[0129] Considering a general resonator with multiple input ports and multiple output ports, or a Multiple Input Multiple Output (MIMO) network, is also feasible. However, since SISO is well-suited for DPLP, adding complexity offers little benefit. Nevertheless, for the most general form of DPLP, MIMO should be considered.

[0130] Consider a DPLP with N / 2 resonators. Transforming the resonator transfer function to the Z-domain results in an Nth-order transfer function that is... The coefficient b0 is zero because there is no direct connection. It is always normalized to 1. Multiplying the numerator and denominator by z prepares the state-space notation, yielding...

[0131] Next, this can be considered as a cascade of two transfer functions, as shown in Figure 25, where block 250 corresponds to HA(z), block 252 corresponds to HB(z), input 254 corresponds to uk, transform 256 corresponds to yk, and output 258 corresponds to vk. The first system is an all-pole transform, and the second system is a molecular part.

[0132] The entire pole region is given as This leads to the difference equation State variable set system Make Therefore, the difference equation can be written as Therefore, the state space matrix A can be written as And the B matrix system The molecular transfer function is Given the difference equation as therefore The feedback is also given by the following equation. The feedback transfer function can be written as

[0133] The loop 262 for a general DPLP is now quite simple, consisting only of a filter 264 for the feedback processing 266, as shown in Figure 26. [。]

[0134] Figure 27 shows the time-domain simulated response when the normalized input oscillator is 1 rad / sec and amplitude 1 is enabled. The horizontal time axis represents the clock cycle. Note that the DPLP stabilizes after approximately 800 clock cycles.

[0135] [State Space of a Single-Pole Resonator] [DPLP]

[0136] We will now consider the state-space formula for the DPLP resonant feedback process of a single-pole resonator. This will then be extended to a multi-pole resonator.

[0137] Starting with an ideal single resonator having the following transfer function General state-space formulas Where x is the vector of state variables, u is the input, A is the system matrix, and B is the input matrix. Let z(t) be the input and y(t) be the output. The state vector is chosen as... This leads to the system matrix Please note that the chosen state variables are not unique and may result in different system matrices. However, the system pattern remains unchanged regardless of the choice of state variables. The choice of state variables allows for a simple signal flow diagram consisting of a pair of integrators, as shown in Figure 28. In Figures 28 and 29, the reference numbers represent the following: 280 represents as; 281 represents 1 / s; 282 represents z; 283 represents u; 284 represents x1; 285 represents x2; 286 represents y; 287 represents –c; 288 represents –b; and 289 represents ax2.

[0138] To simplify, the differential operator in the numerator of H(s) is separated, and u(t) is used as input. Next, the input matrix system... To ensure system controllability, it is determined to be full rank. The controllability matrix, in this case, is the system

[0139] The system is controllable, and therefore the poles can be fully moved according to feedback based on the linear superposition of two state variables. However, only the state variables can be accessed. In this simplified embodiment, Therefore, if observed Then it can be derived through linear operations. Therefore, full-state feedback can be provided, and since the resonator is controllable, the closed-loop poles can be placed at any desired location. For higher-order systems, this may not be so obvious, making it possible to observe all state variables from a single output. One way to determine whether this is feasible is to consider the observability of the system. If the state-space system is observable, then all state variables can be derived through linear operations and the superposition of the available outputs. The state-space output is represented as... In this case, observed at the output , making Observability matrix system It is full rank. In this case, the observability matrix system It has a rank of 2.

[0140] Next, a weighted vector of feedback can be formed, labeled k, and then the input is... Therefore, the state space system of the closed-loop AFF The new closed-loop poles are used as a matrix The eigenvalues ​​of k. Therefore, since the weights or control vectors of k can be determined, this will set the desired poles. That is, if the {A,B} pair is controllable, then The eigenvalues ​​can be any set.

[0141] Since the differential operator has been separated from the numerator, feedback can be added to the input, allowing us to adjust the implicit integral of the feedback by (1 / as) to obtain: And the feedback coefficient is F(s) x 1(s). If If adjusted, then It may become zero. Therefore, what remains is that the feedback from the input is proportional to x1(t).

[0142] Therefore, state-space formulas are a powerful tool for considering any form of resonator, and for making an existence query as to whether all poles of a multi-pole resonator can be individually Q-modified (enhanced or suppressed) to a desired location in the s-plane.

[0143] It should also be noted that, for the desired closed-loop poles, it may not be necessary to adjust the resonator. Adjusting k might be sufficient. As will be shown, adjust k after determining its value. This makes minimizing the value of k feasible. Alternatively, by changing... Setting the coefficients in k to zero is also feasible. This is beneficial because when some state variables in the feedback are weighted by zero, the processing of state variables can be simplified.

[0144] Using a switched fixed capacitor for frequency tuning, smooth tuning of the capacitor system in state space is not feasible. Therefore, the state variables can be roughly estimated from the output. This is directly apparent when using a state-space controller version. Therefore, feedback system:

[0145] It is best to change the order of the processing so that after processing the derivative x2 in a state space with a numerator of 1, an estimate of x2 is obtained. This estimate can be scaled and integrated to form the feedback required for the Q-enhanced resonator. Then, the frequency is adjusted so that k1 = 0. The state space inversion is shown in Figure 29. [。]

[0146] The optimal determination of the weighted vector of k is based on A and B. Note that the state variables are now based on this modified transfer function. Note that it is assumed that the numerator derivative B was changed earlier, and therefore the weighted vector k and the state variables are also changed. This can be compensated for in the DPLP feedback processor.

[0147] Figure 30 depicts a Simulink model 300 of a state-space Q-enhanced single-pole resonator with state-space feedback, demonstrating that a DSP consisting of three gain blocks, an integrator, and an adder can be used to determine the effect of active feedback in the frequency space of a single-pole RF resonator. These operations can be mapped to discrete-time DSP formulas. Figure 31 shows the simulated response of the Simulink model 300.

[0148] DSP processing can be added, as shown in Simulink model 320 in Figure 32, and the DSP processing exhibits a Q-enhancement similar to that in Figure 33, where the horizontal axis is seconds. Note that the results are slightly biased due to the delay in the integrator, represented by the discrete-time accumulator. Further note that the quantization resonator output lags behind the input in time phase. The quantization step size is 0.1, and the time resolution is 0.25.

[0149] Figure 33 shows the simulated response of Simulink model 320.

[0150] While this demonstrates that DSP processing is both efficient and easy to implement, the conversion from continuous-time to discrete-time is not the best approach. It is preferable to model the resonator in the Z-domain, leading to a more direct DSP implementation.

[0151] [Variable Delay Active Feedback Filter Tuning]

[0152] A relatively simple embodiment of the continuous-time AFF implementation of the signal processing circuit 30 in the state space is shown in Figure 34. The AFF circuit has been discussed and presented above.

[0153] The inner loop 40 filter can be bypassed, making There is a variable delay 340 with a gain of Td and a gain block 342 with a gain of G. A simple DPLP based on a single-pole resonator can be used, which can provide an arbitrarily continuously variable delay in the DSP, and can be modeled as an infinite series of poles plus a gain factor, thus allowing for arbitrary tuning.

[0154] Open-loop response system evaluated on the jω axis This makes the Nyquist resonance (NRC) curve a closed loop of unit radius. The operating point is at 1 / G on the real axis, therefore if G > 1, the operating point will be enclosed and the AFF will be unstable. For the range -1 < G < 1, there is a set of frequencies with Q-boosting, where ,and Therefore, a periodic frequency response with multiple Q-enhancing poles and multiple passbands can exist. This is illustrated in Figure 35. The delay is shown.

[0155] Next, consider DPLP, where the sampling interval is T and the delay is... The Simulink model 360 is shown in Figure 36. As mentioned earlier, the DPLP loop has a summing block for feedback. The quantizer then samples in time at sampling intervals T. The sampling is delayed by a z 2 block, which in this case is 2 sampling intervals. The DAC block is then held at another zero order.

[0156] Figure 37 illustrates a portion of the analog and digitally quantized signal. The difficulty in time-domain simulation involves a small number of transients at multiple frequencies because the source turns on at t = 0, generating several frequency components. Due to the delayed DPLP Q-amplification of multiple frequencies, the transients take a long time to dissipate.

[0157] The analysis method converts the loop components to the Z-domain and roughly estimates the quantization as an independent source of noise added at the ADC transition point.

[0158] In a continuous domain, there may be an open-loop response. This is not in On-axis estimation, just as in the s-plane, can be estimated in the z-plane. The unit circle is NRC. Therefore, the NRC system is a unit circle, and Nyquist stability analysis can be considered as before. In this case, there is no continuous-time transfer function in the loop, so the entire loop can be considered unsampled, making the closed-loop response as... It should be noted that the comparison of continuous-time closed-loop responses... If If the two are equal, then they are equal. The difference lies in that the closed-loop response uses a time-sampled signal. Therefore, the equivalent DPLP Simulink model 380 is shown in Figure 38.

[0159] The DPLP under consideration has a delay of an integer number of sampling intervals, which is preferably variable. One possibility is to implement the delay using passband responses of wo = 0.2 (normalized), D = 0.1, Td = 0.1, and T = 1.0. Bode plots for continuous and discrete time are shown in Figure 39. When the zero-order hold (ZOH) approximation is applied to the sampling operation, the discrete time is calculated from the continuous time based on the invariance of the step-order response. The response is indistinguishable in terms of magnitude and small phase differences.

[0160] The Simulink simulation model 400 of the discrete filter placed in the loop is shown in Figure 40. The G-coefficient is 0.9, therefore the Q-enhancement coefficient is approximately 10, indicating that the input sinusoidal frequency coefficient is 0.2 rad / sec and the amplitude coefficient is 1. The response model is shown in Figure 41, where the horizontal axis is represented by the DSP clock cycle, indicating the start-up transient stability and corresponding to the rise time constant commensurate with the implemented pole Q. There is a slight loss due to the ZOH of the frequency response "sin(x) / x".

[0161] Since the transfer function of Hd(z) is given as The difference equation can be determined directly. This indicates that the implementation in the DSP involves 5 coefficient multiplications and 5 additions.

[0162] [Single Pole()] [P = 1] [)Variable Delay Discrete Time] [DPLP]

[0163] In this embodiment, a single continuous-time pole (P = 1) resonator or a first-order resonator is considered as the Simulink model 420 depicted in Figure 42, starting from a simple gain block.

[0164] The open-loop Nyquist plot is based on converting the resonator into a discrete-time sampling transfer function, and then cascading it with the discrete-time transfer function for calculation. The resulting NRC curve is shown in Figure 43.

[0165] The Nyquist resonator curve (NRC) of this double-pole DPLP resonator looks similar to that of the double-pole frequency space resonator NRC because there are actually two poles in this DPLP state space resonator: one as a continuous-time resonator and the other as a digital-domain resonator.

[0166] Clearly, a continuous-time resonator can be tuned, and then a DSP resonator / phase shifter can be determined to provide the desired Q-enhanced response.

[0167] [double poles()] [P = 2] [)Variable Delay Discrete Time] [DPLP]

[0168] A second resonator can be added to form a second-order resonator. Simulink model 440 is shown in Figure 44.

[0169] As described above, the open-loop Nyquist plot is first calculated by converting the continuous-time resonator into a discrete-time sampling transfer function, and then cascading it with the discrete-time transfer function. The resulting NRC for P = 2DPLP is shown in Figure 45.

[0170] [Fixed-frequency resonator frequency tuning]

[0171] RF resonators can be integrated with or implemented using distributed off-chip components. Consider fixed-frequency resonators for certain applications, perhaps designated as SAW or BAW devices. Typically, passive fixed-frequency resonators can effectively perform this filtering task without power requirements and can be designed to withstand large interference signals, despite being at a fixed center frequency.

[0172] Fixed-frequency resonators typically consist of a set of fixed poles: these poles can be Q-enhanced or Q-suppressed, and frequency-shifted as needed according to the principles described above. SAW or BAW resonators share the common characteristic of spectral regrowth, which can be mitigated according to the principles outlined above.

[0173] Furthermore, SAW / BAW may have several passband poles with moderate Q values. However, one problem with SAW is the difficulty in controlling the passband ripple and slope using frequency. If implemented with RF circuitry, the feedback processing required for multi-pole placement becomes inefficient and unreliable. However, implementing such processing in the digital domain after signal digitization is almost negligible. Therefore, the loop should consist of two domains: an RF domain for the resonator and a digital domain for feedback processing.

[0174] By using DPLP feedback, multiple poles of the SAW can be moved to more desired positions to provide a higher Q passband response with very small passband variation, and spectral regrowth can also be suppressed in this process. The feedback signal in the DPLP loop can also be larger than the input signal.

[0175] With the development of ultra-high-speed digital processing, ADCs, and DACs, such mixed-signal loops are practically feasible. A potential drawback is that transitioning from the RF domain state space A to the state space domain B involves frequency downconversion, sampling, and ADC quantization. These procedures can have relatively high noise figures (NF) and are susceptible to out-of-band noise.

[0176] Before the domain A to domain B loop conversion component, the resonator removes a significant amount of out-of-band noise and interference as it propagates through the loop. The domain B to domain A conversion involves upsampling and a DAC that can generate significant out-of-band frequency spikes and quantization noise. Most of this is removed by the resonator before looping back to the A and B domain conversion.

[0177] [use] [DPLP] [Generates a third-order Chebyshev or Butterworth response]

[0178] As a final example, consider a practical implementation of the signal processing circuit 30, as shown in Figure 46. Three resonators 462 are set to fixed capacitors with frequencies closest to the center frequency of the target third-order Q-boost filter. In Figure 46, the resonator outputs are connected to block 464, representing all the ADCs, DSPs, and DACs.

[0179] The DPLP pole placement algorithm can then be used to determine the necessary processing to obtain the pole placement that will result in the target passband response. In the Chebyshev case, the objective is a flat passband response over the desired -1 dB bandwidth.

[0180] The resulting response is shown in Figure 47, where the phase is on the left vertical axis and the magnitude is on the right vertical axis.

[0181] As another visualization of this Chebyshev bandpass filter example using the DPLP algorithm, consider Figure 48. The blue curves represent the responses of the three resonators in Figure 46, without any DPLP feedback. For this Chebyshev example, the normalized resonant frequency of each resonator is set to 1 rad / sec, which is the center of the desired passband response. Then, the DPLP feedback shifts the three poles of the resonators in the s-plane to obtain the desired passband response.

[0182] The response shown in Figure 47 is copied to Figure 48, and the amplitude is normalized for direct comparison of the two results.

[0183] The same method is used to achieve Butterworth band response.

[0184] [Determining Positive Feedback Processing Based on the Nyquist Stability Criterion]

[0185] As the number of resonators 462 increases, directly using the transfer function at the poles and zeros may present more numerical problems than benefits. Instead, the Nyquist resonator curve (NRC) can be used. The NRC includes all frequency-dependent components of the open-loop response. By deforming the NRC around the operating point to graphically represent the open-loop response, the desired characteristics of the closed-loop response can be achieved more easily.

[0186] make The transfer function of the resonator in the z-domain. This can be determined directly from the frequency measurement of the resonator, or it can be transformed into a discrete-time domain pole-zero transfer function model of the resonator. This is DSP processing, which is a precise representation implemented using exceptions of signal digitization. Then, from... The open-loop response forms the NRC, which is plotted in the complex z-plane.

[0187] The NRC (Neural Resonance Coefficient) plotted for a single-pole equivalent open-loop circuit is shown in Figure 49. A portion of the NRC is shown for the region near the resonant frequency. The operating point can be to the right of the NSC to maintain stability and is on the real axis. If the operating point is to the left of the NRC, the DPLP is unstable.

[0188] The frequency response is approximately given by the inverse of the phasor of the frequency point connected to the NRC. As can be observed here, the phasor length increases as the frequency moves away from the closed-loop resonant point. The closed-loop resonant point is defined as the intersection of the NRC and the real axis.

[0189] Optimization of the target system This allows the NRC to have the desired shape. An example of this is shown in Figure 50, where it has been determined... This results in the phasor in Figure 49 having a nearly constant length over the desired closed-loop bandwidth of the DPLP.

[0190] Figure 51 shows the simulated NRC of a two-pole resonator with optimized pole placement based on the desired closed-loop resonator pole positions. The operating point is located at a value of 1 on the real axis. The blue curve represents the NRC of the two-pole resonator. The red curve represents... The open-loop transfer function's NRC. Note the concavity of the open-loop NRC around the resonant frequency, which results in a flat passband response.

[0191] [Frequency shifting and signal digitization] [DPLP] [Phase Combination] []

[0192] The DPLP transformation from domain A to domain B can involve frequency shifting and signal digitization, where the DSP is used for feedback processing 48. This serves as an example of the parallel processing paths shown in Figures 52a and 52b. Figure 52a illustrates that feedback processing 48 can involve frequency shifting 522, causing the actual feedback processing 524 to occur at a different frequency. This can lead to simpler and more practical implementations of feedback processing for specific applications. For example, actual feedback processing 524 could be fundamental frequency analog processing.

[0193] Figure 52b illustrates the domain transformation, which includes frequency shift 522 and discrete-time sampling and quantization of the input signal. Feedback processing can then be performed in the state space of the DSP. A basic DPLP with frequency shift can be incorporated into the SDR, as discussed below.

[0194] [, Z , ] [, In the domain , ] [, DPLP , ] [, Implementation Plan , ]

[0195] [exist] [Z] [Modeling a single pole in the domain] [DPLP] [Resonator Response]

[0196] The first step is to establish a continuous-time model of the resonator, and then, as discussed above, convert it into a discrete-time model and model it, as shown in Figure 42. This indicates that the resulting Z-transform model is: Assume the input is based on the uk system and divide the model into a denominator and a numerator. Let yk be the output of the first transition function, and define the state variables as follows: Then, establish the state spaces of A and B, where vk is the output.

[0197] Next determine the Q-enhanced pole and determine the k vector. The feedback is given by the following formula The output is observable as vk and its relationship to the state variable is: which is expressed in terms of state variables as: From it The advantage of the controller state space model is that the state variables are all directly delayed versions. Therefore a simple delay tap is implemented. This is shown in the Simulink model 530 depicted in FIG. Since this is only a single pole, only one delay is required. Note that the required operations are four times multiplication and two times summation.

[0198] [in] [Z] [Modeled Bipolar Point Resonator in the Domain]

DPLP

[0199] Next consider the DPLP with two resonators. The required DSP processing can be determined by following the same steps as described above. The first step is a continuous-time model of the resonator, which is subsequently converted to a discrete-time model. This bipolar point resonator has been discussed previously and has been modeled as previously shown in Fig. 44 [. ]

[0200] This can indicate that this leads to the z-transform model as: The coefficient a 1 is always 1, which can be eliminated to rewrite the transfer function as Now multiply by z -3 to get it Assuming uk is input, the model is then divided into the denominator part and the numerator part, obtained Make yk the output of the first transfer function and define the state variable as The state space of A and B is then created, where vk is the output. Next determine the Q-enhanced pole and determine the k vector. Therefore, this can indicate that the feedback is given by the following The output is observable as vk and its relationship to the state variable is: which is expressed as in terms of state variables From it

[0201] The advantage of the controller state space model is that the state variables are all directly delayed versions. Therefore a simple delay tap is implemented. This is shown in the Simulink model 540 depicted in FIG. Since this is only a single pole, only one delay is required and the DSP becomes a simple filter structure that is easy to implement. Note that the required operations are four times multiplication and two times summation.

[0202] Figure 55 demonstrates the analog output of this bipolar DPLP resonator in which both poles are placed simultaneously. The horizontal axis is represented by the DSP clock cycle and indicates that the startup transient is stable and corresponds to a rising time constant commensurate with the implemented pole Q.

[0203] [Dual-loop expansion to bandpass] [Δ∑]

[0204] Referring to Fig. 56 , the design principles discussed earlier can be extended to other architectures involving downfrequency conversion, such as bandpass Δ∑ circuits. Δ∑ (Delta Sigma, DS) is a digital signal processing technology incorporated into the ADC architecture to reduce quantization noise in general-purpose receivers. Bandpass Delta Sigma (BDS) is an extension of DS and can be used to suppress the inherent noise of frequency reduction conversion procedures in addition to quantifying noise. Chip-integrated versions of BDS (such as BDS operated higher than 1 GHz) may be difficult to implement because resonators with sufficiently high Q values ​​are required, which Q values ​​are difficult to produce using conventional integrated circuits. Using the variable filter technology of the present invention, high-Q, stable resonators (such as those with Q over 1,000) can be integrated onto the wafer.

[0205] In circuits involving downconversion, the downconversion process can be a significant source of noise.

[0206] [Tunable Notch Filter]

[0207] Signal processing circuit 30 can provide a notch filter, but input 34 needs to be applied at different points in the loop. This is illustrated in Figure 57 and includes a phase shifter 570 in the outer loop 50. Please note that the transfer function from input 32 g(t) to output port 34 is the same as the transfer function for the downstream noise previously considered. The transfer function will have a notch at the dominant pole location of the Q-enhanced bandpass filter 42 with filter block 572 and gain block 574. The negative feedback gain 576 will determine the depth of the notch. Please note that this is an RF version.

[0208] Another version features a fundamental frequency processing variant with quadrature sampling, as shown in Figure 58. Downstream components may include a quadrature downconversion and sampling ADC 582, a DSP 52, and a quadrature DAC and upconversion 584. The downconversion and upconversion are optional.

[0209] Notch filters can be used to eliminate narrowband interference, and can also be used to form the zeros of composite filters that use poles and zeros (such as RF elliptic bandpass filters).

[0210] [Numerical Example of a Notch Filter Using a Bandpass Filter from the Catalog]

[0211] To give a numerical example, first consider a variable bandpass for the catalog, whose response is shown in Figure 59. The NRC under this setting is shown in Figure 60, where the optimal axis for the inner loop Q enhancement is represented by line 602, and the optimal axis for the outer loop bandpass Δ∑ is represented by line 604.

[0212] Note that when s = 0, the optimal bandpass Δ∑ axis coincides with the trough of the NRC, allowing for a larger feedback gain (to separate the poles from the zeros). However, this angle is difficult to determine, so practical implementations often place the Δ∑ axis at 180 degrees to the peak. That is, the peak for further Q enhancement is easily determined, but the bandpass Δ∑ axis is difficult to determine. In such cases, the maximum Δ∑ negative outer loop feedback is smaller.

[0213] Given an NRC, there exist points on the outer boundary of the trajectory with the maximum modulus relative to the origin and points with the minimum modulus relative to the origin. For an NRC with Q-enhanced SAW, these points are roughly located on opposite sides. The maximum value applies to Q-enhanced positive inner loop feedback, and the minimum value applies to Q-suppression in negative outer loop feedback.

[0214] Next, a moderate Q-boost is applied with a coefficient Qen = 10. The closed-loop NRC is shown in Figure 61. Note that the negative gain of the outer loop may be larger.

[0215] Figure 62 illustrates the transfer function of quantization noise (QNTF), where the tunable bandpass Δ∑ feedback gain is 0 (i.e., no action is taken), and the Q-boosting loop is a flat line at 10.0 dB. The peak Q-boosting signal transfer function (STF) exhibits the expected positive feedback of signal boosting in the inner loop.

[0216] Figure 63 illustrates the effect of tunable bandpass Δ∑ modulation, where the drop in the quantization noise transfer function is flat in Figure 62. Here, the outer loop negative feedback can be adjusted to result in a loss of approximately 19 dB in QNTF. The STF signal bandwidth has widened as the negative feedback removes some of the positive feedback gain from the inner loop.

[0217] By increasing the signal enhancement gain of this inner loop, the STF bandwidth can be recovered. However, the zeros are pushed towards the jω axis, resulting in a narrower notch. To widen the notch bandwidth, a second-order bandpass Δ∑ providing two poles and two zeros can be implemented. By implementing a higher-order bandpass Δ∑, the notch bandwidth can be further widened.

[0218] This loop can be extended to have two poles, allowing for a Q-enhanced pole in the upstream receiver through two signal boosting. As mentioned above, the negative feedback loop can also have two loops.

[0219] [Fixed-frequency bandpass filter]

[0220] As described above, the bandpass filter 42 of the inner loop 40 (or resonator A(s) or block 92 of the upstream processing 91 shown in Figure 9) can have many different variations. In FEMs, many RF / microwave receivers have fixed filters with high frequency selectivity. The bandpass filter 42 can be a surface acoustic wave (SAW) filter or a bulk acoustic wave (BAW) filter, a microstrip filter, a cavity filter, etc. The filter can be narrowband and non-tunable. In mobile phones, there can be a set of these filters that can be individually selected to demodulate a given signal band.

[0221] [Acoustic Filter]

[0222] We will now discuss SAW / BAW devices, especially SAWs that are similar to BAWs.

[0223] For a dual-loop configuration, this acoustic filter network is part of a bandpass filter 42 and may include a SAW filter 642, a gain block 644, and a phase shifter 646. A positive reinforcement feedback loop 45 may be provided around this acoustic filter network, which will perform two tasks: 1. Subband within a narrow bandwidth of a Q-enhanced SAW (or other) filter. 2. Change the shape of the closed-loop bandpass filter 42 of the inner loop 40 (add a boosted feedback path to the upstream receiver) so that the negative feedback of the outer loop 50 can frequency-shape the noise injected by the downstream receiver.

[0224] To achieve deeper noise transfer function filtering in the downstream receiver, higher negative feedback gain is required. Upstream receiver stability can be ensured by shaping the NRC of the closed loop.

[0225] Acoustic resonators such as SAWs can serve as bandpass filters 42 to provide high-frequency selectivity. The NRC of a SAW is typically unsuitable for noise shaping in the outer loop 50 due to its numerous poles. However, the SAW response can be Q-enhanced via the inner loop 40, resulting in a sufficiently large change in NRC to allow for arbitrary gain and negative feedback suppression at arbitrary levels. Figure 64 shows a block diagram of an implementation of a SAW filter as a resonator in the upstream receiver, which includes down-conversion low-pass filters (LPFs), a quadrature ADC 648, a complex scaling factor 650 corresponding to A(z), a DAC 56, up-conversion 652, negative feedback gain 576, sample storage 654, and post-processing 656.

[0226] SAW filter 642 can be any bandwidth SAW filter, where the passband includes the passband of the desired signal. Referring to Figure 65, the signal processing circuit can also have a set of SAW filters 642 that are switched in and out of the signal path of bandpass filter 42 via switch 658, as shown in Figure 65. It is important to note that the negative gain of outer loop 50 can be complex, while the signal enhancement gain of inner loop 40 is real.

[0227] In quadrature sampling, signal phasors with real and imaginary components are captured. This is then multiplied by a complex number having both real and imaginary components. The angle and magnitude of the resulting phasor are altered, which is treated here as complex scaling. The resulting phasor is then converted back to radio frequency using a quadrature DAC 56 and a frequency upconversion converter 652.

[0228] The system in Figure 64 can be modified into a second-order system with two reinforced SAW resonators and one or two negative feedback loops. The movement of the poles in the bandpass Δ∑ is illustrated in Figure 66. The bandpass poles are indicated by asterisks and also form the zeros of the QNTF (downstream quantization noise to output transfer function). This zero cannot be moved by feedback. The QNTF pole 660 starts at the same position as the zero, thus canceling the effect. However, through negative feedback in the outer loop, the pole can be moved to the left, separating it from the zero. The effect is that the zero of the QNTF now reduces the response in the middle of the passband. As also observed, the poles must have high Q before the feedback loop is formed. This requirement for high Q poles limits the application of Δ∑ processing. However, by using an upstream signal loop, Q can be increased to make the zeros of the QNTF relevant.

[0229] The concept of tunable bandpass ∑Δ will be described in detail below.

[0230] [Table of contents] [SAW] [Filter Enhancement Example]

[0231] For example, consider the SAW from Taiwan Semiconductor Manufacturing Company (TSMC). Figure 67 shows the frequency response of the TSMC SAW, illustrating the passband from approximately 1.71 to 1.77 GHz. Note that the passband is flat, while the edges are steep, indicating multiple poles within the passband.

[0232] Figure 68 shows the Nyquist resonance (NRC) curves of the SAW series. As mentioned earlier, NRC can be Q-enhanced, but cannot be directly used for negative feedback because the modulus of the outer ring of the NRC is too large. This limits the amount of negative feedback that can be applied.

[0233] Next, consider signal enhancement applied to the SAW filter in the positive feedback inner loop at the maximum modulus frequency. The inner loop gain is denoted by G and is a real number. This corresponds to the loop gain when all other components in the loop have unity gain at the frequency corresponding to the maximum modulus of the open-loop NRC. In Figures 69a, 69b, and 69c, G increases from 0.5 to 0.7 to 0.9, respectively, indicating that the NRC becomes more rounded and the origin shifts closer to one side of the outer ring of the NRC.

[0234] [, SAW , ] [, Specific frequency selection and bandwidth adjustment , ]

[0235] [Adjusting the inner ring road of the dual-ring road architecture]

[0236] For a specific frequency within the general passband of a SAW, the NRC can be adjusted to be more circular, and the origin can be moved closer to one side of the outer ring of the NRC. In Figure 70, for zero phase error (or a multiple of 360-degree phase shift) at 1.75 GHz, the target frequency of 1.75 GHz is selected by adjusting the inner loop phase. [。] Essentially, the only change is that the NRC rotates with the phase rotation, so that this phase rotation is taken into account when negative feedback is applied to the outer loop. However, note that the shape of the Q-enhanced SAW filter converges to this circle, where the origin s = 0 moves toward the outer ring of the NRC. This is expected because Q-enhancing results in an approximate equivalent of a single dominant pole with this general NRC shape.

[0237] The frequency curve of the Q-enhanced SAW is shown in Figure 71, indicating that the narrow passband appears at 1.75 GHz.

[0238] [Adjust the outer ring road of the dual-ring road architecture]

[0239] Next, the negative feedback outer loop is added to (and specifically to) the signal transfer function (STF) from the input to the output of the outer loop, and the noise transfer function (NTF) from the output of the Q-enhanced SAW in the inner loop to the output of the outer loop.

[0240] Figure 72 shows the results with an outer loop featuring complex negative feedback Go = 1j. The system shown is a superposition of STF and NTF. Note that complex gain feedback is required to achieve a 90-degree phase shift that depends on the NRC rotation.

[0241] In Figure 73, the negative feedback gain is increased to Go = 2j. Note that the noise suppression coefficient is now approximately 9 dB, but at the cost of a wider signal passband.

[0242] In Figure 74, the complex negative feedback gain is increased to Go = 4j. Note that the noise suppression is now approximately 14 dB, but the passband is increasing.

[0243] To narrow the signal passband, the gain of the internal positive feedback loop can now be increased. In this case, it is increased to G = 0.93. The NRC of this further Q-enhanced SAW is shown in Figure 75.

[0244] Figure 76 shows the results of the signal transfer function (STF) and noise transfer function (NTF), demonstrating how the STF narrows for the same 14 dB noise suppression.

[0245] The key point is that the inner and outer loops can be adjusted in conjunction and collaboratively to achieve the desired noise reduction and the desired narrow passband of STF.

[0246] [, Dual-loop mixed-signal processing for software-defined radio ( , ] [, SDR , ] [, Application of ) , ]

[0247] [SDR] [Processing Overview: Receive Mode]

[0248] In this paper, the desired signal is referred to as S, and the interference and noise are referred to as N. As shown in Figure 77, these are summed at the receiver input 772. Next, there is a sub-circuit block 774 (block A) that digitizes the combined signal, so that the DSP 52 can be used to extract information at the output 776. Assume that S occupies a passband of finite width centered at fc. N has a large interference signal, but this interference signal is outside the passband of S, and the additive noise components of N are uniform across the spectrum.

[0249] One problem is that digitizer block A has 1. Finite sampling frequency 2. It will saturate under large signal input conditions. 3. Introduce quantization noise

[0250] Therefore, some information in S is destroyed when it is transformed into digitized A.

[0251] In more abstract terms, the input to digitizer A is an infinite number of continuous signals in different states. The output is a finite number of discrete states. When N is large, most of these states are used to map the variability of N, and only a few of A's effective output states are used to map S. Therefore, most of the information in S is lost. To give a concrete example, consider digitizer A as an ADC that samples a signal with Nq quantization levels. This mapping is a mapping from the input continuous signal S + N to the output discrete categories. Mapping an infinite number of continuous states to a finite Nq categories represents information loss. To see this, if N >> S, the entropy or uncertainty of the mapping from S to the output categories is large. Therefore, the mutual information between the input S and the ADC output is low. Here, mutual information refers to a 1:1 correspondence between the transmitter and receiver at the bit level, meaning that the transmitter and receiver mutually agree that the transmitted bits are the same as the received bits.

[0252] In the digitization process, a region of continuous signal space is mapped to an irreversible quantized output. Once this region is folded into an output category, it cannot be recovered, and mutual information is lost. This loss of mutual information can be quantized.

[0253] To illustrate this, consider the differences in the receivers in Figures 78a and 78b, where the inputs include the desired signal 782 (S) and in-band interference 784 (N), which are shown as inputs to a summing block 780. This in-band interference can be intentional (like man-made interference) or unintentional noise from any general RF source with in-band energy. In Figure 78a, S + N is digitized, followed by a digital BPF 786, which removes any N outside the bandwidth of S. In Figure 78b, S + N is first filtered by a bandpass filter (BPF) 42 to remove N outside the bandwidth of S, and then sampled by A. In both cases, the quantization of S, N, and A is the same.

[0254] In these two circuits, A is responsible for information loss due to quantization noise. After quantization of A, a DSP may be constructed where further loss of mutual information is negligible.

[0255] As shown in Figure 78b, the quantity N is minimized by BPF 42, resulting in low loss of mutual information. For the top receiver, N is large, leading to significant irreversible loss of mutual information. Therefore, the bottom receiver preserves mutual information better than the top receiver.

[0256] The argument is that the mapping process from continuous-valued signals to discrete-valued signals is a key part of the irreversible loss of mutual information. Typically, a quantizer can be considered an ADC with Nq levels. However, it can be much more: a. It can be orthogonal sampling. b. It can be sampled after frequency conversion. c. It can become complex and difficult to analyze due to the composition of a set of samples.

[0257] However, the concept is straightforward: acquire signals with continuous time and continuous amplitude, and map them to a finite number of discrete categories in the digitization process.

[0258] The aim is to apply such abstract concepts to signal processing circuits such as the signal processing circuit 30 shown in Figure 3. The purpose of upstream processing of the ADC can be to "protect the ADC." This means conditioning the continuous-time signal into the ADC so that the mutual information loss caused by the ADC mapping operation is minimized. This is a useful way of thinking for the concept of signal processing circuit 30 because there is no need to consider the DSP connected after the ADC. In principle, the relative performance of signal processing circuit 30 compared to other solutions can be quantified by how much mutual information loss occurs in the ADC.

[0259] The optimal effect achievable is continuous-time matching, providing a filter output symbol that perfectly corresponds to the symbol of the input signal. For example, consider uncoded BPSK using a single-bit ADC. In such cases, the mutual information loss of the ADC can be zero (depending on the probability density functions (PDFs) of S and N). Matched filters provide signal conditioning, or "ADC protection," so that mutual information is not lost in the ADC; this is suitable for ADCs with only a single bit.

[0260] An ADC can be fixed using a known sampling rate and a fixed number of quantization levels. A BPF resonator can have a fixed, moderate Q, with a bandwidth wider than that of S.

[0261] Considering that the signal from BPF 42 can cycle back to the starting point several times, as shown in Figures 3 and 8, the goal is to enhance S and further reduce the out-of-band components of N.

[0262] The effect is to amplify S with positive feedback, causing its amplitude to grow at the output of the BPF, while N only grows within its frequency band. By controlling the amplitude gain of the feedback signal, the effective number of times S passes through the BPF can be effectively controlled. Therefore, in quantizer A, S is added to S passing through the BPF twice, S passing through the BPF three times, and so on, until the effective number of cycles is reached. This is roughly equivalent to the Q enhancement of the feedback resonator BPF, denoted as Qe. Note that N is limited to approximately one pass through the BPF because the contribution of subsequent passes is much smaller. However, the spectral portion of N near fc within the BPF will become enhanced just like S.

[0263] The benefit is that the quantization level of A can be adjusted to best accommodate a larger S. Through this enhancement, S grows relative to N, making quantization S-dominated. Note that this limitation can arise as Qe increases to the point that some of S is lost at the outer band edges of S, resulting in a narrower passband. For isolated symbols of S, having arbitrarily high Qe is practically not a loss, meaning that very narrow bandwidths can be smaller than the bandwidth of S. However, this no longer holds when considering continuous symbol streams, as symbols will begin to interfere with each other. This causes adjacent symbols to mix together, leading to information loss.

[0264] To avoid such losses, multiple BPF resonators can be used.

[0265] One issue is that recirculating BPF requires gain, and gain is accompanied by noise. Furthermore, the loss through BPF represents the Noise Factor (NF) caused by thermal noise affecting components in the loop. This type of in-band thermal noise is amplified by enhancement in the same way as S. Therefore, NF can be minimized to avoid eroding the mutual information of the filtered version of S.

[0266] Since nonlinearity does not directly cause information loss, it is of concern. Therefore, gain compression can be performed, which is simply a new mapping from S to the output. However, compression itself does not cause state merging. However, if compressing the signal causes the quantizer to mix states, then information loss occurs. Furthermore, different frequency components of the signal can be considered. Since these components are mixed due to nonlinearity, this is equivalent to state merging again leading to information loss.

[0267] One limitation is that S also observes that the feedback path suppresses some gain, thus effectively widening the bandwidth of the BPF. However, this is a balance between Qe and the positive feedback gain G. This can be quantified by evaluating the transfer function.

[0268] This can be extended to having multiple resonators in the loop. Consider two BPFs in series. If the BPFs are at the same center frequency, one frequency will be slightly emphasized over the others. After Q e times through the loop, this frequency component will then be strongly emphasized, and the overall Q-enhanced response will exhibit a single pole.

[0269] If the BPF is the same, then this is roughly equivalent to 2, 4, 6, ... Qe·2 times through a BPF, instead of 1, 2, ... Qe times. It is roughly equivalent to having only one BPF but with twice the Q.

[0270] If the BPF is tuned differently, there won't be a significant difference because it's assumed that the BPF bandwidth is wider than the Q-boost bandwidth. Therefore, there will still be one frequency with a slightly higher gain than the others.

[0271] If the bipolar response is desired, two loops can be used, one loop surrounding each BPF 42, as shown in Figure 79. In this invention, the two signal enhancement loops are referred to as second-order and can be inner loop 40. Digital data 792 is acquired from the ADC 54 and DSP 52. Now assume that such a second-order filter with first and second BPF 42 makes the feedback loop favorable at two different frequencies. It can now be seen that the Q-enhanced response will result in a double-pole response. These poles can be advantageously placed as described above.

[0272] Now, assume the two loops are identical. The S-series loops pass through the Q-eBPF sequentially (approximately) and then through the Q-eBPF in the second loop. Again, this is roughly equivalent to a single BPF with twice the Q. By this approximate equivalence, it can also be seen how the overall response can be a bipole response if the BPF loops are tuned in a slightly different manner.

[0273] Now consider the negative feedback of the error signal shown in Figure 80, where the negative feedback 576 in feedback loop 55 with G < 0 represents the negative feedback opposite to the signal enhancement feedback.

[0274] When the negative feedback passes through two BPF 42s, this effectively provides a double integral of the error signal. For better control of the negative feedback, negative feedback 576 can be input at the two summing blocks 780, as shown in Figure 81.

[0275] This architecture can be summarized as N BPF 42s with positive feedback and N negative feedback 576s, as shown in Figure 82.

[0276] For higher-order loops, the feedback analogy still applies, because it is clear that the N passband poles can be arbitrarily placed and tuned. The concept of quantization error negative feedback can be viewed as using the approximate equivalent of N integrals to cancel out the injected quantization error. Therefore, the more BPF poles that are transformed into zero, the more control can be exercised over the location of quantization noise at zero frequency.

[0277] [Overview of Receiver RF Signal Processing]

[0278] Figure 3 was redrawn to focus on the different configurations of the dual-loop architecture, as shown in Figure 83.

[0279] Here, the input is the sum of the desired signals 782, represented by S, assumed to be within the passband of the bandpass filter. The interference and noise signals 784, represented by N, are assumed to be distributed over a wider frequency range than S. These signals propagate through the bandpass filter (BPF) 42. The output of the BPF 42 is digitized in the ADC 54, which may contribute to the quantization of noise, and then the DSP 52 extracts information from the desired signals 782.

[0280] The sole purpose of the receiver is to process the combination of S and N such that information 832 represented by I can be retrieved. This information I relates to the unknown about the S of concern. For example, in a communication signal sending a sequence of symbols, the symbol carrier frequency fc, the symbol shape (and therefore its frequency bandwidth) are known. Symbol amplitudes corresponding to different bit values ​​are also known. The bit value of the symbol carrying this information is unknown. Thus, all processing of the receiver is concerned with retrieving I from the receiver input sample of N+S, in which case, I is the bit value.

[0281] Given {S + N}, the theoretical mutual information of the existence of IM is less than I . That is, in the absence of N , I is the retrievable information of S . However, due to the presence of N, there is also remaining uncertainty in the information retrieved from S, which is IM. Note that the IM is processed independently of the receiver and that the actual information (represented by the IR) retrieved by the receiver from S is less than the IM. The best receiver is the one where IR= IM. The inefficiency of the receiver is the loss of information, such that will form the FOM of the receiver, as . It is necessary to consider damage to the receiver assembly, which contributes to FOM deterioration. This results in loss reduction in the receiver, thereby providing a tangible specification to the receiver assembly. However, the receiver architecture and processing should be evaluated based on the deterioration of the FOM rather than individual specifications such as linearity and noise indices.

[0282] The performance or advantages of the signal processing circuit 30 architecture of FIG.83 can only be considered as a whole, with S+N at its inputs and IR at its outputs. Briefly, the concept of signal processing circuitry 30 lies in the positive feedback loop (inner loop 40) enhancing S with respect to the out-of-band component of N such that the ADC 54 digitizes the filtered signal, thereby minimizing the information loss of the ADC 54 . A portion of the uncertainty of the ADC 54 (due to quantized noise) can be interrelated with the passage from one digitized sample of the ADC 54 to the next, and is therefore reduced by recourse to feeding it back to the front end of the receiver via a negative feedback loop (outer loop 50). In this way, some of the uncertainty of the ADC can be alleviated, thereby partially recovering the information that would have been lost.

[0283] Note that to reliably implement positive and negative feedback loops, loop gain and frequency response must be designed and managed. Therefore, positive and negative feedback are concepts related to signal enhancement or amplification and loop noise suppression, respectively. The output of the ADC 54 is also sent to a processing block that acquires signal information, such as a DSP 52. Furthermore, the BPF 42 can be a resonator, a multi-pole filter, or a filter with poles and zeros, and is therefore versatile. The only real requirement is that the desired signal of S has no null values ​​in its passband and that there are some amplitude and phase variations with frequency. For example, it could be a delay line where only the phase varies with frequency, without amplitude variations.

[0284] In Figure 84, there is an adder 780, where signals entering the input port are superimposed at the output port. This is an idealized combination function that can be approximated in a physical RF circuit. Therefore, it should be understood as a concept of signal superposition. The physical adder 780 will have some signal loss to consider, as well as some signal reflection at the adder port. Figure 84 shows the loop tap 842 after BPF 42, where the feedback signal is tapped. This is an idealized splitter where the input signal and the two output signals have the same signal amplitude. In a practical splitter, the amplitude of the output signal will be lower than that of the input signal, resulting in power savings. Furthermore, the implemented splitter will have additional losses associated with the signal port and some signal reflection.

[0285] The dual-loop concept can be summarized as two types of receiver spontaneous noise that affect FOM degradation. These two types will be represented here as upstream and downstream spontaneous noise. The noise generated upstream of the tap point of the positive feedback loop is upstream noise 844 (Nu). The noise generated downstream of the tap point of the positive feedback loop is downstream noise 846 (Nd). The positive feedback loop can reduce Nu noise outside the bandpass of S. Nd noise within the bandwidth of S can be suppressed based on the negative feedback loop. This is illustrated in Figure 85.

[0286] This can be further generalized as follows: BPF 42 can be any filter component before or upstream of loop tap 842. Therefore, it can be assumed that the upstream receiver contains BPF 42. Similarly, the positive feedback loop can be appropriately responded to as long as the upstream receiver has some phase variation with frequency. The upstream noise is N + Nu, and Nu can be absorbed into N, which will be assumed to propagate forward. The downstream component 850 can be the remaining receiver component consisting of further filtering, an ADC, frequency shifting, etc. ND is the equivalent noise source, which is the superposition of all these downstream noise sources 846. This is illustrated in Figure 85. Note that a DAC may need to be included in the negative feedback loop to convert the digitized feedback signal back to an analog signal. The DAC is general and may include a frequency shifter.

[0287] The signal processing circuit 30 may have a general architecture, having an upstream receiver section and a downstream receiver section separated by a tap 842. A signal enhancement positive feedback path 45 surrounds the upstream section, and a negative feedback path 55 surrounds both the upstream and downstream sections, wherein the downstream tap 852 is located at the output of the downstream component 850.

[0288] To further summarize, the DSP processing block 52 that operates on the digitized signal can have two general-purpose outputs: one output optimized for the negative feedback path 55, and the other output resulting in the acquisition of information from the signal S. Therefore, an equivalent downstream tap 852 can be located within the DSP processing block.

[0289] However, the negative feedback loop operates to suppress noise generated in the downstream receiver. The subsequent DSP, utilizing noise suppression, must also obtain the feedback signal through the downstream tap 852.

[0290] However, there may be additional processing between the downstream tap 852 and the DAC, which is not necessarily shared with the processing used to acquire information. Therefore, the DSP processing is divided into two parts. This could involve two separate DSP elements. Both functions can be performed in a single physical DSP, but the logic will perform two different functions.

[0291] The final summary implements the upstream portion of the signal processing circuit 30, which can be subdivided into multiple tap points 842 and summing blocks 780 at tap points 842, where portions of the positive and negative feedback loops can be fed back to the input signal loop. This is illustrated in Figure 86 with two positive feedback paths 45 around the bandpass filter 42 as an example. The bandpass filter 42 can be a signal network with at least a phase that varies with frequency. Note that in addition to the equivalent noise from the upstream receiver, N is the noise to the receiver input. The two paths of the negative feedback path 55 can have different gains.

[0292] Mixed-signal processing may rely on positive and feedback loops, where the BPF shares a common branch between the two loops: 1. Multiple positive feedback loops are used to progressively increase S as the feedback is strengthened. 2. The purpose of the negative feedback loop is to suppress spontaneous noise originating from the downstream receiver within the S-bandwidth.

[0293] The essence of this invention is a device with two nested hybrid signal processing loops and its method of use. By balancing these two loops, the desired signal information can be optimally preserved.

[0294] [Anti-aliasing]

[0295] The high-efficiency anti-aliasing filter (AAF) 870 with integer multiple downsampling capability is a cascaded integrator combo (CIC) filter 872, which is an optimized type of finite impulse response (FIR) filter combined with an interpolator or integer multiple downsampler. An example of the CIC 872 implementation architecture is shown in Figure 87, which has an input from an ADC 874, a numerical controller oscillator 876, and further filtering, data symbol correlation 878, and downconversion 880.

[0296] The advantage of the anti-aliasing filter 870 is that the integrator is easy to implement and does not require overload logic. The CIC 872 implementation is general because almost no configuration parameters need to be changed. However, the limited number of configurable parameters also implies that the filter is not very tunable for specific RF signal modulation. Furthermore, the filter is located after the ADC 54 and does not reduce the processing load of the ADC 54. Therefore, this limits the AAF implementation, which must be highly efficient and generally reduces the sampling by an integer multiple after an equalization filter. As will be discussed below, the complexity of this CIC implementation is not guaranteed.

[0297] [Basic anti-aliasing]

[0298] To implement basic receiver-side anti-aliasing in the current DSDR architecture, a low-pass filter (LPF) can be added before the ADC in the DSDR architecture shown in Figure 2. A fixed LPF 882 is used as the anti-aliasing filter, based on a bandwidth of half the ADC sampling rate. A block diagram of the direct sampling high gigabit / second architecture 880, showing the LPF 882, can be seen in Figure 88.

[0299] Note that antenna 12 is ineffective for low frequencies; therefore, the combination of the antenna and LPF on the receiving side provides a wideband filter before digitization. On the transmission side of Figure 2, DAC 16 acquires signal samples and converts them into an RF signal. LPF 882 removes high-frequency spurious signals from DAC 16. This signal is then amplified and transmitted.

[0300] Furthermore, on the transmission side, the system DSP 20 in Figure 2 generates a bandpass signal that incorporates the input information, converts the bandpass signal to an analog signal, provides a bandpass RF filter to clean the signal, and then amplifies and transmits the filtered RF signal. This type of anti-aliasing implementation is enabled by a high-Q, narrow-bandwidth tunable response and its extensions within a positive feedback loop.

[0301] The positive feedback loop in Figure 2 can be redrawn as a simple arrangement of three components on the receiving side as shown in Figure 89, which includes: a signal source input 892, which can be connected to an antenna or to an RF system in which the desired signal is to be processed; a narrowband filter, which consists of a filter component network 894; a sampling device (ADC) 896; and a DSP 898, which is used for post-detection processing.

[0302] Anti-aliasing filters with a fundamental frequency can be advantageous because they eliminate the need for complex coefficient multiplication and are typically used for pre-integer multiple downsampling operations that dominate the overall DSP power requirements, even though CIC integrators are highly efficient and usable in general. However, this is not always feasible, as band mapping during downsampling can be a significant contributor to overall noise. A high final integer multiple downsampling rate can result in a substantial reduction in the subsequent DSP clock rate, thus reducing concerns about power dissipation.

[0303] [Band folding in a positive feedback loop]

[0304] The positive feedback loop has the following properties: it can form a stable high-Q pole (which is necessary to avoid all scrambling noise and to use anti-scrambling filters to reduce the complexity of the band mapping before downconversion); it uses the band folding shown in Figures 90a and 90b; and it is a method to eliminate scrambling with negligible spectral regrowth while saving power.

[0305] Band folding is based on the Nyquist frequency Nf = 1 / Δt, where t represents the time increment between observations. Note that the Nyquist frequency is a property of discrete-time systems, while the Nyquist rate is a property of continuous-time signals.

[0306] Any excessive noise accumulated during folding is of concern. In ADC sampling where frequency bands that are multiples of the sampling frequency are folded, the sampled output is the superposition of these folded frequency bands. However, since only one folded frequency band contains the signal, excessive noise will not accumulate.

[0307] To avoid superimposed noise, it is necessary to: 1. The out-of-band spectral regrowth of the RF filter is negligible, and 2. The frequency selectivity of the RF filter is sufficiently close around the desired signal.

[0308] Figure 90a illustrates the presence of frequency overlap and noise 904 that may superimpose on the desired signal 902.

[0309] Figure 90b illustrates the effect of the filter, which removes spectral components from the folded bands, except for the band containing the desired signal. Line 906 represents the folded band without the filter, and line 908 represents the folded band with the filter. Due to its high frequency selectivity, the filter can be a sufficiently narrow band without spectral re-growth, resulting in no frequency superposition distortion in the ADC samples.

[0310] Therefore, the ADC does not need to extend the quantization and dynamic range of these unwanted signals.

[0311] [Dynamic Range Considerations]

[0312] The limitation of Figure 3 is that digitization in both the receiving and transmitting directions has sufficient dynamic range to digitize a wide bandwidth of the input signal. All noise and interference signals can be digitized along with the desired signal. Quantization noise during the digitization of the desired signal may not be the primary factor limiting the achievable signal-to-noise ratio (SNR). For this reason, the ADC can have a moderate number of quantization bits and a high sampling rate. Furthermore, the dynamic range of the DSP can be preserved.

[0313] Each DSP operation before bandpass filtering to remove out-of-band frequency components adds quantization noise and degrades dynamic range. Therefore, these initial DSP processing steps can be very intensive.

[0314] On the transmission side, signal samples are generated in the RF passband and converted into analog signals. This is a highly intensive DSP process because the DAC can only eliminate conversion artifacts via a subsequent LPF. Therefore, the DSP and DAC can handle samples with low quantization noise, which in turn means a moderate number of bits. This limits the processing in Figure 3 to applications that can tolerate such high-speed conversion and intensive DSP, as well as the associated DSP power consumption.

[0315] To make SDR a reality, a tunable narrow-bandpass filter architecture is desirable when there are no high performance requirements for ADCs, DACs, and DSPs (generally, dynamic range). It provides robust and stable active Q enhancement to achieve the desired signal capture and mitigate nearby interference.

[0316] The upstream signal loop can be programmed and controlled to provide arbitrarily high Q values ​​in the thousands. Therefore, all filtering can be performed in this tunable high-Q bandpass filter before band digitization and DSP, to isolate the desired signal and eliminate all out-of-band interference.

[0317] [Reduced timing jitter in positive feedback loop]

[0318] SH distortion and gate clock jitter become critical for achieving acceptable performance in SDR. During the transition time, the matched filter output will have a high rate of change of signal voltage over time (dv / dt). This requires a very short transition time to obtain a sufficient sample definition, which significantly limits tolerable clock jitter. For example, consider a GPS signal with a bandwidth of approximately 1.2 MHz and a data rate of 50 Hz, resulting in a T of 20 milliseconds. Since the symbol rate is only 50 Hz, a suitable SH, ADC, and DSP capable of operating at a 1.5 GHz carrier can be provided by a very slow processor (such as an Arduino). However, if the signal is sampled at a rate of 1 / T, the dv / dt of the sampled point is correlated with a signal with a bandwidth of 1.2 MHz. Therefore, the transition time for the ADC to sample the chip-level matched filter output of the GPS baseband can only be tens of nanoseconds. But this requirement is negligible compared to the 1.5 GHz carrier rate in DSDR, where significant changes occur within tens of picoseconds. Transition timing jitter ultimately limits the effect that can be achieved by reducing the sampling rate.

[0319] Referring to Figure 91, consider a scheme where a local oscillator 910 down-converts the carrier signal before ADC sampling. After down-conversion, there is an LPF 912 with a signal bandwidth that is coarsely averaged over a time constant, which is the reciprocal of the bandwidth. The ADC then samples at a Nyquist rate twice the bandwidth of the LPF. The carrier down-conversion can be viewed as the LPF sampling the initial bandpass signal once per cycle, and then performing a short-term average of these samples using a time constant consistent with the time constant of the LPF. The output of this short-term average is then sampled.

[0320] The LO (Local Optical Array) shown is a pulse train with the same rate as the carrier. The jitter of one LO pulse is independent of the next pulse, resulting in voltage noise in the sample of (dv / dt)dt. However, since these are independent in the LPF (Local Perimeter) after downconversion, the jitter is averaged. For example, consider a 10 GHz carrier and a 10 MHz LPF bandwidth. Then, downconversion is equivalent to averaging 1000 jitter source noise samples, thus effectively eliminating the sampling jitter problem. The remaining noise is the low-frequency phase noise of the LO clock.

[0321] Jitter reduction can also be achieved using an oversampling ADC. This is the same function as downsampling conversion. Assuming a 10 GHz carrier signal is sampled at 10 GHz, the ADC samples are then averaged and downsampled by an integer multiple. Similarly, 1000 jitter source noise samples are averaged to eliminate jitter noise.

[0322] However, an oversampling rate of 1000 is generally too high for eliminating jitter noise. Instead, consider reducing the ADC sampling rate to 1 GHz, averaging 100 samples. Therefore, the RF BPF can be set to include only 10 MHz of the desired signal bandwidth. This eliminates any excessive noise caused by band folding. If the upstream signal loop has a sufficiently matched filter and sampling jitter is not a problem, the ADC sampling rate can be set as low as 1 / T. If jitter is a problem, the ADC rate can be increased to achieve sufficient jitter averaging to meet specifications. This specification will be lenient for simple modulations such as Binary Phase Shift Keying (BPSK) and Quadrature Phase Shift Keying (QPSK), but will be stringent for complex high-order QAM clusters.

[0323] Therefore, the upstream signal loop may provide a sufficiently matched filter response, allowing the sampling rate to be as low as 1 / T. For cases where sampling clock jitter is a problem, the ADC sampling rate can be increased to over 1 / T to achieve sample averaging. Furthermore, the upstream signal loop can be used in conjunction with LO downconversion before ADC sampling to achieve a similar effect. For example, downconverting the LO to the baseband signal and performing corresponding ADC sampling is equivalent to a high-speed sampling once per RF cycle, then averaging over the ratio of carrier frequency to the desired signal bandwidth. In other words, including an upstream signal loop in the DSDR allows the ADC sampling rate to be set according to the clock jitter reduction required to meet overall SNR requirements (more generally expressed as Eb / No requirements).

[0324] The concept of matched filters also extends to significantly reducing the quantization requirements of ADCs. Taking BPSK as an example, whether the symbol amplitude is positive or negative is meaningful. Referring to Figure 92, which shows a BPSK receiver 920, the signal 922 is filtered by an upstream signal loop 40 configured as a matched filter. The ADC is a simple comparator with carrier tracking 924, clock 926, data output 928, and sample-and-hold 929. The sampling time is based on the clock output controlled by a carrier and symbol clock synchronization scheme. Since BPSK is relatively robust to jitter, the ADC sampling rate may only need to be 1 / T. Excessive sampling is not required to reduce jitter.

[0325] In more complex receiver processing, encoding will be applied to a set of BPSK symbols. To achieve higher efficiency, it is necessary to use schemes such as software decoding, which may require an ADC with several quantization levels. AGC feedback is required in this case. However, the number of ADC levels does not outweigh the advantage gained from software decoding. That is, four quantization levels are sufficient, and increasing them further yields diminishing returns. Furthermore, if jitter is excessive, a down-conversion converter can be added before the ADC to eliminate the problem, or the comparator can be sampled faster and averaged.

[0326] Next, consider QPSK with only two orthogonal channels of BPSK. A total sampling rate of 2 / T can be used to provide the required quadrature sampling. This facilitates implementation using a mixing device at the output of the upstream signal loop, which can provide both in-phase and quadrature phase components. A QPSK comparator can still replace an ADC because the basic signal system is BPSK. If an N x N QAM cluster is considered, only log 2(N) bits of an N-stage ADC are needed.

[0327] QAM modulation is common in high-speed communication signals. For such schemes, information is contained within the amplitude, and a single-bit quantization is insufficient. However, an ADC can be used to implement QAM schemes, where the number of ADC levels equals the number of QAM levels. Therefore, for 64 QAM, only an 8-stage ADC and DAC are needed, i.e., 3 bits. This can be achieved using a high-speed flash converter, such as shown in Figure 93, which includes input quantization 932, bubble error correction 934, and digital encoding 936.

[0328] The key point is that the upstream signal loop can be a sufficiently narrow resonator, ensuring that only the desired signal, containing some in-band noise and interference, reaches the quantizer. Therefore, the symbol decoder is the output of the quantizer / accumulator / integer downsampling procedure. If equalization is required to minimize ISI and provide a matched filter response, the upstream signal loop can be tuned directly. In this case, an additional DSP-based equalizer may not be necessary.

[0329] There exist modulated signals for which ADCs / DACs with a few fixed quantization levels are insufficient. For example, consider LTE modulation, where multiple signals are superimposed and the signal amplitude samples have a more Gaussian distribution. For such signals, more quantization levels may be required, especially when the SNR within the frequency band is very high. In this case, quantization noise can become the dominant contributor to overall noise and irrecoverable distortion, which is undesirable.

[0330] In summary, a reduced sampling rate of 1 / T has been considered, while the carrier frequency can be arbitrarily high. Jitter in the noise sensitivity of (dv / dt)dt is considered a limitation. Another limitation to consider is the sample-and-hold (SH) device. SH has practical limitations because the ratio of sample-and-hold time to transition time cannot be arbitrarily large. Advanced SH devices use cascaded switches and holding capacitors to improve this ratio, but this introduces overall sampling noise and distortion. As the ratio increases, a faster ADC may be required, with a transition time commensurate with the limitations of SH.

[0331] Including a faster ADC increases the sampling rate, at the modest cost of a faster DSP clock. A multi-stage circuit 940, shown in Figure 94, is used to increase the hold time to transition time ratio and includes a switch 942, a hold capacitor 944, a pulse stretcher 946, and a pulse gate signal 948.

[0332] While a matched filter can theoretically be achieved using a set of poles from the upstream signal loop, some limitations exist. Establishing an all-pole approximation for a root-raised cosine filter is achievable, but establishing a Barker code impulse response for a spread-spectrum signal without zeros is not feasible. Zeros can be generated in the upstream signal loop by paralleling some components. However, controlling the location of these zeros can be difficult. Therefore, matched filters can be categorized into analog and digital component filters. Consider Barker codes as an example. The matched filter corresponding to the chip is implemented in the upstream signal loop, while the Barker correlation is implemented in the DSP. In this case, the sampling bandwidth is the chip rate, not the symbol rate.

[0333] Spread spectrum codes can be viewed as convolutions of small segments and large segments. A simple example is the Manchester code, which is often used to guarantee a zero average value regardless of the data. An example is shown in Figure 95, where the subcode elements are (1, -1). Note that the upstream signaling loop can be configured to provide an impulse response that reproduces the (1, -1) segment. One implementation may consist of two branches, one containing a bandpass filter and the other containing a cascaded bandpass filter and a delay. The outputs of the two branches are combined. Note that the poles of this circuit remain the same, but the combination of the outputs of the two branches results in manipulation of the zeros.

[0334] Consider a communication receiver with modulated symbols of incoming data subjected to noise and interference. The receiver needs to process the signal by aligning the symbol components of the incoming signal with ideal orthogonality to the noise components. This is easily visualized in the signal space, where the receiver's processing occurs along the symbol basis functions. Assuming that the noise is uniformly distributed across all orthogonal signal basis functions in the signal space, this results in symbol correlation in the time domain and a frequency-matched filter from a frequency domain perspective.

[0335] The symbol implicit minimum sampling rate for the most complex phase and amplitude data modulation with a duration of T is 1 / T. Note that the symbol time is not necessarily inversely proportional to the bandwidth of the individual symbol pulse shape signal, and in fact can be quite uncorrelated. For example, spread-spectrum coded symbols used in CDMA can have bandwidths much larger than 1 / T.

[0336] Another application of the disclosed architecture is that the poles of the upstream signal loop can be positioned so that the frequency response or impulse response of the filter matches the data symbols, resulting in a matched filter as described above. The ADC can then subsample at the lowest possible rate of the data signal symbol ratio. Note that a symbol ratio of 1 / T may be lower than the actual Fourier bandwidth of the data symbols themselves. However, such a low sampling rate is only feasible if the RF filter is precisely centered on the desired signal. This level of accuracy is achieved through calibration and adaptive feedback tuning during operation of the upstream signal loop.

[0337] [Using a negative feedback outer loop to remove spontaneous processing noise from RF signal processing]

[0338] We will consider the dual-loop architecture described above and, for example, in Figure 3.

[0339] A positive feedback loop (or upper loop 40) composed of multiple resonators can be used as a tunable bandpass filter based on active feedback. Compared to variable capacitors that introduce nonlinear effects, loop components based on switching reactive components can exhibit higher linearity. The resonators are placed upstream of the downconverter and ADC, both of which are susceptible to large out-of-band signals and broadband noise. The resonators can be operated to provide a mid-Q pole of approximately 100, offering very effective bandpass filtering to suppress most unwanted noise and interference entering the downconverter and ADC.

[0340] Turning to the negative feedback loop in Figure 3, the implementation of DSP 52 within the FEM module can achieve the following functions: 1. Independently place the poles of the positive feedback loop resonator as described above. 2. Remove quantization noise from the signal passband.

[0341] For reference, the signal processing circuit is shown in Figure 96.

[0342] A key approach to quantization noise removal is to implement a variable bandpass Δ-Σ modulation method that shifts the quantization noise out of the signal band. Δ-Σ modulation (DSM) is a well-known fixed-frequency scheme.

[0343] The signal plus noise input is down-converted to the fundamental frequency to produce a fundamental frequency Δ-Σ, and an integrator is used to provide a pole at s = 0, which is a previous technique. When using a bandpass filter with a center frequency of fc to transfer the direct sampling operation, the integrator is now replaced by a resonator centered at frequency fc. This produces a bandpass Δ-Σ modulator (BP-DSM).

[0344] One problem with broadband BP-DSM is obtaining a tunable resonator with sufficient Q. Because current BP-DSM implementations operate at a fixed bandpass center frequency and are therefore untunable, BP-DSM is not currently used at RF / microwave frequencies. However, this problem can be addressed by providing a tunable resonator with a high and stable Q independent of frequency variations in the upstream loop. In this embodiment, the resonator can be shared by both positive and negative feedback loops, thereby establishing a variable bandpass frequency Δ-Σ modulation (VBP-DSM) scheme 970.

[0345] Please refer to FIG. 97. The diagram of the VBP-DSM 970 can be drawn as a resonator having an analog positive feedback loop (upstream signal loop 108), a digitizable negative feedback outer loop 974, an input 976, an output 978, and a phase shifter 980.

[0346] [Variable Bandpass] [Delta-Sigma]

[0347] The feedback path can be used to implement a variable bandpass delta-sigma. In this case, the poles of the upstream signal loop become the zeros of the QNTF. The movement of the dominant resonator poles in the VBP-DSM is shown in FIG. 98. The important notes regarding FIG. 98 are: 1. The filter poles are denoted by asterisks and also form the zeros of the QNTF. 2. This zero (dashed circle) cannot be moved by feedback. 3. However, the poles of the QNTF start at the same position as the zeros, canceling the effect. 4. The poles can be moved away from the zeros so that the zeros have any effect.

[0348] It is important to note that in the case of negative feedback (Q suppression), the poles may move to the left, separating the upstream signal loop poles from the zeros. The system effects of the negative feedback loop will be discussed further below.

[0349] The effect is that the zeros of the QNTF now reduce the response in the middle of the passband. As also observed, the poles must have a high Q before forming the feedback loop. This is the reason for limiting the delta-sigma application. However, with the upstream signal loop, the Q can be increased such that the zeros of the QNTF become relevant.

[0350] Consider the VBP-DSM with the following general bandpass filter The closed-loop response of the filter is given by where G represents the feedback. The transfer function of the quantization noise is given by which shows that the poles of the filter are mapped to the zeros of the QNTF, as discussed previously. However, consider the ratio of the closed-loop signal to the quantization noise: This is the filter transfer function independent of the feedback level G. It can be seen that increasing G reduces a) the signal level arriving at the ADC and b) quantization noise. Therefore, the important consequence is that VBP-DSM allows for a reduction in the signal level entering the ADC without increasing the effective NF of the receiver.

[0351] The negative feedback loop will nominally have a very narrow passband. Therefore, the analysis can be simplified to an equivalent complex envelope analysis. The integrator poles move from the origin along the real axis to LHP.

[0352] Because the upstream signal loop poles shift more significantly to the left with negative feedback, the effectiveness of Δ-∑ in reducing quantization noise decreases. In this case: The simulation results are shown in Figure 101.

[0353] Adding ADC to alleviate saturation, as described below, results in Simulink model 1020 (Figure 102), and the simulation results are shown in Figure 103.

[0354] [Solution for a first-order negative feedback loop] []

[0355] Next, consider how to implement the negative feedback loop to achieve a first-order VBP-DSM 970 with an upstream signal loop 972, as shown in Figure 104. The upstream signal loop is Q-enhanced to form a pole with a Q-coefficient of approximately 100. This is in the feedback loop 974 of the discrete filter transfer function 1042 with ADC 54, DAC 56, and H(z). H(z) may only include gain, and perhaps some delay to model the pipeline delays of ADC 54 and DAC 56. Signal input 32 can pass through the low-noise amplifier 1042.

[0356] Obviously, ADCs / DACs do not necessarily need to be direct samples and can include frequency shifting, but the following should be considered: If direct sampling is implemented, the upstream signal loop 972 can be used to protect the downconversion mixer from out-of-band interference. In such cases, an LPF can be added to provide any desired pole for Δ-∑. Chip-integrated downconversion mixers can suffer from a weakness in noise level (NF), typically around 14 dB. This stems from the way the LO switching FETs in the mixer operate. During the transition, there is a quasi-linear period where the output is essentially a linearly amplified LO noise. As mentioned above, mixer noise significantly increases quantization noise. However, the combined mixer and quantization noise can be approximated as statistically independent of the desired input signal and can therefore be reduced using VBP-DSM processing.

[0357] [Solution for a Second-Order Negative Feedback Loop] []

[0358] With the Simulink model 1050 shown in Figure 105b, a second-order loop system with two upstream signal loops 972 is feasible, as shown in Figure 105a.

[0359] With saturation levels of 0.5 and -0.5 and an input gain set to 0.5, the second-order loop provides good attenuation of quantization noise, as shown in Figure 106. Again, quantization is performed at 0.2 intervals, resulting in a level system {-0.5, -0.3, -0.1, 0.1, 0.3, 0.5}.

[0360] If ADC saturation is sensed, an AGC-like control is added to reduce the gain. As mentioned earlier, reducing the gain in front of the ADC has the same effect as increasing the quantization step, but allows for an increase in the degree of saturation.

[0361] [Add additional extreme points] [Δ-∑]

[0362] Next, consider the possibility of adding additional poles to H(z) in the equation. The system is mapped to the s-domain using a Δ-∑ filter. The signal path is now given as... Now QNTF is given as Therefore, it can be seen that the additional zeros in the QNTF can be contributed by the VBP-DSM filter. Furthermore, the ratio... As mentioned earlier, additional poles can be added to the VBP-DSM filter, which will provide different closed-loop responses without affecting the ratio of the input signal level to the quantization level. This provides additional design flexibility.

[0363] [Features variable frequency and] [Q] [of] [Δ-∑] [Modulator]

[0364] The dual-loop circuit can be represented by the upstream signal loop 970 used as the BPF, which has a positive feedback gain 1072 (G > 0) in the feedback path 1074 and a negative feedback loop 974, as shown in Figure 107. From the viewpoint of the input signal, the signal sees a net Q bandpass pole, which is derived from the Q enhancement of the resonator in the positive feedback loop and the Q suppression in the negative feedback loop. From the viewpoint of the quantization noise in the negative feedback loop, there are slightly separated poles and zeros, which make the zeros the agents of the fundamental frequency Δ-∑.

[0365] Alternatively, the ADC may be a direct sampling ADC that does not require down-conversion. In this discussion, direct sampling ADCs have been used for most of the analyses. However, this can be implicitly understood as down-conversion before the ADC. Several possible variations can also be included in the analysis and development of dual-loop architectures. As discussed, the principle of dual-loop can be considered independently of the down-conversion and digitization method. Therefore, the considerations for direct sampling can also be applied to general down-conversion and digitization schemes.

[0366] The upstream signal loop 972 also provides the required medium-high Q bandpass poles, which is essential for implementing the VBP-DSM 970 loop. The primary purpose of the VBP-DSM 970 is to suppress quantization noise during the digitization process within a narrow bandwidth of the desired signal. This is achieved by practically shaping the noise spectrum of the ADC 54 quantization noise to frequencies outside the desired signal's bandwidth.

[0367] Ideally, an effective VBP-DSM 970 combined with further Q-enhancement of the resonator poles would simultaneously result in higher frequency selectivity of the desired signal. However, to achieve the desired noise spectrum shaping, Q-suppression of the upstream signal loop components may be necessary. Therefore, the proposed VBP-DSM implementation can be considered a compromise, with the primary goal of achieving the highest possible SNR output for the digitized process. The dual loops can utilize negative feedback loop DSP filtering to achieve the final passband shaping of the desired signal, as will be discussed.

[0368] The generalized dual-loop architecture 1080 is illustrated in Figure 108. When a less than approximately 5 dB NF is required, the LNA 1042 is advantageous because its gain compensates for the loss in the summing block and the NF of the upstream signal loop 972. This diagram includes only one upstream signal loop 972, but two upstream resonator components can be used to implement a higher-order VBP-DSM. When using a direct-sampling ADC, down-conversion and up-conversion may not be necessary. The dual-loop architecture 1080 incorporates a DSP bandpass filter 1082, a scaling block 1084, and a VBP-DSM 970 in the negative feedback loop 974.

[0369] The VBP-DSM 970 can be used to shape noise in components after the upstream signal loop 972, keeping the noise outside the bandwidth of the desired signal. This results in a significant reduction in the frequency response (NF) of this section of the circuit. Thus, the signal level entering this part of the circuit can be reduced by scaling the entire signal. This is the function of the scaling block 1084 in Figure 108. As the signal amplitude entering the down-conversion and digitization block decreases, the linearity of the entire receiver is improved, allowing for the accommodation of larger out-of-band interference signals.

[0370] Analyzing the VBP-DSM 970 can be challenging due to the need for mixed-signal modeling. This is simplified by approximating the bandpass operation as the equivalent fundamental frequency below. This allows for efficient time-domain simulation. Secondly, the nonlinear behavior of the digitization process can be linearized, thus allowing for Laplace LTI analysis. This is the first step in demonstrating that the fundamental frequency modeling represents a variable bandpass dual-loop system. Then, the fundamental frequency VBP-DSM can be described by introducing simultaneous transfer functions for both signal and noise, and is considered as a first-order and second-order VBP-DSM in the negative feedback loop of the dual-loop architecture.

[0371] [Variable base frequency] [Δ-∑] [Formalism]

[0372] In this section, the equivalence of bandpass poles as first-order low-frequency poles will be considered to prove the rationality of the fundamental frequency model for representing bandpass systems with variable bandpass Δ-∑. The input impedance of the parallel RLC resonator is considered, given as... Specifically, consider surrounding An extension of. This can be written as It can be approximated as This is valid, provided that... Therefore, this approximation refers only to the operation around the resonance, not to the Q of the pole itself. Using self... It can be simplified to Finally, it was formalized into This only depends on The bandpass pole parameters. Therefore, in The bandpass pole is equivalent to the low-pass pole of DC. Consider the expression Therefore, the poles are set on the negative real axis. This was expected.

[0373] [First-order fundamental frequency is variable] [Δ-∑]

[0374] Referring to Figure 109, a first-order VBP-DSM 970 may include a single negative feedback loop 974 having a single upstream signal loop 972, an ADC 54, a DSP 52, a DAC 56, a negative feedback gain 576, and a summing block 780. The negative feedback slightly Q-suppresses the poles of the negative feedback loop within the VBP-DSM.

[0375] From the perspective of ADC quantization noise, the transfer function is H(s) = s / (s+G), while from the perspective of the input signal, the transfer function is H(s) = 1 / (s+G). Therefore, the signal-to-noise ratio (SNR) is 1 / s. Note that the SNR is independent of G. This hides the fact that as the negative feedback loop BPF poles move away from the jω axis, the signal bandwidth increases as the negative feedback loop G of the VBP-DSM decreases.

[0376] In the example shown in Figure 110, the dual-loop architecture combines the positive feedback loop 1100 with the negative feedback VBP-DSM loop of Figure 109, and adds a variable phase shifter. The positive feedback loop 1100 has a positive gain block 1102 and a phase shifter 1104.

[0377] When the delay is included in the positive feedback loop 1100, the limitation of G < 0 can be seen. To analyze this, it is necessary to switch to discrete-time analysis, where the pole trajectory eventually crosses the unit circle and the positive feedback loop becomes unstable.

[0378] The positive feedback loop 1100 provides a narrowband Q-enhancing pole for the input signal 32, thereby protecting the ADC 54. It also provides a zero close to the jω axis for quantization noise of the ADC 54, which is effective in reducing quantization noise around the desired signal band.

[0379] Consider the implications for input signal 32. The positive feedback loop 1100 at the top is connected in parallel with the negative feedback loop 974 at the bottom. Therefore, if feedback loop 1100 compensates for the gain of negative feedback loop 974, the net Q enhancement can remain the same. The total feedback gain is significant when the poles are pushed toward the jω axis. This becomes the zero of VBP-DSM 970 and negative feedback loop 974. In other words, the dual loops allow independent control of the pole and zero positions.

[0380] The positive feedback loop gain 1100 can now be greater than 1. Without the negative feedback gain 576, a positive feedback loop gain G > 1 would result in an unstable feedback loop that oscillates. The external negative feedback loop gain can be increased from low to high values ​​to stop the oscillation. This provides the ability to approach the zeros of the jω axis and move away from the poles of the jω axis, thus providing the desired stable bandwidth for the desired signal.

[0381] The results in the previous section demonstrate the rationale for modeling the VBP-DSM 970 as a baseband delta-sigma module (BB-DSM), provided that the Q of the bandpass poles is sufficiently high. This is convenient because BB-DSMs are easier to develop and analyze. First, consider the continuous-time loop 1110 shown in Figure 111, where the transfer function block 1112 is G / s. It is known that BB-DSMs have integrators, representing resonators with infinite Q. The effect of poles with negative real parts will be considered later.

[0382] Let the Signal Transfer Function (STF) represent the transfer function from the input to the output, and let the Quantization Noise Transfer Function (QNTF) represent the transfer function from the quantization noise source at the ADC output to the output port.

[0383] In ADCs and DACs, arbitrary mappings from analog to digital and digital to analog can be considered, each with a gain of 1. Then, there exists an additional loop gain associated with the integrator, such that the transfer function is G / s. Based on this, the transfer function can be written as:

[0384] Therefore, the poles of the STF system are located in the first-order low-pass filter at s = -G, while the poles of the QNTF system are also located in the high-pass filter at s = -G. Importantly, the QNTF has a zero at s = 0 (see Figure 98). Therefore, for low signal frequencies << G, quantization noise is suppressed in the output, while the desired signal passes through.

[0385] This is the core concept of VBP-DSM, which is that the signal passes through at low frequencies without loss, while quantization noise is suppressed.

[0386] However, this ideal characteristic disappears at higher frequencies. Therefore, VBP-DSM is suitable for situations where the ratio of the ADC sampling rate to the Nyquist rate of the bandpass signal is large.

[0387] In the continuous-time STF and QNTF given above, if G increases, the poles move along the real axis into the LHP, and the cutoff frequency increases. Therefore, the effective frequency range of the VBP-DSM increases. However, this limits the ADC sampling frequency.

[0388] Now consider a signal g(t) with frequency ωs << G and an interference v(t) with frequency ωv << G, such that both components pass through the loop with unity gain. Therefore, the output will be approximately g(t) + v(t). The added noise is q(t), but is attenuated by approximately ωs / G at the signal frequency and by ωv / G at the interference frequency. It can be assumed that there is a subsequent filter after the VBP-DSM loop to remove the higher frequency interference.

[0389] The key point here is that VBP-DSM is not intended to suppress interference relative to the desired signal. Rather, it aims to suppress quantization noise at the desired signal frequency. The actual form of the quantization noise at the interference frequency can be disregarded, as it can be assumed that subsequent DSP bandpass filtering around the desired component suppresses interference.

[0390] Next, the approximate equivalent of the integrator can be considered to be replaced by a discrete-time accumulator. This is accomplished using mappings, such as... Next STF series It has an extreme point at For QNTF, the zero point is held at z = 1. In a true ADC, the conversion has a delay, allowing an additional z⁻¹ to be included in the open-loop transfer function: Next STF series There is a pole at z = .

[0391] When GT exceeds 2, the poles move away from the unit circle, at which point the VBP-DSM becomes unstable. Furthermore, it should be clear that the zero-point effect of QNTF at z = 1 only applies to frequencies lower than the sampling frequency.

[0392] [by] [100 Hz] [First-order signal sampling] [Δ-∑] [Example]

[0393] The following is an example of a first-order VBP-DSM with a sampling rate of 100 Hz and an ADC quantized with a resolution of 0.2. Four input sine signals with different frequencies are used in the Simulink model 1120, as shown in Figure 112. This is necessary because the difficulty in modeling quantization noise lies in that it is not real noise but a deterministic function of the combined input. If there is only a small desired input signal, the behavior of quantization noise will be unrealistic. Therefore, one sine wave represents the signal and three sine waves with higher frequencies represent the interference. When plotting the resulting power spectrum, it is easy to distinguish what is the noise floor caused by quantization noise and what is the interference signal. This clearly demonstrates the benefits of the VBP-DSM brought by noise shaping.

[0394] The spectrum shown in Figure 113 exhibits four frequency components. The amplitude of all sine waves is 1. The noise floor in the spectrum is entirely caused by quantization noise. Note that the reduction of the noise floor at low frequencies is the desired noise shaping. Therefore, the desired signal is placed in this low-frequency region, and the effect of quantization noise is greatly reduced.

[0395] Note that the required gain may seem important, which is a problem in the closed loop. However, this gain is associated with the integrator, so this gain is illusory, and as in the physical circuit, it is more about how quickly the capacitive integrator can be charged by the current source. Note that making the capacitance smaller is equivalent to increasing the gain. The integrator can also be replaced by a discrete-time accumulator (as shown in the Simulink model 1140 depicted in Figure 114), and the same result can be obtained.

[0396] [1 Hz] [with weak frequency modulation (] [Weak Tone] [) signal of the first-order] [Δ-∑] [example]

[0397] In the following simulation, the signal is 1 Hz, the amplitude is 0.1, and there is some interference with higher frequencies each with an amplitude of 1. The results are shown in Figure 115. Note how the VBP-DSM significantly improves the SNR of the signal by approximately 18 dB.

[0398] [Second-order] [Δ-∑] [provides additional quantization noise suppression]

[0399] Now turn to the second-order VBP-DSM 970 shown in Figure 116, which displays two upstream signal loops 972.

[0400] The advantage of second-order induction is that it provides a second zero for quantization noise in the passband of the desired signal. In complex fundamental frequencies, this can be modeled using a pair of integrators 1172 (representing 1 / s1 and 1 / s2), as shown in Figure 117.

[0401] If we analyze the movement of the closed-loop poles of this circuit, the result is the trajectory shown in Figure 118.

[0402] The additional positive feedback loop of the second-order VBP-DSM 970 allows the passband poles to be placed anywhere in the LHP, providing significant design flexibility. For example, gains G1 and / or G2 can be adjusted to make both positive feedback loops unstable and oscillating. Then, G3 and / or G4 can be increased until the oscillation stops. In this way, more control over the pole placement is possible, and poles can be placed arbitrarily near the jω axis. This provides flexibility in configuring the VBP-DSM for desired signal passband and VBP-DSM noise suppression.

[0403] Using a second-order system can further suppress quantization noise. This has two 1 / s integrators, as shown in Figure 119a. The Simulink model 1190 is shown in Figure 119b.

[0404] The significant results using an ADC with only six quantization levels {-0.5, -0.3, -0.1, 0.1, 0.3, 0.5} are shown in Figure 120, which illustrates the 28 dB SNR improvement resulting from shifting quantization noise out of the signal band by a second-order Δ-Σ.

[0405] At this point, ADC saturation has been avoided by reducing the input gain of the ADC but increasing scaling at the output of the ADC.

[0406] To aid in visualizing the signal flow within the negative feedback loop 974, consider the outer loop 50 at a higher level. This linear superposition must be taken into account, which results in random confusion between neighboring states for different quantizer output categories. This merely illustrates that noise in the ADC output will cause randomness between adjacent mapped values. For quantization noise, this can be viewed as confusion between a given state and its neighboring states.

[0407] [, ADC , ] [, Factors to consider , ]

[0408] [ADC] [Sampling rate]

[0409] Next, we will consider the sampling rate of the ADC. Let the sampling interval be T, and the sampling frequency be... (rads / sec). If the frequency is much higher than ωs or ωv, the effect of frequency folding does not need to be considered. Then, G can be increased to make the quantization noise negligible. This is equivalent to a high oversampling rate. Generally, it can be assumed that there are some pre-fixed filters commensurate with the ADC sampling rate, so that frequency folding does not occur.

[0410] Next, consider the saturation effect of the ADC. If the input signal is large enough to saturate the ADC, the SNR will decrease significantly. Saturation negatively impacts SNR and should be avoided. This can never be completely avoided because many interfering signals are typically superimposed on the input, which is calculated by combining the amplitudes. More of the signal backs up to the ADC system based on the RMS of the combined signal, and then the SNR degradation can be determined by approximating the probability density function of the combined amplitude as a Rayleigh metric. However, using input signal backscaling to manage saturation implies an increase in the equivalent noise index (NF) of this part of the receiver. This becomes problematic because the receiver system carefully balances NF and linearity. To calculate this, the ADC step size associated with kTB thermal noise can be considered.

[0411] If the input is scaled by a ratio of (1 / R), it can be directly concluded that, with the same ADC saturation probability, a higher interference power of 20log(R) is tolerable. In VBP-DSM, the transfer gain of quantization noise is considered to be ωs / G. Therefore, R can be set to G / ωs, and the quantization noise level is the same as the desired signal level, as if there were no scaling (R+1) and no VBP-DSM loop. However, an increase of 20log(G / ωs) dB in interference power level is tolerable, which can improve the ADC saturation problem.

[0412] In other words, if the ADC has a fixed sampling interval T, the power spectral density of the quantization noise will be proportional to 1 / T. Furthermore, if a VBP-DSM loop is implemented, the input can be scaled by a factor R = G / ωs without degrading the output SNR due to ADC quantization noise. For a first-order VBP-DSM, G is unrestricted. Only the poles shift towards the center. However, if the ADC delay is added, G will be subject to a limitation, though not significantly.

[0413] In one example, a dual-loop architecture may involve a VBP-DSM to utilize the ADC's oversampling rate to reduce quantization noise, which subsequently allows for less signal entering the ADC, resulting in higher interference tolerance.

[0414] Why doesn't Q-boosting provide this benefit? With Q-boosting, the pole at ωs will be closer to jω, resulting in a larger gain at the desired frequency. There is no boosted gain at the interference frequency. But this means that although the desired signal is grown relative to the interference signal, the interference signal is not suppressed. Therefore, at the ADC input, there is now a larger desired signal and an interference signal of the same size. But it now appears that the ADC input can be reduced, but this only reduces the loop gain that can be maintained for Q-boosting. Scaling the signal outside the loop triggers an increase in NF, which can be seen by taking the quantization noise and replacing it with an equivalent noise source at the loop input. Now, the quantization noise directly competes with the desired signal, which is now attenuated due to scaling.

[0415] [Frequency modulation input mixed and scaled] [ADC] [Saturation effect]

[0416] Next, consider the effect of ADC saturation. Here, the ADC saturation is set to ±1. The effect is shown in Figure 121, where it can be seen that due to the hard saturation of the ADC, the intermodulation of the four sine waves becomes mixed. The mixed frequency modulation is near the desired signal, which is obviously a problem.

[0417] To address this issue, scaling can be applied before the loop, as shown in the following simulation. The 6 dB attenuation depicted in the Simulink model 1220 in Figure 122 resolves the ADC saturation problem, as seen in Figure 123.

[0418] However, this is not a viable solution because the integrator's NF will have a moderate NF, and the 6 dB loss will be added directly to the integrator's NF.

[0419] [ADC] [Previously scaled] [ADC] [Saturation effect]

[0420] A better approach is to apply scaling in front of the ADC, as shown in the Simulink model 1240 depicted in Figure 124, where the gain is reduced to G = 20. The simulation results are shown in Figure 125, demonstrating the removal of the stray saturation effect.

[0421] By adding a larger scaling factor after the ADC, the Δ-∑ loop gain can be obtained again. If a feedback gain of 2.5 is added after the ADC, the loop gain is equivalent to a return of 50, and the quantization noise is improved as "G" increases from 20 to 50.

[0422] Due to the attenuator required to eliminate saturation, the desired 6 dB signal is lost to the ADC. However, the noise floor is improved by approximately 14 dB due to the 20 dB increase in VBP-DSM. Further improvements in SNR can be achieved with a lower input frequency, as demonstrated in Figure 126.

[0423] Software-Defined Radio (SDR) with Dual-Loop Mixed Signal Processing [SDR] [) Other details of the application]

[0424] One application of DPLP processing is the direct frequency shift discussed above, which can also be achieved in DSPs. DSPs use discrete-time sampling and quantization of the signal, along with subsequent reconstruction, to provide additional signal digitization, where feedback processing can be precisely implemented.

[0425] To apply the signal processing circuit 30 to the SDR, additional taps can be added to the signal processing circuit 30 discussed above, as shown in Figure 127. This includes adding a DSP input tap 1272 and a transmission output tap 1274 to the antenna 1276.

[0426] A more detailed view of the dual-loop hybrid signal processing architecture in the output mode can be seen in Figure 128, which shows the signal processing circuit 30 consisting of the following three parts: 1. The forward path from summing block 780 through inner loop 40, down-converter 1282, anti-overlap LPF 1284, and ADC 54 to DSP 52. 2. Feedback processing in DSP 3. The reverse path 55 from DAC 56 back to summing block 780 via upconversion 1286 and bandpass filter 1288.

[0427] As shown, the loop connects to antenna 1280, T / R switch 1281, and LNA 1283. The forward signal path, digitization, and DSP can be existing components of the SDR, as shown in Figure 128. Therefore, DPLP can be implemented in an SDR with conventional transmit and receive channels.

[0428] In Figure 129, antenna 1280 is fed to T / R switch 1281, with the receiver port connected to LNA 1283, and the DPLP forward path has multiple inner loops 40. DPLP loop processing is performed in DSP 52, and SDR feedback is achieved through DAC 56, upconverter 1286, and adder 780, as described above.

[0429] In standard SDR transmission mode, the DSP 52 uses DAC 56 and upconverter 1286 to generate the transmission baseband signal, but now the signal is passed to the power amplifier T / R switch 1281 and antenna 1280. In this way, the DPLP function requires almost no additional hardware. The bandpass filter 1288 after upconverter 1286 has a wide bandwidth and is designed to remove some parasitic DAC components, such as noise from DAC 56. However, this is hindered because DAC 56 is in the loop and generates noise.

[0430] For this purpose, an additional active RF feedback 1290 may be required, as shown in Figure 129. Note that appropriate additional hardware can be added to achieve transmission filtering.

[0431] Many SDR options are relevant here, some of which include: There may be no down-conversion in direct sampling SDR. Frequency shifting can optionally be handled in a DSP. This sampling method is applicable.

[0432] As an example, three single-pole point resonators can be equipped with an active feedback signal loop containing variable gain blocks to form a bandpass filter in the RF domain. When the feedback gain increases, the center poles of the three resonators move toward the jω axis, while the poles on both sides move a smaller amount away from the jω axis, thereby producing Q enhancement.

[0433] In contrast, if the feedback gain is reduced, the central poles of the three resonators will move away from the jω axis, and the poles on both sides will move a smaller amount towards the jω axis, thereby producing Q suppression.

[0434] However, using DPLP state-space feedback, each of the three s-plane poles can move simultaneously and independently toward the jω axis for Q-enhancement or away from the jω-axis for Q-suppression. This active feedback 3-pole BPF is always stable as long as no single pole moves from the left plane across the jω axis to the right s plane.

[0435] Active feedback BPF can be enabled, then this active feedback BPF path is disabled and the DPLP state space feedback path is enabled. In addition, referring to FIG. Active gain feedback control is useful for modest Q enhancement, in which case the resulting pole Q is modest. In FIG.

[0436] DPLP feedback processing may include upscaling conversion for use with a slower rate DAC, or may be performed at the signal frequency of a high sample rate DAC. Although DPLP is capable of Q-enhancing all three poles simultaneously, DSP processing delays may be introduced if the BPF bandwidth is too wide.

[0437] Referring to Fig. 131 , more resonator poles can be Q-enhanced using a cascaded bandpass filter 42 . These can be Q-enhanced in a bipolar point bandpass filter between the input port and the ADC port. Alternatively, DPLP can be used to simultaneously Q-enhance the quadrupole point bandpass filter used for all four resonators, as shown in Figure 131 .

[0438] In this patent document, the word "comprising" is used in its non-limiting sense to mean including the items that follow the word, but not excluding items not specifically mentioned. The indefinite article "a" in reference to an element does not exclude the possibility that there may be more than one element, unless the context clearly requires the existence of one and only one element.

[0439] The scope of the following patent application should not be limited to the preferred embodiments presented in the above embodiments and drawings, but should be given the broadest interpretation consistent with the entire description.

[0440] 10: Sampling Software-Defined Radio, Software-Defined Radio, Digital Signal Processing Block 12, 172, 222, 1276, 1280: Antenna 14, 78, 874: Analog-to-digital converters 16, 56: Digital-to-Analog Converter 18: Amplifier 20, 898: Digital Signal Processing Block 22. 1288: Bandpass filter 30: Signal processing circuit 32: Input, Signal Input 34: Output, Output Signal 40: Inner Ring Road 42: Bandpass filter, upstream processing block, processing block, inner processing block, inner loop tunable RF bandpass filter, tunable bandpass resonator network, tunable resonator network, resonator network, resonator, filter, multi-pole bandpass filter 44: Positive feedback variable gain block, variable gain block, internal feedback path processing block, internal feedback processing block, feedback processing block, gain block, feedback processing 45: Positive feedback loop, internal feedback path, feedback path, signal enhancement positive feedback path, processing loop; positive feedback path 46: Tunable resonator, resonator, network resonator, resonator network, variable filter 48, 152, 266, 1302: Feedback Processing 49: Control Block 50: Outer Ring Road, Outer Processing Ring Road 52: Digital signal processing block, digital signal processing, processing block 54: Analog-to-digital converter, downstream signal processing block, second signal processing block 55: Feedback loop, external feedback path, negative feedback path, reverse path 55a, 55b: Negative feedback loop, feedback processing path, feedback path 70: Sample and hold circuit 72: FET gate, switch 74: Input signal, input signal driver 76: Capacitor 80: Signal Path 82: Noise Handling 84: Negative Gain Block 85, 782, 902: desired signal 86, 99, 904: Noise 88: Summation Block 90: Dual-loop architecture 91: Upstream processing section, upstream processing, upstream section Blocks 92, 92a, 92b, 96, 110, 202, 204, 250, and 252 93, 93a, 93b, 97a, 97b, 234, 342, 574, 644: Gain Blocks 94: Downstream processing section, downstream processing, downstream section, downstream outer ring road processing 97: Gain Block, Gain Component 98:Tap point 100, 258, 776, 978: Output 102: Post-detection processing block 104, 832: Information 108, 972: Upstream signal loop 140:P pole 142: Initial closed loop position 144: Final closed loop location 150: First Transformation Block 150b: Third Transform Block 152b: Second Feedback Processing 154: Second Transformation Block 154b: Fourth Transform Block 174: Initial Bandpass Filter 176: Initial Amplifier 178: RF Feedback Gain 232: Analog Resonator Switched Capacitor Bank 254, 976: Input 256: Transformation 262: Loop 264: Filter 280:as 281:1 / s 282:z 283:u 284:x1 285:x2 286:y 287:–c 288:–b 289:ax2 300, 320, 360, 380, 420, 440, 530, 540, 1120, 1140, 1190, 1220, 1240, 1020, 1050: Simulink models 340: Variable Delay 400: Simulink simulation model 462: Resonator 464: Block 522: Frequency shift 524: Actual Feedback Processing 570, 646, 980, 1104: Phase shifters 572: Filter Block 576: Negative Feedback Gain 582: Quadrature downconversion and sampling analog-to-digital converter 584: Quadrature Digital-to-Analog Converter and Upconversion 642: Surface Acoustic Wave Filter 648: Orthogonal Analog-to-Digital Converter 650: Complex scaling factor 652: Frequency upscaling conversion, frequency upscaling conversion 654: Sampling and Storage 656: Post-processing 658, 942: Switches 660: Extreme Point 772: Receiver Input 774: Sub-circuit block 780: Summation Block, Adder 784: Intra-band interference and noise signals 786: Digital bandpass filter 842: Loop tap point, tap point 844: Upstream Noise 846: Downstream Noise 850: Downstream Components 852: Downstream tap point 872: Cascaded Sparse Integral Filter 876: Numerical Controller Oscillator 878: Data Symbol Related 880: Downclocking conversion, direct sampling high gigabit / s architecture 882, 912: Low-pass filters 892: Signal source input 894: Filter Component Network 896: Sampling device, analog-to-digital converter 906, 908: Line 910: Local Oscillator 920: Binary Phase Shift Keying Receiver 922: Signal 924: Carrier Tracking 926: Time Pulse 928: Data Output 929: Sampling and Holding 932: Input Quantization 934: Foam Error Correction 936: Digital Encoding 940: Multistage circuit 944: Holding Capacitor 946: Pulse stretcher 948: Clock switch signal 970: Variable bandpass frequency Δ-Σ modulation 974: Negative feedback outer loop, feedback loop, negative feedback loop 1042: Discrete filter transfer function; low-noise amplifier 1072: Positive Feedback Gain 1082: Bandpass Filter for Digital Signal Processing 1084: Scaling Block 1100: Positive feedback loop, feedback loop 1102: Positive Gain Block 1110: Continuous-time loop 1112: Transfer function block 1172: Integrator 1272: Input tap for transmitting digital signals 1274: Transmission output tap point 1281: T / R switch 1282: Down-conversion 1283: Low-noise amplifier 1284: Anti-aliasing low-pass filter 1286: Upconversion 1290: Active RF Feedback 1304: Dual parallel loop processing feedback processing 1306: Combined Block

Claims

1. A signal processing circuit comprising: a first signal loop including a first signal processing block and a first feedback path extending around the first signal processing block, the first signal processing block having a frequency dependence that causes the first signal loop to generate a passband; a second signal processing block downstream of the first signal loop; and a second feedback path extending from downstream of the second signal processing block upstream of the first signal processing block; wherein, In operation, the first feedback path amplifies one of the signals in the passband, and the second feedback path modulates the signal at one of the outputs downstream of the first signal processing block.

2. The signal processing circuit as described in claim 1, wherein the first feedback path is a positive feedback path, the second feedback path is a negative feedback path, and wherein, The negative feedback path suppresses an internal noise generated downstream of the first signal processing block.

3. The signal processing circuit as described in claim 1, wherein the first signal processing block includes a resonator.

4. The signal processing circuit as claimed in claim 3, wherein one center frequency, one frequency selectivity, or both a center frequency and a frequency selectivity of the resonator are tunable.

5. The signal processing circuit as described in claim 4, further comprising an adjustable scaling block in the first feedback path, the second feedback path, or both the first feedback path and the second feedback path.

6. The signal processing circuit as claimed in claim 3, wherein the second signal processing block applies a first domain transform, and the second feedback path includes a third processing block applying a second domain transform, the second domain transform being the inverse of the first domain transform.

7. The signal processing circuit as claimed in claim 6, wherein the second signal processing block includes an analog-to-digital converter (ADC) and the third processing block includes a digital-to-analog converter (DAC).

8. The signal processing circuit as described in claim 7, wherein the internal noise includes quantization noise from the ADC.

9. The signal processing circuit as claimed in claim 7, further comprising a digital signal processor for regulating one of the signals in the second feedback path.

10. The signal processing circuitry as described in claim 7, wherein one output of the ADC is connected to a digital signal processor as a receiving channel of a software-defined radio.

11. The signal processing circuit as claimed in claim 1, wherein the first processing block, the second processing block, or both the first processing block and the second processing block include at least one phase control element.

12. The signal processing circuit as described in claim 3, comprising a plurality of bandpass filters connected in series, each bandpass filter comprising a corresponding first feedback path.

13. The signal processing circuit as claimed in claim 12, comprising one or more further second feedback paths connected in parallel downstream of the second signal processing block between adjacent bandpass filters of the plurality of bandpass filters.

14. The signal processing circuit as claimed in claim 13, wherein the first feedback path is a positive feedback path, the second feedback path is a negative feedback path, and the signal processing circuit further includes a controller programmed with instructions to adjust a positive gain block of the positive feedback path to cause the bandpass filter to self-oscillate, and then adjust a negative gain block of the negative feedback path to stabilize the bandpass filter.

15. The signal processing circuit as described in claim 1, wherein the second signal processing block is controlled by a controller.

16. The signal processing circuit as claimed in claim 1, wherein the first signal processing block includes an acoustic resonator and an adjustable phase control element.

17. The signal processing circuit as claimed in claim 1, wherein the first signal processing block includes a plurality of acoustic filters and a switch for selecting one of the plurality of acoustic filters.

18. The signal processing circuit as claimed in claim 1, including a signal input upstream of the first signal loop.

19. The signal processing circuit as claimed in claim 1, comprising a signal input between the first signal processing block and the second signal processing block, the second feedback path comprising a negative gain block.

20. A method of processing a signal using a signal processing circuit, the signal processing circuit including a first signal loop, the first signal loop including a first signal processing block and a first feedback path extending around the first signal processing block, such that the first signal loop includes a passband, a second signal processing block downstream of the bandpass filter, and a second feedback path extending from downstream of the signal processing block to upstream of the first signal processing block, the method comprising the steps of: causing the first signal loop to generate a filtered signal in the passband; processing the filtered signal using the second signal processing block downstream of the bandpass filter, such that an output signal is adjusted at an output downstream of the bandpass filter.

21. The method as described in claim 20, wherein the first feedback path is a positive feedback path, the second feedback path is a negative feedback path, and wherein adjusting the output signal includes suppressing an internal noise generated downstream of the first signal processing block.

22. The method as described in claim 21, wherein the second signal processing block applies a domain transform, and the negative feedback path includes a third processing block applying a second domain transform, the second domain transform being the inverse of the first domain transform.

23. The method as described in claim 22, wherein the second signal processing block is an analog-to-digital converter (ADC) and the third processing block includes a digital-to-analog converter (DAC).

24. The method as described in claim 23, wherein the internal noise includes quantization noise from the ADC.

25. The method as described in claim 20, further comprising the steps of adjusting the gain of one of the positive feedback paths to induce self-oscillation of the bandpass filter, and then adjusting the gain of one of the negative feedback paths to stabilize the bandpass filter.

26. The method of claim 20, wherein generating a filtered signal and adjusting the output signal comprises: controlling a gain factor, a phase, or the gain factor and the phase of each of the first feedback path and the second feedback path.

27. The method of claim 20, wherein the first signal processing block includes a bandpass filter, and the method further includes the steps of tuning a center frequency, a frequency selectivity, or both a center frequency and a frequency selectivity of the bandpass filter.

28. The method as described in claim 20, comprising a plurality of bandpass filters connected in series, each bandpass filter comprising a corresponding feedback path.

29. The method as described in claim 28, comprising a plurality of negative feedback paths connected in parallel from downstream of the signal processing block to upstream of the plurality of bandpass filters and between adjacent bandpass filters.

30. A receiving module for a digital communication device, the receiving module comprising: a bandpass filter having a passband; an analog-to-digital converter (ADC) downstream of the bandpass filter, the ADC having an output connected to a processor of the digital communication device; a positive feedback path extending from between the bandpass filter and a signal processing block to an upstream position of the bandpass filter; and a negative feedback path extending from downstream of the signal processing block to upstream of the bandpass filter, the negative feedback path including a digital-to-analog converter (DAC); wherein, In operation, the positive feedback path amplifies the signal in the passband, while the negative feedback path suppresses internal noise generated downstream of the bandpass filter.

31. The receiving module as described in claim 30, wherein the digital communication device includes a software-defined radio.

32. A signal processing circuit for a digital communication device, comprising: an outer signal loop including an input, an output, and a conversion block adapted to perform a signal conversion operation on a signal being processed; and an inner signal loop including a tunable bandpass filter, the inner signal loop being nested within the outer signal loop such that the tunable bandpass filter is connected in each of the inner signal loop and the outer signal loop, and the conversion block is connected outside the inner signal loop.

33. The signal processing circuit as described in claim 32, wherein one or more of the center frequency, frequency selectivity, Q factor, or combinations thereof of the bandpass filter are adjustable.

34. The signal processing circuit as described in claim 32, wherein the bandpass filter comprises a plurality of resonator outputs.

35. The signal processing circuit as described in claim 34, wherein the transformation block includes a processor block programmed with instructions to individually control the poles of a transfer function of the external signal loop.

36. The signal processing circuit as claimed in claim 34, wherein the transformation block is adapted to apply a domain shift to at least one of the resonator outputs.

37. The signal processing circuit as described in claim 34, wherein the transformation block receives the plurality of resonator outputs in parallel.

38. The signal processing circuit as described in claim 32, wherein the external signal loop is a negative feedback loop and the internal feedback loop is a positive feedback loop.

39. The signal processing circuit as described in claim 34, wherein the transformation block is in one signal path of the external signal loop or in one feedback path of the external signal loop.

40. The signal processing circuit of claim 32, wherein the inner signal loop includes a positive feedback path and the outer signal loop includes a negative feedback loop, such that the positive feedback path amplifies the signal in the passband and the negative feedback path suppresses an internal noise generated downstream of the bandpass filter.

41. The signal processing circuit as claimed in claim 40, wherein the signal processing block applies a first domain transform, and the negative feedback path includes a second processing block applying a second domain transform, the second domain transform being the inverse of the first domain transform.

42. The signal processing circuit as claimed in claim 41, wherein the signal processing block includes an analog-to-digital converter (ADC) and the second processing block includes a digital-to-analog converter (DAC).

43. The signal processing circuit as described in claim 42, wherein the internal noise includes quantization noise from the ADC.

44. The signal processing circuit as described in claim 42, further comprising a digital signal processor that modulates one of the signals in the negative feedback path.

45. The signal processing circuit as described in claim 32, wherein the external signal loop includes an output connected to a transmission device.

46. ​​The signal processing circuit as claimed in claim 32, wherein the inner signal loop includes an input upstream of the outer signal loop of the tunable bandpass filter, the outer signal loop being connected to a receiving device.

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