Cooling cover, packaged semiconductor devices including the same, and method of cooling packaged semiconductor devices

Abstract

A cooling cover comprising a trapezoidal cooling chamber for cooling a semiconductor device and a method thereof are disclosed. In one embodiment, the cooling cover for the semiconductor device includes an inlet; an outlet; and a cooling chamber in fluid communication with the inlet and the outlet, the cooling chamber having a trapezoidal shape in a cross-sectional view.

Description

Technical Field

[0001] The embodiments of the present invention relate to a cooling cap, a packaged semiconductor device including the same, and a method for cooling the packaged semiconductor device. Prior Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. In most cases, this increase in integration density is due to iterative reductions in the minimum feature size, allowing more components to be integrated into a given area. As the demand for miniaturized electronic devices continues to grow, smaller semiconductor die packaging technologies have emerged.

[0003] With the further development of semiconductor technology, stacked and bonded semiconductor devices have become an effective alternative to further reduce the physical size of semiconductor devices. In stacked semiconductor devices, active circuits such as logic, memory, and processor circuits are at least partially fabricated on separate substrates and then physically and electrically bonded together to form a functional device. This bonding process utilizes complex technologies and requires improvement. Summary of the Invention

[0004] This invention provides a cooling cover for a semiconductor device, comprising: an inlet; an outlet; and a cooling chamber in fluid communication with the inlet and the outlet, the cooling chamber having a trapezoidal shape in a cross-sectional view.

[0005] This invention provides a packaged semiconductor device including a cooling cap, comprising: a packaged semiconductor device including a first integrated circuit wafer, the first integrated circuit wafer including a plurality of channels located on the back side of the first integrated circuit wafer; and a cooling cap located on the packaged semiconductor device, wherein the cooling cap includes: a cooling chamber located on the first integrated circuit wafer; and a gasket surrounding the cooling chamber and contacting the packaged semiconductor device.

[0006] This invention provides a method for cooling a packaged semiconductor device, comprising: providing the packaged semiconductor device; attaching a cooling cap to the packaged semiconductor device; and allowing a liquid coolant to flow through the cooling cap, wherein the cooling cap is configured to increase the flow rate of the liquid coolant as the liquid coolant moves across the surface of the packaged semiconductor device. Simple Explanation of the Diagram

[0007] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figures 1A and 1B show perspective and cross-sectional views of a cooling cover according to some embodiments, respectively.

[0009] Figures 2 to 13 show cross-sectional and top views of intermediate stages in the manufacturing of the packaging structure according to some embodiments.

[0010] Figures 14A to 14D show cross-sectional views of a package structure including a cooling cover according to some embodiments. Implementation

[0011] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, embodiments in which a first feature is formed on or on a second feature may include those where the first and second features are in direct contact, and embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, this disclosure may repeat reference numerals and / or letters in various instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments or configurations discussed.

[0012] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," and similar terms may be used in the text to describe the relationship between one element or feature and another, as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0013] Various embodiments provide a cooling cap, a method for manufacturing the cooling cap, a packaged semiconductor device including the cooling cap, and a method for manufacturing the packaged semiconductor device. The packaged semiconductor device may include one or more wafers with channels formed on their back sides. The cooling cap can directly supply liquid coolant to the channels. Therefore, the cooling cap provides direct cooling to the wafer, thereby improving heat transfer between the wafer and the liquid coolant. The cooling cap includes a cooling chamber through which the liquid coolant flows over the back side of the wafer. The cooling chamber is inclined relative to the surface of the wafer such that the height of the cooling chamber at its inlet above the wafer is greater than the height of the cooling chamber at its outlet above the wafer. This causes the flow rate of liquid cooling (e.g., mass flux) to increase as the liquid coolant flows over the back side of the wafer. This improves the uniformity of cooling provided on the back side of the wafer. Therefore, the cooling cap can provide improved heat transfer from the wafer to the liquid coolant, even wafer cooling, improved device performance, and reduced device defects caused by wafer overheating.

[0014] The embodiments will be described for a specific context, namely a die-interpolator substrate stacked package using chip-on-wafer-on-substrate (CoWoS) processing. However, in some embodiments, the liquid cooling cap may be applied to other types of packages, such as die-on-die-substrate stacked packages, system-on-integrated-chip (SoIC) device packages, integrated fan-out (InFO) packages, and / or other types of semiconductor packages.

[0015] Figures 1A and 1B show a perspective view and a cross-sectional view of a cooling cap 200 according to some embodiments, respectively. The cooling cap 200 can be configured to contact the back side of a semiconductor device and can supply liquid coolant to the back side of the semiconductor device to cool the semiconductor device. As shown in Figures 1A and 1B, the cooling cap 200 includes a cap body 202, an inlet 204, an inlet distributor 206, a cooling chamber 208, an outlet collector 210, and an outlet 212. Liquid coolant is supplied through the inlet 204, flows through the inlet distributor 206 and into the cooling chamber 208, flows through the cooling chamber 208 and across the back side of the semiconductor device, converges through the outlet collector 210, and flows out of the outlet 212.

[0016] As shown in Figures 1A and 1B, the cooling chamber 208 has a trapezoidal shape in cross-sectional views. In some embodiments, the cooling chamber 208 may have different shapes, but may taper gradually from the inlet 204 to the outlet 212. The cooling chamber 208 tapers gradually from an inlet height HI adjacent to the inlet distributor 206 to an outlet height HO adjacent to the outlet collector 210. The inlet height HI may range from about 10 μm to about 2000 μm, the outlet height HO may range from about 20 μm to about 1000 μm, and the ratio of the inlet height HI to the outlet height HO is in the range of about 1 to about 50. The area of ​​the cooling chamber 208 may vary based on the semiconductor device to be cooled by the cooling cover 200. Forming a cooling chamber 208 with a prescribed height and shape results in an increase in the flow rate (e.g., mass flux) of the liquid coolant as it flows through the cooling chamber 208 from the inlet distributor 206 to the outlet collector 210 across the back of the semiconductor device. As the liquid coolant flows through the cooling chamber 208, its temperature rises, which reduces heat transfer to the liquid coolant. However, increasing the flow rate of the liquid coolant increases heat transfer to the liquid coolant. Therefore, forming the cooling chamber 208 with a specified height and shape ensures that heat transfer to the liquid coolant is uniform across the back of the semiconductor device. This allows for improved device performance and reduced device defects caused by overheating in the semiconductor device.

[0017] Channel 216 is formed in cooling cap 200, and gasket 220 is disposed in channel 216. In some embodiments, an adhesive may be provided in the channel to attach cooling cap 200 to semiconductor device. Channel 216 may be formed in cooling cap 200 by molding process, machining process, etc. Gasket 220 may be an O-ring or the like and may be formed of polytetrafluoroethylene (PTFE), nitrile, fluoropolymer, ethylene propylene diene monomer (EPDM) rubber, etc. Cooling cap 200 is configured to be placed directly against the back of semiconductor device, such that cooling chamber is adjacent to the back of semiconductor device. When liquid coolant flows across the back of semiconductor device, gasket 220 is included in cooling chamber 208 to contain liquid coolant. In some embodiments, liquid coolant may flow outside cooling chamber 208 but may be contained within gasket 220. Channel 216 and the gasket 220 / adhesive disposed within channel 216 surround cooling chamber 208 to prevent liquid coolant from overflowing from cooling chamber 208 when cooling chamber 200 is used to cool semiconductor devices. Placing cooling cap 200 directly adjacent to the back of the semiconductor device provides improved heat transfer from the semiconductor device to the liquid coolant. For example, heat transfer from the semiconductor device can be greater than about 5 W / mm², and can be improved by about 60% compared to conventional cooling structures. This allows for improved device performance and reduced device defects caused by overheating in the semiconductor device. Placing cooling cap 200 directly near the back of the semiconductor device also allows for the omission of other structures, such as thermal interface material (TIM), caps, etc., which reduces costs.

[0018] The cover body 202 can be formed as a single piece of material or as several parts combined together. The cover body 202 can be a solid piece, in which the inlet 204, inlet distributor 206, cooling chamber 208, outlet collector 210, and outlet 212 are formed. Alternatively, it can be a hollow piece. In some embodiments, each of the inlet 204, inlet distributor 206, cooling chamber 208, outlet collector 210, and outlet 212 can be machined in the cover body 202, for example, by a precision machine. In some embodiments, the cover body 202 can be formed by a molding process, such as injection molding, compression molding, etc. A combination of molding and machining processes can be used to form the cover body 202. The cover body 202 can be formed of a conductive material, such as a metal like aluminum or copper. The cover body 202 can be formed of a plastic or other polymer, such as polyethylene, polyvinyl chloride, acrylate polymers, etc. The cover body 202 can be formed of a ceramic material. The cover body 202 can be formed of a material inert to the liquid coolant. In some embodiments, the liquid coolant may include water; a solution of ethylene glycol, diethylene glycol, propylene glycol, etc.; oil; a dielectric liquid; a combination thereof; or the like.

[0019] Figure 2 shows a cross-sectional view of an integrated circuit die 50, which can be disposed in a semiconductor device for cooling by a cooling cap 200. The integrated circuit die 50 will be packaged in a subsequent process to form an integrated circuit package. The integrated circuit die 50 may be a logic die (e.g., a central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.); a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.); a power management chip (e.g., a power management integrated circuit (PMIC) chip); a radio frequency (RF) chip; a sensor chip; a micro-electro-mechanical system (MEMS) chip; a signal processing chip (e.g., a digital signal processing (DSP) chip); a front-end die (e.g., an analog front-end (AFE) die); or a combination thereof.

[0020] Integrated circuit die 50 can be formed in a wafer, which may include different device regions that are monolithized in subsequent steps to form multiple integrated circuit dies. The integrated circuit die 50 can be processed according to applicable manufacturing processes to form integrated circuits. In some embodiments, the integrated circuit die 50 includes a semiconductor substrate 52, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may be used. The semiconductor substrate 52 has an active surface (e.g., the upward-facing surface in FIG. 2), sometimes referred to as the front side, and a passive surface (e.g., the downward-facing surface in FIG. 2), sometimes referred to as the back side.

[0021] Device 54 (represented by a transistor) may be formed on the front side of semiconductor substrate 52. Device 54 may be an active device (e.g., a transistor, diode, etc.), capacitor, resistor, etc. Interlayer dielectric (ILD) 56 is located on the front side of semiconductor substrate 52. ILD 56 surrounds and may cover device 54. ILD 56 may include one or more materials such as phosphosilicate glass (PSG), boro-silicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0022] A conductive plug 58 extends through the ILD 56 and is electrically and physically coupled to the device 54. In embodiments where the device 54 is a transistor, the conductive plug 58 may be coupled to the gate and source / drain regions (e.g., source and / or drain regions) of the transistor. The conductive plug 58 may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, or combinations thereof. An interconnect structure 60 is formed on the ILD 56 and the conductive plug 58. The interconnect structure 60 interconnects the device 54 to form an integrated circuit. In some embodiments, the interconnect structure 60 may be formed by a metallization pattern in a dielectric layer on the ILD 56. The metallization pattern includes metal lines and vias formed in one or more low-k dielectric layers. The metallization pattern of the interconnect structure 60 is electrically coupled to the device 54 through the conductive plug 58.

[0023] The integrated circuit die 50 also includes a pad 62, such as an aluminum pad, externally connected to the pad 62. The pad 62 is on the front side of the semiconductor substrate 52, for example, in and / or on the interconnect structure 60. Solder areas (e.g., solder balls or solder bumps) may be disposed on the pad 62. The solder areas can be used to perform chip probe (CP) testing on the integrated circuit die 50. The CP test can be performed on the integrated circuit die 50 to determine whether the integrated circuit die 50 is a known good die (KGD). Therefore, only integrated circuit dies 50 that are KGDs undergo subsequent processing and are packaged. Dies that fail the CP test are not packaged. After testing, the solder areas can be removed in subsequent processing steps.

[0024] One or more passivation films 64 are present on the integrated circuit die 50, for example, on portions of the interconnect structure 60 and pad 62. Openings are formed through the passivation films 64 extending into the pads 62. Die connectors 66, such as conductive pillars (e.g., formed of a metal such as copper), are formed in the openings extending through the passivation films 64. The die connectors 66 can be physically and electrically coupled to various pads 62. The die connectors 66 can be formed by means of electroplating, etc. The die connectors 66 are electrically coupled to the integrated circuit of the integrated circuit die 50.

[0025] The dielectric layer 68 may or may not be on the front side of the semiconductor substrate 52, for example, on the passivation film 64 and around the die connector 66. The dielectric layer 68 laterally encapsulates the die connector 66 and is laterally connected to the semiconductor substrate 52. The dielectric layer 68 may be a polymer, such as PBO, polyimide, BCB, etc.; a nitride, such as silicon nitride, etc.; an oxide, such as silicon oxide, PSG, BSG, BPSG, etc.; or a combination thereof. The dielectric layer 68 may be formed by spin coating, lamination, chemical vapor deposition (CVD), etc. Initially, the dielectric layer 68 may bury the die connector 66 such that the uppermost surface of the dielectric layer 68 is above the uppermost surface of the die connector 66. In some embodiments, solder regions may be formed on the die connector 66, and the dielectric layer 68 may bury the solder regions. In some embodiments, the die connector 66 is exposed through the dielectric layer 68 during the formation of the integrated circuit die 50. In some embodiments, the die connector 66 remains buried and is exposed during subsequent processes for packaging the integrated circuit die 50. The die connector 66 can remove any solder areas that may be present on it.

[0026] In some embodiments, the integrated circuit die 50 is a stacked device comprising a plurality of semiconductor substrates 52. For example, the integrated circuit die 50 may be a memory device, such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, etc., comprising a plurality of memory dies. In such embodiments, the integrated circuit die 50 comprises a plurality of semiconductor substrates 52 interconnected via through-substrate vias (TSVs). Each semiconductor substrate 52 may (or may not) have an interconnect structure 60.

[0027] Figures 3 through 12 are cross-sectional views of intermediate stages in the fabrication of an integrated circuit package 160 (see Figure 12) according to some embodiments. Specifically, the integrated circuit package 160 is formed by bonding an integrated circuit die 50 to a wafer 100 (see Figure 3). In some embodiments, the integrated circuit package 160 is a chip-on-wafer (CoW) package, but it should be understood that the embodiments can be applied to other three-dimensional integrated circuit (3DIC) packages. The integrated circuit package 160 can be mounted to a substrate 150. In some embodiments, the resulting package is a wafer-on-wafer (CoWoS) package (shown in Figure 13), although it should be understood that the embodiments can be applied to other 3DIC packages.

[0028] The processing of the two packaging regions of wafer 100, the first packaging region 100A and the second packaging region 100B, is shown in the subsequent cross-sectional view, and the processing of the four packaging regions of wafer 100, the first packaging region 100A, the second packaging region 100B, the third packaging region 100C, and the fourth packaging region 100D, is shown in the subsequent top view. It should be understood that any number of packaging regions of wafer 100 can be processed simultaneously and monolithically to form multiple integrated circuit packages 160 from the monolithized portions of wafer 100.

[0029] In Figure 3, wafer 100 is obtained or formed. Wafer 100 includes devices in multiple package regions, such as the first package region 100A and the second package region 100B shown in Figure 3. Each of package regions 100A-100B will be monolithized in a subsequent process to be included in an integrated circuit package 160 (as shown in Figure 12). Wafer 100 can be monolithized to form interposers, integrated circuit dies, etc. In some embodiments, wafer 100 may include a substrate 102, interconnect structures 106, and conductive vias 104.

[0030] The substrate 102 may be a semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multilayer semiconductor substrate, etc. The substrate 102 may include semiconductor materials such as silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The substrate 102 may be doped or undoped. In some embodiments, the substrate 102 has no active devices, although the substrate 102 may include passive devices formed in and / or on the front surface of the substrate 102. The substrate 102 (e.g., the downward-facing surface in FIG. 2) is sometimes referred to as the front side. In embodiments where an integrated circuit device is formed in the substrate 102, active devices such as transistors and diodes, as well as passive devices such as capacitors and resistors, may be formed in the substrate 102 and / or on the front side of the substrate 102.

[0031] An interconnect structure 106 is located above the front side of the substrate 102 and is used for electrically connecting devices on the substrate 102 (if any). The interconnect structure 106 may include one or more dielectric layers 108 and one or more metallization layers 110 within the dielectric layers 108. Acceptable dielectric materials for the dielectric layers 108 include oxides (e.g., silicon oxide or aluminum oxide); nitrides (e.g., silicon nitride); carbides (e.g., silicon carbide); the like; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, etc. Other dielectric materials may also be used, such as polymers, which may include polybenzoxazole (PBO), polyimide, benzocyclobuten-based polymers (BCB), etc. The metallization layers 110 may include conductive vias and / or conductive lines to interconnect devices on the substrate 102 and / or external devices together. The metallization layer 110 can be formed of a conductive material such as a metal, which may include copper, cobalt, aluminum, gold, or combinations thereof. The interconnect structure 106 can be formed by a damascene process, such as a single damascene process or a dual damascene process.

[0032] Conductive vias 104 extend into interconnect structures 106 and / or substrates 102. Conductive vias 104 are electrically coupled to a metallization layer 110 of interconnect structure 106. In some embodiments, conductive vias 104 can be formed by forming grooves in interconnect structure 106. Interconnect structure 106 and / or substrate 102 are fabricated using etching, milling, laser technology, combinations thereof, etc. Thin dielectric materials can be formed in the grooves, for example, by using oxidation techniques. Thin barrier layers can be conformally deposited in the grooves, for example, by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, combinations thereof, and / or similar methods. The barrier layer can be formed of oxides, nitrides, carbides, combinations thereof, etc. Conductive materials can be deposited over the barrier layer and in the grooves. Conductive materials can be formed by electrochemical plating processes, CVD, ALD, PVD, combinations thereof, etc. Examples of conductive materials include copper, tungsten, aluminum, silver, gold, combinations thereof, etc. Excess conductive material and barrier layer material can be removed from the surface of interconnect structure 106 and / or substrate 102 through planarization processes such as chemical mechanical polishing (CMP), grinding processes, and etch-back processes. The remaining portion of the barrier layer and conductive material form conductive vias 104.

[0033] Bonding pad 112 is formed on metallization layer 110, and dielectric layer 108 and conductive connector 114 of interconnect structure 106 are formed on bonding pad 112. Bonding pad 112 can be formed by forming a seed layer (not shown separately) on metallization layer 110 and dielectric layer 108. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using PVD or the like. A photoresist is formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and can be exposed to be patterned. The pattern of the photoresist corresponds to bonding pad 112. Patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by electroplating, such as electroplating or electroless plating. The conductive material may include metals, such as copper, titanium, tungsten, aluminum, etc. Remove the photoresist and the seed layer portion where no conductive material forms. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, remove the exposed portion of the seed layer using an acceptable etching process. The remaining portion of the seed layer and the conductive material form bonding pad 112.

[0034] Conductive connectors 114 are formed on bonding pads 112. Conductive connectors 114 can be ball grid array (BGA) connectors, solder balls, controlled collapse chip connection (C4) bumps, microbumps, or bumps formed using an electroless nickel-electroless palladium-immersion gold technique (ENEPIG). Conductive connectors 114 can be formed from reflow-solderable conductive materials, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof. In some embodiments, conductive connectors 114 are formed by initially evaporating, electroplating, printing, solder transfer, ball placement, etc., to form a solder layer. Once the solder layer is structurally formed, reflow soldering can be performed to shape the material into the desired bump shape.

[0035] In Figures 4A and 4B, integrated circuit dies 50 (e.g., first integrated circuit die 50A and multiple second integrated circuit dies 50B) are attached to wafer 100. The desired type and number of integrated circuit dies 50 are attached to package regions. In the illustrated embodiment, multiple integrated circuit dies 50 are placed adjacent to each other in each package region, including first integrated circuit dies 50A and second integrated circuit dies 50B. The first integrated circuit dies 50A in each package region are located between the second integrated circuit dies 50B. As shown in Figure 4B, one of the first integrated circuit dies 50A and four of the second integrated circuit dies 50B can be coupled in each package region 100A-100D. However, any number of first integrated circuit dies 50A and second integrated circuit dies 50B can be formed in each of the package regions 100A-100D. The first integrated circuit die 50A can have a different function than the second integrated circuit dies 50B. For example, in some embodiments, the first integrated circuit die 50A may be a logic device, such as a CPU, GPU, SoC, microcontroller, etc. The second integrated circuit die 50B may be a memory device, such as a DRAM die, SRAM die, HMC module, HBM module, etc. The first integrated circuit die 50A and the second integrated circuit die 50B may be formed in the same technology node process or in different technology node processes. For example, the first integrated circuit die 50A may be formed using a process at a more advanced process node than the second integrated circuit die 50B.

[0036] In the illustrated embodiment, the integrated circuit die 50 is attached to the wafer 100 via solder bonding (e.g., via conductive connector 114). The integrated circuit die 50 can be placed on the interconnect structure 106 using a pick-and-place tool. Attaching the integrated circuit die 50 to the wafer 100 may include placing the integrated circuit die 50 on the wafer 100 and reflow soldering the conductive connector 114. The conductive connector 114 forms a joint between the bonding pad 112 of the wafer 100 and the die connector 66 of the integrated circuit die 50, physically and electrically coupling the integrated circuit die 50 to the wafer 100.

[0037] In Figure 5, underfill 122 may be formed around the conductive connector 114 and between the wafer 100 and the integrated circuit die 50. Underfill 122 can reduce stress and protect the joints created by reflow soldering of the conductive connector 114. Underfill 122 may be formed of an underfill material such as molding compound, epoxy resin, etc. Underfill 122 may be formed by a capillary flow process after the integrated circuit die 50 is attached to the wafer 100, or it may be formed by a suitable deposition method before the integrated circuit die 50 is attached to the wafer 100. Underfill 122 may be applied in liquid or semi-liquid form and subsequently cured. In some embodiments, underfill 122 may extend at least partially upwards onto the side surfaces of the integrated circuit die 50. Although underfill 122 is shown as having straight side surfaces, underfill 122 may have curved side surfaces.

[0038] In some embodiments, the integrated circuit die 50 is attached to the wafer 100 by direct bonding. For example, hybrid bonding, fusion bonding, dielectric bonding, metallic bonding, etc., can be used to directly bond the corresponding dielectric layers, bonding pads, and / or die connections of the wafer 100 and the integrated circuit die 50 without the use of adhesives or solder. In embodiments where the integrated circuit die 50 is attached to the wafer 100 using direct bonding, the underfill 122 can be omitted.

[0039] In Figure 6, an encapsulation 124 is formed on wafer 100 and integrated circuit die 50. After formation, the encapsulation 124 seals the first integrated circuit die 50A, the second integrated circuit die 50B, and the underfill 122. The encapsulation 124 can be a molding compound, epoxy resin, etc. The encapsulation 124 can be applied by compression molding, transfer molding, etc., and can be formed on wafer 100 such that the first integrated circuit die 50A and / or the second integrated circuit die 50B are buried or covered. The encapsulation 124 can be further formed in the gap region between the first integrated circuit die 50A and / or the second integrated circuit die 50B. The encapsulation 124 can be applied in liquid or semi-liquid form and subsequently cured.

[0040] In Figure 7, a planarization process is performed on the encapsulation 124 to expose the first integrated circuit die 50A and the second integrated circuit die 50B. The planarization process may also remove material from the first integrated circuit die 50A and / or the second integrated circuit die 50B until the first integrated circuit die 50A and the second integrated circuit die 50B are exposed. Within a range of process variations, after the planarization process, the top surfaces of the first integrated circuit die 50A, the second integrated circuit die 50B, and the encapsulation 124 may be substantially coplanar (e.g., horizontal). The planarization process may be CMP, polishing, etch-back, or a combination thereof. In some embodiments, for example, if the first integrated circuit die 50A and / or the second integrated circuit die 50B have already been exposed, planarization may be omitted.

[0041] In Figures 8A to 8H, channels are formed on the back side of integrated circuit die 50 and / or encapsulation 124. In Figures 8A to 8D and 8G, channel 140 is formed on the back side of the first integrated circuit die 50A. In Figures 8E and 8F, channels 140 and 142 are formed on the back side of the first integrated circuit die 50A and the second integrated circuit die 50B, respectively. In Figure 8H, channels 140 and 142 are formed on the back side of the first integrated circuit die 50A, the second integrated circuit die 50B, and encapsulation 124.

[0042] Channels 140 and / or 142 can be formed by suitable methods. In some embodiments, channels 140 and 142 can be formed by mechanical processes, such as mechanical die sawing. Channels 140 and 142 can be formed by laser cutting, etc. Channels 140 and 142 can be formed by acceptable photolithography and etching techniques. In some embodiments, the etching technique can include isotropic etching, such as wet etching, etc. In some embodiments, the etchant used to form channels 140 and 142 can include potassium hydroxide (KOH). Channels 140 and 142 can have a width ranging from about 10 μm to about 3000 μm, a depth ranging from about 10 μm to about 700 μm, and a spacing ranging from about 15 μm to about 5000 μm. The shape of channels 140 and 142 can be controlled by controlling the parameters of the method used to form channels 140 and 142. In embodiments where channels 140 and 142 are formed using a mechanical die saw, suitable blades can be selected to control the shape of channels 140 and 142. Channels 140 and 142 can be rectangular, U-shaped, V-shaped, etc., and can gradually taper in the direction facing the front of the first integrated circuit die 50A and the second integrated circuit die 50B.

[0043] In Figures 8A and 8B, channel 140 is disposed on the back side of the first integrated circuit die 50A, and the second integrated circuit die 50B and the encapsulation 124 do not have channels 140 and 142. Each channel 140 may be parallel to each other. Channel 140 may extend to the opposite edges of the first integrated circuit die 50A perpendicular to the longitudinal axis of channel 140. Channel 140 may be spaced apart from the opposite edges of the first integrated circuit die 50A parallel to the longitudinal axis of channel 140. Although five channels 140 are shown to be formed in each first integrated circuit die 50A, more or fewer channels 140 may be formed in each first integrated circuit die 50A. For ease of illustration, the embodiments of Figures 8A and 8B are illustrated in the following figures.

[0044] In Figures 8C and 8D, channel 140 is disposed on the back side of the first integrated circuit die 50A, and the second integrated circuit die 50B and the encapsulation 124 do not have channels 140 and 142. Channel 140 is perpendicular to the channel 140 shown in Figures 8A and 8B. Channel 140 may be spaced apart from the opposite edges of the first integrated circuit die 50A perpendicular to the longitudinal axis of channel 140. Channel 140 may also be spaced apart from the opposite edges of the first integrated circuit die 50A parallel to the longitudinal axis of channel 140. Although five channels 140 are shown to be formed in each first integrated circuit die 50A, more or fewer channels 140 may be formed in each first integrated circuit die 50A.

[0045] In Figures 8E and 8F, channel 140 is provided on the back side of the first integrated circuit die 50A, channel 142 is provided on the back side of the second integrated circuit die 50B, and the encapsulation 124 does not have channels 140 and 142. Channels 140 and 142 may be parallel to each other. However, in some embodiments, channels 140 may be parallel to each other, channels 142 may be parallel to each other, and channel 140 may be perpendicular to channel 142. Channel 140 may extend perpendicularly to the longitudinal axis of channel 140 to the opposite edge of the first integrated circuit die 50A. Channel 140 may be spaced apart from the opposite edge of the first integrated circuit die 50A, which is parallel to the longitudinal axis of channel 140. Channel 142 may extend to the opposite edge of the second integrated circuit die 50A. The integrated circuit die 50B is perpendicular to the longitudinal axis of channel 142. Channel 142 may be spaced apart from the opposite edge of the second integrated circuit die 50B, which is parallel to the longitudinal axis of channel 142. Although five channels 140 are shown to be formed in each of the first integrated circuit die 50A and two channels 142 are shown to be formed in each of the second integrated circuit die 50B, more or fewer channels 140 and channels 142 may be formed in each of the first integrated circuit die 50A and the second integrated circuit die 50B.

[0046] In Figure 8G, channel 140 is disposed on the back side of the first integrated circuit die 50A, and the second integrated circuit die 50B and the encapsulation 124 do not have channels 140 and 142. Channel 140 may be spaced apart from the opposite edges of the first integrated circuit die 50A perpendicular to the longitudinal axis of channel 140. Channel 140 may also be spaced apart from the opposite edges of the first integrated circuit die 50A parallel to the longitudinal axis of channel 140. As shown in Figure 8G, channel 140 may have a shortened length and may be specifically disposed above areas of the first integrated circuit die 50A prone to hot spots. Therefore, channel 140 can be configured to provide additional cooling to areas adjacent to hot spots, which reduces device defects and improves device performance. Although five channels 140 are shown to be formed in each first integrated circuit die 50A, more or fewer channels 140 may be formed in each first integrated circuit die 50A.

[0047] In Figure 8H, channel 140 is disposed on the back side of the first integrated circuit die 50A, and channel 142 is disposed on the back side of the second integrated circuit die 50B and the encapsulation 124. Channels 140 and 142 may be parallel to each other. However, in some embodiments, channels 140 may be parallel to each other, channels 142 may be parallel to each other, and channel 140 may be perpendicular to channel 142. Therefore, channels 140 and 142 may form an intersecting pattern. Channel 140 may extend across the opposite edge of the first integrated circuit die 50A to the opposite edge of the encapsulation 124 perpendicular to the longitudinal axis of channel 140. The longitudinal axis of channel 140 may be spaced apart from the opposite edge of the first integrated circuit die 50A parallel to channel 140. Channel 142 may extend across the opposite edge of the second integrated circuit die 50B to the opposite edge of the encapsulation 124 perpendicular to the longitudinal axis of channel 142. Channels 142 may be spaced apart from each other. The second integrated circuit die 50B is parallel to the longitudinal axis of the channel 142. Although five channels 140 are shown to be formed in each of the first integrated circuit die 50A, and two channels 142 are shown to be formed in each of the second integrated circuit die 50B, more or fewer channels 140 and channels 142 may be formed in each of the first integrated circuit die 50A and the second integrated circuit die 50B.

[0048] A cooling cap (e.g., cooling cap 200, shown in Figures 1A and 1B and discussed with reference to Figure 1B) may subsequently be attached to the first integrated circuit die 50A, the second integrated circuit die 50B, and the encapsulation 124. The cooling cap may be configured to allow liquid coolant to flow directly across the back surface of the first integrated circuit die 50A, the back surface of the second integrated circuit die 50B, and / or the surface of the encapsulation 124. The cooling cap may be configured to allow liquid coolant to flow across the surfaces of the first integrated circuit die 50A, the second integrated circuit die 50B, and / or the encapsulation 124 in a direction parallel or perpendicular to the longitudinal axis of channels 140 and / or 142. Channels 140 and 142 provided in the back surface of the first integrated circuit die 50A and / or the second integrated circuit die 50B improve heat transfer from the first integrated circuit die 50A and / or the second integrated circuit die 50B to the liquid coolant. For example, the heat transfer from the first integrated circuit die 50A and / or the second integrated circuit die 50B can be greater than about 5 W / mm², and can be improved by about 60% compared to conventional cooling structures. This allows for improved device performance and reduces device defects caused by overheating in the first integrated circuit die 50A and / or the second integrated circuit die 50B. Providing channels 140 and / or 142 and allowing the liquid coolant to flow directly near the back surface of the first integrated circuit die 50A and / or the second integrated circuit die 50B further allows other structures, such as thermal interface materials (TIM), covers, etc., to be omitted, which reduces costs.

[0049] In Figure 9, the carrier substrate 130 is bonded to the encapsulation 124, the first integrated circuit die 50A, and the second integrated circuit die 50B via a release layer 132. The carrier substrate 130 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 130 may be a wafer, allowing multiple packages to be formed simultaneously on the carrier substrate 130.

[0050] Release layer 132 may be formed of a polymer-based material and may be removed together with the carrier substrate 130 from the overlay structure to be formed in subsequent steps. In some embodiments, release layer 132 is an epoxy-based thermal release material that loses its adhesiveness upon heating, such as a photothermal conversion (LTHC) release coating. In some embodiments, release layer 132 may be a UV adhesive that loses its adhesive properties upon exposure to ultraviolet light. Release layer 132 may be dispensed and cured as a liquid, may be a laminated film laminated onto the carrier substrate 130, or may be the like. In some embodiments, release layer 132 may extend at least partially into channels 140 and / or channel 142; however, in some embodiments, channels 140 and / or channel 142 may be without release layer 132. The top surface of release layer 132 may be horizontal and may have a high degree of flatness. Further, in Figure 9, after the carrier substrate 130 is bonded to the encapsulation 124, the first integrated circuit die 50A and the second integrated circuit die 50B, the device can be flipped so that the back side of the substrate 102 faces upward.

[0051] In Figure 10, substrate 102 is thinned. Thinning can be performed through CMP processes, polishing processes, etch-back processes, or combinations thereof. Thinning is performed on the back surface of substrate 102. Thinning exposes conductive vias 104. After thinning, the surface of conductive via 104 and the back surface of substrate 102 are coplanar (e.g., horizontal) within the process variation. The exposed conductive via 104 can be referred to as a substrate via or a through-silicon via (TSV). After substrate 102 is thinned, conductive via 104 can provide electrical connections through substrate 102.

[0052] In Figure 11, a die connector 134 is formed on the back side of the substrate 102, and a conductive connector 146 is formed on the die connector 134. The die connector 134 can physically contact and be electrically coupled to the conductive via 104. The die connector 134 can be a conductive post, pad, etc., for external connection. The die connector 134 can be formed of a metal such as copper or aluminum, and can be formed by, for example, electroplating. The die connector 134 is electrically connected to devices formed in the substrate 102 and the interconnect structure 106.

[0053] The conductive connector 146 may be a ball grid array (BGA) connector, solder ball, metal pillar, controlled collapse wafer connection (C4) bump, microbump, bump formed by electroless nickel-palladium immersion gold (ENEPIG) technology, or the like. The conductive connector 146 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, the conductive connector 146 is formed by initially evaporating, electroplating, printing, solder transfer, ball placement, etc., to form a solder layer. Once a solder layer is structurally formed, reflow soldering can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 146 includes metal pillars (e.g., copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. In embodiments where the conductive connector includes metal pillars, the metal pillars may be solderless and have substantially vertical sidewalls. In some embodiments, a metal capping layer is formed on top of the metal pillar. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or combinations thereof, and may be formed by an electroplating process.

[0054] In Figure 12, a dicing process is performed by sawing along a scribe line region. For example, a dicing process can be performed by sawing along a scribe line region between package regions 100A-100D (see Figure 8B). The sawing separates the individual integrated circuit packages 160 from each other. The resulting monolithic integrated circuit package 160 can originate from any of package regions 100A-100D. The monolithization process monolithizes the substrate 102 of wafer 100 to form a plurality of substrates 103. The monolithization process can also cut through the encapsulation 124 and the interconnect structure 106. Each integrated circuit package 160 may include a monolithized portion 100 of the wafer (e.g., substrate 103) and an integrated circuit die 50 bonded to the monolithized portion of wafer 100.

[0055] Further, in Figure 12, a carrier substrate peel is performed to separate (or “peel off”) the carrier substrate 130 from the encapsulation 124, the first integrated circuit die 50A, and the second integrated circuit die 50B. In some embodiments, peeling includes projecting light, such as laser or UV light, onto the release layer 132, causing the release layer 132 to decompose under the heat of the light and allowing the carrier substrate 130 to be removed. The carrier substrate 130 peel can be performed before or after the monolithic fabrication process.

[0056] In Figure 13, substrate 150 is coupled to each integrated circuit package 160. Substrate 150 may be made of semiconductor materials such as silicon, germanium, diamond, etc. In some embodiments, compound materials such as germanium silicon, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, germanium silicon carbide, gallium arsenide phosphide, gallium indium phosphide, and combinations thereof may also be used. Alternatively, substrate 150 may be a silicon-on-insulator (SOI) substrate. Typically, an SOI substrate comprises a semiconductor material layer, such as epitaxial silicon, germanium, germanium silicon, SOI, germanium silicon-on-insulator (SGOI), or combinations thereof. In some embodiments, substrate 150 may be based on an insulating core such as a glass fiber reinforced resin core. In some embodiments, the core material may be a glass fiber resin, such as FR4. In some embodiments, the core material may include bismaleimide-triazine (BT) resin, other printed circuit board (PCB) materials, or other thin films. Laminated films such as Ajinomoto build-up film (ABF) or other laminated materials can be used on substrate 150.

[0057] Substrate 150 may include active and passive devices (not shown separately). A wide variety of devices may be included, such as transistors, capacitors, resistors, combinations thereof, etc. Any suitable method may be used to form the devices. Substrate 150 may also include a metallization layer (not shown separately) and conductive vias 156. The metallization layer may be formed over the active and passive devices and is designed to connect the various devices to form a functional circuit. The metallization layer may be formed of alternating layers of dielectric material (e.g., a low-k dielectric material) and conductive material (e.g., copper), wherein the vias interconnect the conductive material layers. The metallization layer may be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.). In some embodiments, substrate 150 is substantially devoid of active and passive devices.

[0058] The substrate 150 may include a bonding pad 152 formed on a first surface of the substrate 150 and a bonding pad 154 formed on a second surface of the substrate 150 opposite to the first surface. The bonding pad 152 may be coupled to a conductive connector 146. In some embodiments, the bonding pads 152 and 154 may be formed by forming grooves (not shown separately) in a dielectric layer (not shown separately) on the first and second sides of the substrate 150. The grooves may be formed to allow the bonding pads 152 and 154 to be embedded in the dielectric layer. In some embodiments, the grooves are omitted and the bonding pads 152 and 154 may be formed on the dielectric layer. In some embodiments, the bonding pads 152 and 154 include a thin seed layer (not shown separately) made of copper, titanium, nickel, gold, palladium, or combinations thereof. The conductive material of the bonding pads 152 and 154 may be deposited on the thin seed layer. The conductive material may be formed by electrochemical plating, electroless plating, CVD, ALD, PVD, or combinations thereof. In one embodiment, the conductive material of bonding pad 152 and bonding pad 154 includes copper, tungsten, aluminum, silver, gold, or combinations thereof.

[0059] In some embodiments, bonding pads 152 and 154 are UBMs comprising three layers of conductive material, such as a titanium layer, a copper layer, and a nickel layer. Other arrangements of materials and layers, such as chromium / chromium-copper alloy / copper / gold, titanium / titanium-tungsten / copper, or copper / nickel / gold, may be used to form any suitable material or layer of materials that can be used for bonding pads 152 and 154 and are fully intended to be included within the scope of this application. In some embodiments, a conductive via 156 extends through the substrate 150 and couples at least one bonding pad 152 to at least one bonding pad 154.

[0060] The substrate 150 can be mechanically and electrically bonded to the integrated circuit package 160 via bonding pads 152, conductive connectors 146, and die connectors 134. The substrate 150 can be placed on the integrated circuit package 160 and a reflow soldering process can be performed to bond the conductive connectors 146 to the die connectors 134 via the conductive connectors 146.

[0061] Underfill 158 can be formed between integrated circuit package 160 and substrate 150, surrounding bonding pad 152, die connector 134, and conductive connector 146. Underfill 158 can reduce stress and protect joints formed by reflow soldering. Underfill 158 can be formed by a capillary flow process after substrate 150 is attached to integrated circuit package 160, or it can be formed by a suitable deposition method before attachment of substrate 150.

[0062] According to some embodiments, in Figures 14A to 14D, a cooling cap 200 is attached to an integrated circuit package 160 and an underlying substrate 150. In the embodiments shown in Figures 14A and 14D, the cooling cap 200 is attached to the integrated circuit package 160 and the underlying substrate 150 by screw-type fasteners 170. In the embodiment shown in Figure 14B, the cooling cap 200 is attached to the integrated circuit package 160 by adhesive 226. In the embodiment shown in Figure 14C, the cooling cap 200 is attached to the integrated circuit package 160 and the substrate 150 by one or more clip-on fasteners 180.

[0063] In the embodiments shown in Figures 14A and 14D, the cooling cap 200 is attached to the integrated circuit package 160 and the substrate 150 via screw-type fasteners 170. The screw-type fasteners 170 may include bolts extending through bolt holes 228 in the cap body 202 and bolt holes 157 in the substrate 150. In some embodiments, such as the one shown in Figure 1A, six bolt holes 228 may be provided in the cap body 202 and six bolt holes 157 may be provided in the substrate 150. However, more or fewer bolt holes 228 / 157 may be provided. The screw-type fasteners 170 may also include fasteners that screw onto the bolts and are tightened to clamp the cooling cap 200 onto the integrated circuit package 160. In some embodiments, the fastener may be a nut screwed onto the bolt.

[0064] In the embodiment shown in Figure 14B, the cooling cap 200 is attached to the integrated circuit package 160 via an adhesive 226. The adhesive 226 may be a thermal interface material (TIM) or other suitable adhesive. In some embodiments, the adhesive 226 may include any suitable adhesive, epoxy resin, die attach film (DAF), etc. The adhesive 226 may be applied in the channel 216, pressure may be applied between the cooling cap and the semiconductor device, and the adhesive 226 may be cured.

[0065] In the embodiment shown in FIG. 14C, the cooling cap 200 is attached to the integrated circuit package 160 and the substrate 150 by a clamp fastener 180. The clamp fastener 180 may be similar to a screw-type fastener 170. For example, the clamp fastener 180 may include a threaded portion, such as a bolt, and a fastener screwed onto the bolt and tightened to clamp the cooling cap 200 onto the integrated circuit package 160. The fastener may include a nut screwed onto the bolt. The clamp fastener 180 may be fastened to the exterior of the cooling cap 200 and the substrate 150 such that no bolt holes are formed in the cooling cap 200 and the substrate 150. At least a portion of the clamp fastener 180 may be disposed outside the periphery of the cooling cap 200 and the substrate 150. The clamp fastener may contact the surface of the cooling cap 200 opposite to the substrate 150 and the surface of the substrate 150 opposite to the cooling cap 200. Two clip fasteners 180 are shown in FIG. 14C as being attached to opposite sides of the cooling cap 200, integrated circuit package 160, and substrate 150; however, in some embodiments, the clip fasteners 180 on opposite sides of the cooling cap 200, integrated circuit package 160, and substrate 150 may be continuous, or any number of clip fasteners 180 may be used to attach the cooling cap 200 to the integrated circuit package 160 and substrate 150.

[0066] In embodiments where the cooling cap 200 is attached to the integrated circuit package 160 and the substrate 150 using screw-type fasteners 170 or clamp-type fasteners 180, a gasket 220 may be disposed in the channel 216 to seal the cooling chamber 208 between the cap body 202 and the integrated circuit package 160. As shown in Figures 14A, 14C, and 14D, a gap may exist between the cooling cap 200 and the integrated circuit package 160, and the gasket 220 may be used to seal the gap. The gap may have a gap height HG ranging from approximately 0 μm to approximately 5000 μm. Attaching the cooling cap 200 with a specified gap height HG ensures that the gasket 220 can seal the cooling chamber 208, which prevents liquid coolant 222 from overflowing from the cooling chamber 208. Furthermore, providing a gap height HG greater than a specified value reduces the ratio between the inlet height HI and the outlet height HO, which reduces the improved heat transfer uniformity from the integrated circuit package 160 to the liquid coolant 222.

[0067] Figure 14D illustrates an embodiment in which a cooling cap 200 is attached to an integrated circuit package 160i, which includes a single first integrated circuit die 50A and no second integrated circuit die 50B. As shown in Figure 14D, the first integrated circuit die 50A may be laterally sealed by an encapsulation 124, or the encapsulation 124 may be omitted. The cooling cap 200 may be attached to an integrated circuit package 160 including any number of first integrated circuit dies 50A and / or second integrated circuit dies 50B.

[0068] Figures 14A to 14D further illustrate the flow path 224 of liquid coolant 222 through cooling cap 200. Flow path 224 extends through inlet 204, propagates through inlet distributor 206, flows through cooling chamber 208 across surface package 160 of integrated circuit, condenses through outlet collector 210, and exits through outlet 212. As previously described, the height of cooling chamber 208 decreases in the direction of flow path 224, such that the flow rate (e.g., mass flux) of liquid coolant 222 increases as liquid coolant 222 flows through cooling chamber 208. As liquid coolant 222 flows through cooling chamber 208, the temperature of liquid coolant 222 increases, which reduces heat transfer from integrated circuit package 160 to liquid coolant 222. However, increasing the flow rate of liquid coolant 222 increases heat transfer from integrated circuit package 160 to liquid coolant 222. Therefore, forming a cooling chamber 208 with a specified height and shape ensures uniform heat transfer from the integrated circuit package 160 to the liquid coolant 222 through the flow path 224 of the cooling chamber 208. This allows for improved device performance and reduces device defects caused by overheating of the integrated circuit package 160.

[0069] Figures 14A to 14D illustrate embodiments in which a cooling chamber 208 is disposed above a first integrated circuit die 50A. In some embodiments, the cooling chamber 208 may extend over the first integrated circuit die 50A, the second integrated circuit die 50B, the encapsulation 124, or any combination thereof. Furthermore, Figures 14A to 14D illustrate embodiments in which the flow direction of the flow path 224 of the liquid coolant 222 above the first integrated circuit die 50A is perpendicular to the longitudinal axis of the channel 140. However, in some embodiments, the flow direction of the flow path 224 of the liquid coolant 222 over the first integrated circuit die 50A, the second integrated circuit die 50B, and / or the encapsulation 124 may be parallel to or perpendicular to the longitudinal axis of the channel 140 and / or the channel 142. The selection of the flow rate of liquid coolant 222 and the flow direction of liquid coolant 222 along flow path 224 affects the heat transfer from integrated circuit package 160 to liquid coolant 222 and can be used to satisfy the thermal conversion of the device included in integrated circuit package 160.

[0070] The embodiments can achieve various advantages. For example, a cooling cap 200 is provided including a cooling chamber 208 having a gradually decreasing height from inlet to outlet, and the flow rate of the liquid coolant 222 increases as it flows through the cooling chamber 208. This results in more uniform heat transfer from the integrated circuit package 160 to the liquid coolant 222 and improves heat transfer from the integrated circuit package 160 to the liquid coolant 222. This allows for improved device performance and reduced device defects caused by overheating in the integrated circuit package 160.

[0071] According to one embodiment, a cooling cover for a semiconductor device includes: an inlet; an outlet; and a cooling chamber in fluid communication with the inlet and the outlet, the cooling chamber having a trapezoidal shape in a cross-sectional view. In one embodiment, the cooling chamber has a first height adjacent to the inlet, wherein the cooling chamber has a second height adjacent to the outlet, and wherein the first height is greater than the second height. In one embodiment, the ratio of the first height to the second height is from 1 to 50. In one embodiment, the first height is less than 2000 μm, and wherein the second height is less than 1000 μm. In one embodiment, an adhesive is further included surrounding the cooling chamber. In one embodiment, a gasket is further included surrounding the cooling chamber. In one embodiment, the cooling chamber is configured to directly cool the back side of an integrated circuit device using a liquid coolant.

[0072] According to another embodiment, an apparatus includes: a packaged semiconductor device including a first integrated circuit wafer including a plurality of channels located on the back side of the first integrated circuit wafer; and a cooling cap located on the packaged semiconductor device, wherein the cooling cap includes: a cooling chamber located on the first integrated circuit wafer; and a gasket surrounding the cooling chamber and contacting the packaged semiconductor device. In one embodiment, the cooling cap is attached to the packaged semiconductor device by a screw-type fastener, wherein the screw-type fastener extends through a portion of the packaged semiconductor device and a portion of the cooling cap. In one embodiment, the cooling cap is attached to the packaged semiconductor device by a clamp-type fastener contacting a first surface of the cooling cap relative to the packaged semiconductor device and a second surface of the packaged semiconductor device relative to the cooling cap. In one embodiment, the cooling cap further includes an inlet and an outlet, wherein the cooling chamber is in fluid communication with the inlet and the outlet, and wherein the cooling chamber has a trapezoidal shape in a cross-sectional view. In one embodiment, the cooling chamber has a first height adjacent to the inlet, wherein the cooling chamber has a second height adjacent to the outlet, wherein the first height is less than 2000 μm, and wherein the second height is less than 1000 μm. In one embodiment, the cooling chamber is configured to allow liquid coolant to flow through the plurality of channels in a direction perpendicular to the longitudinal axis of the channels. In another embodiment, the cooling chamber is configured to allow liquid coolant to flow through the plurality of channels at an increased mass flux.

[0073] According to yet another embodiment, a method of cooling a packaged semiconductor device includes: providing the packaged semiconductor device; attaching a cooling cap to the packaged semiconductor device; and allowing a liquid coolant to flow through the cooling cap, wherein the cooling cap is configured to increase the flow rate of the liquid coolant as it moves across a surface of the packaged semiconductor device. In one embodiment, the surface of the packaged semiconductor device is provided with a plurality of channels formed therein. In one embodiment, the liquid coolant comprises water. In one embodiment, the cooling cap is attached to the packaged semiconductor device by an adhesive, and wherein the adhesive is placed in a channel of the cooling cap surrounding a cooling chamber. In one embodiment, the cooling cap is attached to the packaged semiconductor device by a screw-type fastener, and wherein the screw-type fastener applies pressure to a gasket of the cooling cap surrounding the cooling chamber to prevent the liquid coolant from escaping from the cooling chamber. In one embodiment, the cooling cap includes a cooling chamber on the packaged semiconductor device, wherein the cooling chamber has an inclined surface opposite the packaged semiconductor device, wherein the inclined surface of the cooling chamber increases the flow rate of the liquid coolant as it moves across the inclined surface of the cooling chamber.

[0074] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art will recognize that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to it without departing from the spirit and scope of this disclosure.

[0075] 50: Integrated circuit die

[0076] 50A: First integrated circuit die

[0077] 50B: Second Integrated Circuit Die

[0078] 52: Semiconductor substrate

[0079] 54: Device

[0080] 56: Interlayer Dielectric

[0081] 58: Conductive plug

[0082] 60, 106: Internal wiring structure

[0083] 62: Pad

[0084] 64: Passivation film

[0085] 66, 134: Grain connectors

[0086] 68, 108: Dielectric layer

[0087] 100: Wafer

[0088] 100A: First package area

[0089] 100B: Second Package Area

[0090] 100C: Third Package Area

[0091] 100D: Fourth Package Area

[0092] 102, 103, 150: Base

[0093] 104, 156: Through holes

[0094] 110: Metallization layer

[0095] 112, 152, 154: Joint pads

[0096] 114, 146: Conductive connectors

[0097] 122, 158: Bottom filler

[0098] 124: Encapsulation

[0099] 130: Supporting base

[0100] 132: Release layer

[0101] 140, 142, 216: Channels

[0102] 157, 228: Bolt holes

[0103] 160, 160i: Integrated circuit package

[0104] 170: Screw-type fasteners

[0105] 180: Clamp-type fastener

[0106] 200: Cooling cover

[0107] 202: Main body of the cover

[0108] 204: Entrance

[0109] 206: Inlet Distributor

[0110] 208: Cooling Chamber

[0111] 210: Exit Collector

[0112] 212: Export

[0113] 220: Gasket

[0114] 222: Liquid coolant

[0115] 224: Flow path

[0116] 226: Adhesive

[0117] HG: Gap Height

[0118] HI: Entrance Height

[0119] HO: Export Height

Claims

1. A cooling cap for a semiconductor device, comprising: An inlet having a first fluid flow cross-sectional area and a first flow channel height; An inlet distributor, fluidly in communication with the inlet, wherein the inlet distributor has a second fluid flow cross-sectional area greater than the first fluid flow cross-sectional area and a second flow channel height greater than the first flow channel height; an outlet; an outlet collector, fluidly in communication with the outlet; and a cooling chamber, fluidly in communication with the inlet distributor and the outlet collector, wherein the cooling chamber has a flat surface on the side away from the semiconductor device, wherein the cooling chamber has a third flow channel height less than the second flow channel height at a first interface with the inlet distributor and a fourth flow channel height less than the third flow channel height at a second interface with the outlet collector, and the cooling chamber has a third fluid flow cross-sectional area less than the second fluid flow cross-sectional area at the second interface, wherein the outlet collector has a fifth flow channel height greater than the fourth flow channel height and greater than the sixth flow channel height of the outlet, wherein the outlet has a fourth fluid flow cross-sectional area less than the third fluid flow cross-sectional area, wherein the cooling cap is attached to the integrated circuit device of the semiconductor device by an adhesive, and wherein the adhesive is placed in a channel of the cooling cap surrounding the cooling chamber. The cooling chamber is configured to directly cool the back side of the integrated circuit device using a liquid coolant. The integrated circuit device includes a plurality of channels located on the back side of the integrated circuit device, the plurality of channels extending to the edges of the integrated circuit device. The semiconductor device includes an encapsulation that seals the integrated circuit device, and the top surfaces of the integrated circuit device and the encapsulation are coplanar.

2. The cooling cap as claimed in claim 1, wherein the liquid coolant comprises water.

3. The cooling cap as claimed in claim 1, wherein the first height is less than 2000 μm, and wherein the second height is less than 1000 μm.

4. The cooling cover as claimed in claim 1, further comprising a gasket surrounding the cooling chamber.

5. A packaged semiconductor device including a cooling cap, comprising: A packaged semiconductor device, the packaged semiconductor device including a first integrated circuit wafer, the first integrated circuit wafer including a plurality of channels located on the back side of the first integrated circuit wafer, the plurality of channels extending to the edge of the first integrated circuit wafer; and a cooling cap, located on the packaged semiconductor device, wherein the cooling cap includes: an inlet having a first fluid flow cross-sectional area and a first channel height extending along a first direction perpendicular to the main surface of the packaged semiconductor device; an inlet distributor, in fluid communication with the inlet, having a second fluid flow cross-sectional area and a second channel height along the first direction, the second channel height being greater than the first channel height; a cooling chamber located on the first integrated circuit wafer, wherein the cooling chamber has a flat surface on the side away from the first integrated circuit wafer, the first side of the cooling chamber in fluid communication with the inlet distributor having a third channel height along the first direction, the third channel height being less than the second channel height; and an outlet collector having a fourth channel height along the first direction, the fourth channel height being greater than the third channel height, wherein the second side of the cooling chamber in fluid communication with the outlet collector has a third fluid flow cross-sectional area, the third fluid flow cross-sectional area being less than the second fluid flow cross-sectional area, and the second side of the cooling chamber is disposed opposite to the first side of the cooling chamber; An outlet, in fluid communication with the outlet collector, wherein the outlet has a fourth fluid flow cross-sectional area and a fifth flow channel height along the first direction, the fourth fluid flow cross-sectional area being smaller than the third fluid flow cross-sectional area and the fifth flow channel height being smaller than the fourth flow channel height; and a gasket surrounding the cooling chamber and contacting the packaged semiconductor device, wherein the cooling cap is attached to the packaged semiconductor device by an adhesive, and wherein the adhesive is placed in a channel of the cooling cap surrounding the cooling chamber, wherein the cooling chamber is configured to directly cool the back side of the first integrated circuit wafer using a liquid coolant.

6. The apparatus of claim 5, wherein the second side of the cooling chamber has a sixth flow channel height along the first direction, the sixth flow channel height being less than the third flow channel height.

7. The apparatus of claim 5, wherein the plurality of channels extend from a first side of the first integrated circuit wafer to a second side of the first integrated circuit wafer opposite to the first side and through the back surface of the first integrated circuit wafer.

8. A method for cooling a packaged semiconductor device, comprising: Provide packaged semiconductor devices; Attach the cooling cap to the packaged semiconductor device; The liquid coolant is allowed to flow through the cooling cap via the following steps: The liquid coolant is allowed to flow through an inlet having a first flow channel height and a first fluid flow cross-sectional area; The liquid coolant is allowed to flow from the inlet to an inlet distributor having a second flow channel height greater than the first flow channel height and a second fluid flow cross-sectional area greater than the first fluid flow cross-sectional area; The liquid coolant is allowed to flow from the inlet distributor to a cooling chamber having a cooling chamber flow channel height that decreases from a third flow channel height to a fourth flow channel height less than the third flow channel height along the flow direction of the liquid coolant, and the cooling chamber having a fluid flow cross-sectional area that decreases from the flow direction of the liquid coolant to a third fluid flow cross-sectional area less than the second fluid flow cross-sectional area; The liquid coolant flows from the cooling chamber to an outlet collector having a fifth flow channel height greater than a third flow channel height; and the liquid coolant flows from the outlet collector to an outlet having a fourth fluid flow cross-sectional area smaller than the third fluid flow cross-sectional area and a sixth flow channel height less than the fifth flow channel height, wherein the cooling cap is configured to increase the flow rate of the liquid coolant as it moves across the surface of the packaged semiconductor device, wherein the cooling chamber has a flat surface on the side away from the packaged semiconductor device, the cooling cap being attached to an integrated circuit device of the packaged semiconductor device by an adhesive, the integrated circuit device including a plurality of channels on the back side of the integrated circuit device extending to the edge of the integrated circuit device, and wherein the adhesive is placed in a channel of the cooling cap surrounding the cooling chamber, wherein the cooling chamber is configured to directly cool the back side of the integrated circuit device using the liquid coolant.

9. The method of claim 8, wherein the packaged semiconductor device includes an encapsulation that seals the integrated circuit device, the back surface of the integrated circuit device being coplanar with the top surface of the encapsulation, the plurality of channels extending from a first side of the integrated circuit device to a second side of the integrated circuit device opposite to the first side and penetrating the back surface of the integrated circuit device, and the plurality of channels further extending through the top surface of the encapsulation.

10. The method of claim 8, wherein the cooling chamber has an inclined surface opposite to the packaged semiconductor device, wherein the inclined surface of the cooling chamber increases the flow rate of the liquid coolant as the liquid coolant moves on the inclined surface of the cooling chamber.

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