Semiconductor structure and method of manufacturing semiconductor device

Abstract

This disclosure provides a semiconductor structure according to some embodiments. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region; a first transistor including a first gate stack disposed in the first circuit region; a second transistor including a second gate stack disposed in the second circuit region; and a guard ring structure disposed between the first circuit region and the second circuit region. The first gate stack and the second gate stack have different material compositions. The guard ring structure completely surrounds the second circuit region.

Description

Technical Field

[0001] This disclosure relates to methods for manufacturing semiconductor structures and semiconductor devices. Prior Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in generation after generation of integrated circuits, each smaller and more complex than the last. Throughout the development of ICs, functional density (the number of interconnects per wafer area) has generally increased, while geometry (the smallest component (or line) that can be created using manufacturing processes) has decreased. This scaling down typically benefits production efficiency and reduces associated costs. However, this scaling down also increases the complexity of processing and manufacturing ICs.

[0003] For example, modern ICs contain millions or billions of transistors formed on semiconductor substrates (such as silicon). ICs can use many different types of transistors, depending on the application. In recent years, the increasing market for mobile phones and RF (radio frequency) devices has led to a significant increase in the use of RF transistors. As the IC industry moves towards advanced technologies with smaller feature sizes, such as 7nm, 5nm, and 3nm, miniaturization processes have led to various developments in IC designs that integrate RF and logic transistors. Integrated circuit structures face various challenges, including noise coupling, short circuits, leakage current, routing resistance, alignment margins, layout flexibility, and package density. Therefore, a transistor structure and approach are needed to address these issues to improve circuit performance and reliability. Summary of the Invention

[0004] This disclosure relates to a semiconductor structure comprising: a semiconductor substrate having a first circuit region and a second circuit region; a first transistor including a first gate stack disposed in the first circuit region; a second transistor including a second gate stack disposed in the second circuit region, wherein the first gate stack and the second gate stack have different material compositions; and a guard ring structure disposed between the first circuit region and the second circuit region, wherein the guard ring structure completely surrounds the second circuit region.

[0005] This disclosure also relates to a semiconductor structure comprising: a semiconductor substrate having a logic circuit region and a radio frequency (RF) circuit region; a first transistor including a first gate stack disposed in the logic circuit region; a second transistor including a second gate stack disposed in the RF circuit region; and a guard ring structure disposed between the logic circuit region and the RF circuit region, wherein the guard ring structure includes an inner guard ring completely surrounding the RF circuit region and an outer guard ring completely surrounding the inner guard ring and the RF circuit region.

[0006] This disclosure also relates to a method of manufacturing a semiconductor device, comprising: forming a first gate stack in a first circuit region on a substrate; forming a second gate stack in a second circuit region on the substrate; forming a third gate stack in a guard ring region between the first circuit region and the second circuit region, wherein the first gate stack, the second gate stack, and the third gate stack each comprise the same material composition, and wherein the third gate stack completely surrounds the second circuit region in a top view; depositing a patterned mask layer covering the guard ring region and the second circuit region; performing an etching process to remove a first metal filler layer in the first gate stack, wherein the etching process also partially etches the third gate stack to form a gap; depositing a second metal filler layer in the gap between the second gate stack and the third gate stack; and planarizing the semiconductor device to expose the first metal filler layer in the second gate stack. Simple Explanation of the Diagram

[0007] The various features disclosed herein are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased arbitrarily for clarity of discussion.

[0008] Figure 1 is a top view of an integrated circuit (IC) structure constructed according to various patterns disclosed herein.

[0009] Figure 2 is a cross-sectional view of the integrated circuit structure of Figure 1 constructed according to the various forms disclosed herein.

[0010] Figures 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20 and 21 illustrate perspective views and cross-sectional views of intermediate stages of IC structures formed according to various forms of the present disclosure.

[0011] Figure 22 illustrates the layout of an IC structure having one or more guard rings surrounding the RF circuit region, according to various embodiments disclosed herein.

[0012] Figures 23, 24, 25, 26, 27, 28, 29, 30, and 31 illustrate cross-sectional views of intermediate stages in the formation of the IC structure of Figure 22 according to various forms disclosed herein.

[0013] Figures 32 and 33 illustrate alternative layouts of IC structures having one or more guard rings surrounding the radio frequency circuit region, according to various embodiments of this disclosure.

[0014] Figures 34A, 34B, 34C, and 34D illustrate some transistor structures that can be used as logic transistors and RF transistor devices according to the various forms disclosed herein.

[0015] Figure 35 illustrates the process flow for forming IC structures including logic circuit regions and RF circuit regions according to various patterns disclosed herein. Implementation

[0016] This disclosure claims priority to U.S. Provisional Patent Application No. 63 / 373,965, filed August 30, 2022, the entire disclosure of which is incorporated herein by reference.

[0017] The following disclosure provides many different embodiments, or examples, for implementing the different features of this disclosure. To simplify this disclosure, specific examples of components and configurations are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features are not in direct contact.

[0018] Furthermore, element symbols and / or letters may be repeated in various embodiments of this disclosure. This repetition is for simplicity and clarity and does not, in itself, determine the relationship between the various embodiments and / or configurations discussed. Additionally, in this disclosure, the formation of one feature on another feature, its connection to another feature, and / or its coupling to another feature may include embodiments where features are formed in direct contact, or embodiments where additional features may be formed between features, thereby allowing the features to not be in direct contact. Furthermore, spatially relative terms, such as “down,” “up,” “horizontal,” “vertical,” “above,” “below,” “under,” “upward,” “downward,” “top,” “bottom,” etc., and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.), are used to facilitate understanding of the relationship between one feature and another in this disclosure. Spatially relative terms are intended to encompass different orientations of the device, including features. Furthermore, when using terms such as "about" or "approximately" to describe a number or range of numbers, the term is intended to cover numbers within a reasonable range that includes the stated number, such as within + / - 10% of the stated number or other values ​​understood by one of ordinary skill in the art. For example, the term "about 5 nm" encompasses a size range from 4.5 nm to 5.5 nm.

[0019] This disclosure generally relates to semiconductor circuit structures with field-effect transistors (FETs) and their fabrication processes, and more specifically to a semiconductor circuit structure comprising a combination of a first type of transistor and a second type of transistor, having one or more moat-like guard rings surrounding the first type of transistor for separation from the second type of transistor. According to some embodiments of this disclosure, the first type of transistor is a transistor for radio frequency (RF) applications (also referred to as an RF transistor); the second type of transistor is a transistor for logic applications (also referred to as a logic transistor). RF transistors operate in high-frequency bands, such as between about 100 kHz and about 300 GHz, or between about 1 GHz and about 300 GHz. Logic transistors operate in lower frequency bands than RF transistors. Those skilled in the art will understand that combinations of other types of transistors besides radio frequency transistors and / or logic transistors, such as first-type transistors for memory applications and second-type transistors for input / output (I / O) applications, can readily serve as the basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages of the embodiments described herein.

[0020] Furthermore, this disclosure provides various embodiments of integrated circuits (ICs) formed on a semiconductor substrate. These ICs have design layouts that can be combined with various standard cells. Standard cells are pre-designed IC structures that can be reused in a single IC design. Effective IC design layouts include various pre-designed standard cells and predefined rules for placing these standard cells to enhance circuit performance and reduce circuit area. According to embodiments, the formation of a FinFET transistor is used as an example to explain the concepts of this disclosure. Other types of transistors, such as planar transistors, nanoplate or nanowire transistors, gate-all-around (GAA) transistors, or the like, may also employ the concepts of this disclosure. According to some embodiments, intermediate stages of forming a FinFET transistor are illustrated. Some variations of some embodiments are discussed. Throughout the different views and illustrative embodiments, similar element symbols are used to designate similar elements. Although method embodiments may be discussed as being performed in a particular sequence, other method embodiments can be performed in any logical sequence.

[0021] Referring now to Figures 1 and 2. Figure 1 is a top view of a semiconductor structure (or semiconductor device) 100, and Figure 2 is a cross-sectional view of the semiconductor structure 100 along the dashed line XX in Figure 1, constructed according to various embodiments of this disclosure. In some embodiments, the semiconductor structure 100 is formed on a flat active region and includes a field-effect transistor (FET). In some embodiments, the semiconductor structure 100 is formed on a fin active region and includes a FinFET. In some embodiments, the semiconductor structure 100 includes a FET (also referred to as a GAA transistor) formed on a vertically stacked channel. Using the semiconductor structure 100 as an example, an IC structure and its fabrication method are described together.

[0022] In various embodiments, semiconductor structure 100 includes various circuit modules integrated on the same substrate. These circuit modules (or simply circuits) may have different functions or different circuit characteristics. These circuit modules are placed in different circuit regions of the substrate, either adjacent or distant, or in different surrounding environments. For example, semiconductor structure 100 includes a first circuit region 120 and a second circuit region 122 disposed on a semiconductor substrate (or simply substrate) 102. Semiconductor structure 100 may include additional circuit regions, similar to or different from the first and second circuit regions. For example, semiconductor structure 100 includes other logic circuit regions, other radio frequency (RF) circuit regions, other circuit regions such as memory regions, image sensor regions, analog circuit regions, or combinations thereof. In some embodiments, the first circuit formed in the first circuit region 120 is a logic circuit, and the second circuit formed in the second circuit region 122 is a radio frequency (RF) circuit. RF circuits typically require high frequencies and high speeds, and therefore have low parasitic capacitance. In some embodiments, the IC structure further includes a third circuit formed in a third circuit region, wherein the third circuit is a memory circuit containing various memory devices, such as static random access memory (SRAM) cells, arranged in an array.

[0023] These circuit regions may contain one or more standard cells placed in the IC layout according to predetermined rules. These standard cells are reused repeatedly in IC designs and are therefore pre-designed and stored in a standard cell library based on manufacturing techniques. IC designers can retrieve these standard cells, incorporate them into their IC designs, and place them in the IC layout according to predefined placement rules. For example, logic standard cells may contain various basic circuit devices such as inverters, AND, NAND, OR, XOR and NOR, flip-flop circuits, latches, or combinations thereof. These devices are popular in digital circuit design, such as in central processing units (CPUs), graphics processing units (GPUs), and system-on-a-chip (SoC) designs.

[0024] Substrate 102 comprises silicon. Alternatively, substrate 102 may comprise elemental semiconductors, such as crystalline silicon or germanium; compound semiconductors, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; or combinations thereof. Substrate 102 may also comprise a silicon-on-insulator (SOI) substrate. The SOI substrate is manufactured by SIMOX separation, wafer bonding, and / or other suitable methods.

[0025] The substrate 102 also includes various isolation features 104, such as isolation features formed on the substrate 102, to define various active regions 106 on the substrate 102. The isolation features 104 utilize isolation techniques, such as shallow trench isolation (STI), to define and electrically isolate the various active regions. Each active region 106 is surrounded by a continuous isolation feature, separating it from other adjacent active regions. The isolation features 104 include silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof. The isolation features 104 are formed by any suitable process. As an example, forming an STI feature includes a lithography process to expose a portion of the substrate, etching trenches in the exposed portion of the substrate (e.g., by using dry etching and / or wet etching), filling the trenches with one or more dielectric materials (e.g., by using a chemical vapor deposition process), and planarizing the substrate and removing excess dielectric material by a polishing process, such as a chemical mechanical polishing (CMP) process. In some examples, the filled trench may have a multi-layered structure, such as a thermally oxidized liner layer and a fill layer of silicon nitride or silicon oxide.

[0026] Active region 106 is a region having a semiconductor surface in which various doping features are formed and configured into one or more devices, such as diodes, transistors, and / or other suitable devices. Active region 106 may contain a semiconductor material similar to the bulk semiconductor material (e.g., silicon) of substrate 102, or a different semiconductor material, such as silicon germanium (SiGe), silicon carbide (SiC), or multiple semiconductor material layers (e.g., replacing silicon and silicon germanium layers) formed on substrate 102 by epitaxial growth to enhance performance, such as strain effects that increase carrier mobility.

[0027] In some embodiments, the active region 106 is three-dimensional, such as a finned active region extending above the isolation feature. The finned active region 106 is extruded from above the isolation feature 104 of the substrate 102 and has a three-dimensional profile for more efficient coupling between the FFT channels and the gate electrode. In particular, the substrate 102 has a top surface, and the finned active region 106 has a top surface that is higher than the top surface of the substrate 102. The finned active region 106 may be formed by selective etching to recess the isolation feature, or by selective epitaxial growth to grow an active region having the same or different semiconductor as the substrate 102, or a combination thereof.

[0028] The substrate 102 further includes various doping features, such as n-type doped wells, p-type doped wells, source and drain features, other doping features, or combinations thereof, configured as elements for forming various devices or components, such as source and drain features of a field-effect transistor. In the example shown in FIG1, the semiconductor structure 100 includes a negatively doped well (also referred to as an N-well) 108 and a positively doped well (also referred to as a P-well) 110. The N-well 108 contains a negative dopant, such as phosphorus. The P-well 110 contains a positive dopant, such as boron. The N-well 108 and the P-well 110 are formed by appropriate techniques, such as ion implantation, diffusion, or combinations thereof. In this embodiment, an active region 106 is formed in the N-well 108, and another active region 106 is formed in the P-well 110.

[0029] The semiconductor structure 100 further includes various gate stacks (or simply gates) 112 having an elongated shape oriented in a first direction (Y-direction). In this embodiment, the X and Y directions are orthogonal and define the top surface of the substrate 102. The gate stacks include gate dielectric layers and gate electrodes. Gate stacks are a feature of FETs and work in conjunction with other features such as source / drain (S / D) features and channels, where the channels are part of the active region located below the gate stack; while the S / D features are in the active region and are disposed on both sides of the gate stack. In this embodiment, the gate stacks of the first circuit region 120 and the second circuit region 122 are referred to as gate stacks 112A and 112B, respectively. It should be noted that gate stacks should not be confused with logic gates, such as NOR logic gates.

[0030] The semiconductor structure 100 may also include a stack of dummy gates disposed on the substrate 102. The dummy gates are not functional gates. Instead, they are provided for other purposes, such as tuning pattern density and / or isolation. The dummy gates may have a structure similar to the functional gate 112. Additionally, in some cases, the dummy gates may have different structures, or even include dielectric features of one or more dielectric materials (also referred to as dielectric gates), and function as isolation features.

[0031] The dummy gate is similar in formation to gate 112. In some embodiments, gate 112 and the dummy gate are formed together by a process, such as a gate-last process. In a further embodiment, the initial dummy gate is first formed by deposition and patterning, wherein the patterning further includes lithography and etching. Subsequently, a subset of the initial dummy gate is replaced by depositing a gate dielectric layer and gate electrodes to form gate 112, while the remaining initial dummy gates are replaced by depositing dielectric material to form dielectric gates. Furthermore, the arrangement and configuration of the dummy gates are different, and therefore their functions are also different. In the described embodiments, some dielectric gates are placed in the boundary region between circuit modules or at the boundary of standard cells to act as isolation, separating one standard cell from adjacent standard cells, and some dielectric gates are placed within the standard cells or within the circuit modules of the circuit region to achieve one or more considerations, such as isolation between adjacent FETs and adjustment of pattern density. Therefore, virtual gates provide isolation between adjacent IC devices and additionally provide pattern density adjustment to improve manufacturing processes such as etching, deposition, and CMP.

[0032] In this embodiment, the semiconductor structure 100 includes a first circuit region 120 for logic circuits and a second circuit region 122 for radio frequency circuits. The two circuit regions 120 and 122 may be placed adjacent to each other or separated by a distance by a virtual region containing a plurality of virtual gates.

[0033] In the described embodiment, the semiconductor structure 100 includes a first active region 106 in an N-well 108 and a second active region 106 in a P-well 110. A gate 112A in the first circuit region 120 extends continuously along the Y direction from the first active region 106 (in the N-well 108) to the second active region 106 (in the P-well 110). Similarly, a gate 112B in the second circuit region 122 extends continuously along the Y direction from the first active region 106 (in the N-well 108) to the second active region 106 (in the P-well 110).

[0034] With the source / drain regions 126 and the channels 130 formed for each transistor associated with its respective gate, active region, and circuit region, the first circuit region 120 includes a p-type FET 132 in an N-well 108 and an n-type FET 133 in a P-well 110; and the second circuit region 122 includes a pFET 134 in an N-well 108 and an nFET 135 in a P-well 110. In this embodiment, the pFET 132, nFET 133, and other FET systems in the first circuit region 120 are integrated to form a functional circuit block, such as a logic circuit; while the pFET 134, nFET 135, and other FET systems in the second circuit region 122 are integrated to form another functional circuit block, such as an RF circuit.

[0035] For illustrative purposes, Figures 1 and 2 provide an exemplary semiconductor structure 100 having a first circuit region 120 and a second circuit region 122. However, it will be understood that the semiconductor structure 100 may include additional circuit regions and some dummy regions (or filler regions) added in various configurations. In some embodiments, the various circuit regions are surrounded by their respective dummy regions. For example, depending on the individual design, additional circuit regions and dummy regions may be added to the left, right, top, and / or bottom edges of Figure 1 in a similar configuration. Other IC structures in the figures, such as those discussed below, should also be understood in a similar manner.

[0036] Specifically, the gate stack 112A in the first circuit region 120 and the gate stack 112B in the second circuit region 122 have different pitches. The pitch is defined as the periodic distance of the gate array, such as the center-to-center distance between two adjacent gates in the gate array. In this embodiment, the gate stack 112A has a first pitch P1, and the gate stack 112B has a second pitch P2 greater than the first pitch P1. For example, the first pitch P1 is less than a reference pitch, and the second pitch P2 is greater than the reference pitch. The reference pitch is determined based on the manufacturing techniques and characteristics of the first and second transistors. In the described embodiment, the reference pitch may be around 100 nm. For example, the first pitch P1 is less than 100 nm, and the second pitch P2 is greater than 100 nm. In some embodiments, the P2 / P1 ratio is sufficiently large, for example, greater than 1.5, to achieve the desired circuit performance improvement and respective gate profiles. In some embodiments, the P2 / P1 ranges between 1.2 and 2. The first pitch P1 and the second pitch P2 can be tuned for their respective circuit performance. Therefore, the RF circuitry in the second circuit region 122 can have a larger spacing, less parasitic capacitance, and higher high-frequency performance; while the logic circuitry in the first circuit region 120 can have a smaller spacing and higher package density without reducing overall circuit performance. Furthermore, the gate stacks 112A and 112B can differ in gate spacing, gate size, gate structure, gate profile, gate orientation, gate configuration, gate composition, gate environment, dummy gate design, or combinations thereof.

[0037] In the above example, only two circuit regions (120 and 122) are described. However, the semiconductor structure 100 may include multiple circuit regions, each designed for its own function. For example, a first circuit region for logic circuits may have a first gate pitch, a second circuit region for RF circuits may have a second gate pitch, a third circuit region for memory circuits may have a third gate pitch, and a fourth circuit region for I / O devices may have a fourth gate pitch. These gate pitches differ from each other and are individually tuned for their respective circuit characteristics and performance enhancements. Furthermore, each circuit region may include dummy gates surrounding the functional gate. These dummy gates are further tuned with different designs (such as gate pitch, gate size, and gate group) to compensate for pattern density, thereby eliminating process defects and improving circuit performance. The region used for the dummy gates is called a dummy region, and the region used for the functional gate is called an active device region (or active circuit region). Because the dummy gates of the dummy regions are not part of the circuit but are designed to improve manufacturing and circuit performance, they have more tuning freedom, such as gate material, gate pitch, gate size, gate orientation, and gate pattern density. Furthermore, the placement and size of the dummy region are also factors for the tuning process. For example, the dummy region is placed at the edge of the circuit area, where the gate pattern density is relatively far from the average value.

[0038] Referring now to Figures 3 through 21, perspective and cross-sectional views are illustrated for intermediate stages of forming RF transistors and logic transistors in the semiconductor device 100 of Figures 1 and 2, according to some embodiments of the present disclosure. The processes shown in these figures are also schematically reflected in the process flow 200 shown in Figure 35.

[0039] Referring to Figure 3, a substrate 102 is provided. The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 102 may be a portion of a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 102 may comprise silicon; germanium; compound semiconductors comprising carbon-doped silicon, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0040] Referring again to FIG. 3, a well region 108 is formed in substrate 102. In the process flow 200 shown in FIG. 35, each process is described as process 202. According to some embodiments of the present disclosure, the well region 108 is an n-type well region formed by implanting an n-type impurity into substrate 102, the n-type impurity being phosphorus, arsenic, antimony, or the like. According to other embodiments of the present disclosure, the well region is a p-type well region formed by implanting a p-type impurity into substrate 102, the p-type impurity being boron, indium, or the like. The formed well region 108 may extend to the top surface of substrate 102. The concentration of the n-type or p-type impurity may be equal to or less than 10¹⁸ cm⁻³, for example, between about 10¹⁷ cm⁻³ and about 10¹⁸ cm⁻³. Substrate 102 also includes a first circuit region 120 for forming logic transistors and a second circuit region 122 for forming RF transistors.

[0041] Referring to FIG. 4, isolation region 104 is formed extending from the top surface of substrate 102 to substrate 102. Isolation region 104 may alternatively be referred to as shallow trench isolation (STI) region. In the process flow 200 shown in FIG. 35, the respective process is illustrated as process 204. The portion of substrate 102 between adjacent STI regions 104 is referred to as semiconductor strip 105. To form STI region 104, a pad oxide layer 116 and a hard mask layer 118 are formed on semiconductor substrate 102, followed by patterning. Pad oxide layer 116 may be a thin film formed of silicon oxide. According to some embodiments of this disclosure, pad oxide layer 116 is formed in a thermal oxidation process, wherein the top surface layer of substrate 102 is oxidized. Pad oxide layer 116 serves as an adhesion layer between substrate 102 and hard mask layer 118. Pad oxide layer 116 may also serve as an etch stop layer for etching the hard mask layer 118. According to some embodiments of this disclosure, the hard mask layer 118 is formed of silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD). According to other embodiments of this disclosure, the hard mask layer 118 is formed by thermal nitridation of silicon or plasma-enhanced chemical vapor deposition (PECVD). A photoresist (not shown) is formed on the hard mask layer 118, followed by patterning. The hard mask layer 118 is then patterned using the patterned photoresist as an etching mask to form the patterned hard mask layer 118 as shown in FIG. 4.

[0042] Next, a patterned hard mask layer 118 is used as an etching mask to etch the pad oxide layer 116 and the substrate 102, followed by filling the resulting trenches in the substrate 102 with a dielectric material. A planarization process, such as chemical mechanical polishing (CMP) or mechanical polishing, is performed to remove excess dielectric material, leaving the remaining dielectric material as the STI region 104. The STI region 104 may include a pad dielectric (not shown), which may be a thermal oxide formed by thermal oxidation of the surface layer of the substrate 102. The pad dielectric may also be a deposited silicon oxide layer, silicon nitride layer, or the like, formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The STI region 104 may also contain a dielectric material on top of the pad oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, or similar methods. According to some embodiments, the dielectric material above the pad dielectric may comprise silicon oxide.

[0043] The top surfaces of the patterned hard mask layer 118 and the STI regions 104 may be substantially flush with each other. Semiconductor strips 105 are located between adjacent STI regions 104. According to some embodiments of this disclosure, semiconductor strips 105 are portions of the original substrate 102, and therefore the material of semiconductor strips 105 is the same as that of substrate 102. According to alternative embodiments of this disclosure, semiconductor strips 105 are replacement strips formed by etching portions of substrate 102 between STI regions 104 to form recesses and performing epitaxy to regenerate another semiconductor material in the recesses. Therefore, semiconductor strips 105 are formed of a semiconductor material different from that of substrate 102. According to some embodiments, semiconductor strips 105 are formed of silicon germanium, silicon carbon, or III-V compound semiconductor materials. The patterned hard mask layer 118 is then removed.

[0044] Referring to Figure 5, the STI region 104 is recessed, so that the top portion of the semiconductor strip 105 protrudes above the top surface 104A of the rest of the STI region 104 to form a protruding fin 106. In the process flow 200 shown in Figure 35, the respective process is illustrated as process 206. The pad oxide layer 116 and the patterned hard mask layer 118 are also removed. This etching can be performed using a dry etching process, for example, where HF 3 and NH 3 are used as etching gases. Plasma may be generated during the etching process. Argon may also be included. According to an alternative embodiment of this disclosure, the recess of the STI region 104 is performed using a wet etching process. The etching chemical may include, for example, HF.

[0045] In the embodiments illustrated in the foregoing figures, the fin can be patterned using any suitable method. For example, the fin can be patterned using one or more photolithography processes, including dual or multiple patterning processes. Typically, dual or multiple patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns, for example, with smaller spacing than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate, and photolithography is used to perform patterning. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin.

[0046] Referring to Figure 6, a virtual gate stack 138 is formed to extend on the top surface and sidewalls of the (protruding) fin 106. In the process flow 200 shown in Figure 35, the respective process is described as process 208. The virtual gate stack 138 may include a virtual gate dielectric 140 and a virtual gate electrode 142 on top of the virtual gate dielectric 140. The virtual gate dielectric 140 may be formed of silicon oxide or a similar material. The virtual gate electrode 142 may be formed, for example, of polycrystalline silicon, or other materials may be used. Each of the virtual gate stacks 138 may also include one (or more) hard masking layers 144 on top of the virtual gate electrode 142. The hard masking layer 144 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or multiple layers thereof. The virtual gate stack 138 can cross over one or more protruding fins 106 and / or STI regions 104. The virtual gate stack 138 also has a length direction perpendicular to the length direction of the fins 106.

[0047] Next, gate spacer 146 is formed on the sidewalls of the virtual gate stack 138. In the process flow 200 shown in FIG. 35, the respective process is also shown as process 208. According to some embodiments of this disclosure, gate spacer 146 is formed of a low dielectric constant dielectric material, such as porous silicon oxynitride, porous silicon carbonitride, porous silicon nitride, or similar materials, and may have a single-layer structure or a multilayer structure comprising multiple dielectric layers. The dielectric constant (k-value) of gate spacer 146 is less than 3.8, and may be less than about 3.0, for example, between about 2.5 and about 3.0.

[0048] Referring to Figure 7, an etching process is then performed to etch portions of the fin 106 not covered by the dummy gate stack 138 and gate spacer 146. The respective process is illustrated as process 210 in the process flow 200 shown in Figure 35. The recess may be non-isotropic, thus protecting the portion of the fin 106 directly beneath the dummy gate stack 138 and gate spacer 146 from etching. According to some embodiments, the top surface of the recessed semiconductor strip 105 may be lower than the top surface 104A of the STI region 104. A recess 148 is formed accordingly. The recess 148 includes portions located on opposite sides of the dummy gate stack 138 and portions between the remaining portions of the fin 106.

[0049] Referring to Figure 8, an epitaxial feature (or source / drain feature or source / drain region) 126 is formed by selectively growing (by epitaxy) semiconductor material in the recess 148. In the process flow 200 shown in Figure 35, each process is described as process 212. For example, when the resulting FinFET is a p-type FinFET, boron-doped silicon germanium (SiGeB), boron-doped silicon (SiB), or the like can be grown; when the resulting FinFET is an n-type FinFET, phosphorus-doped silicon (SiP), arsenic-doped silicon (SiAs), or the like can be grown. According to an alternative embodiment of this disclosure, the source / drain region 126 comprises a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multiples thereof. After the recess 148 is filled by the source / drain region 126, further epitaxial growth of the source / drain region 126 causes it to expand horizontally and may form facets. Further growth of the source / drain region 126 may also cause adjacent source / drain regions 126 to merge with each other. Voids (air gaps) 128 may be created. The source / drain region may refer to either a source or a drain, individually or collectively, depending on the context.

[0050] Referring to Figures 9 and 10, Figure 9 illustrates a perspective view of the structure after the formation of the contact etch stop layer (CESL) 150 and the interlayer dielectric (ILD) layer 152, and Figure 10 illustrates a cross-sectional view along line XX in Figure 9. In the process flow 200 shown in Figure 35, each process is described as process 214. CESL 150 may be formed from silicon nitride, silicon oxide, silicon, carbonitride, or the like, and may be formed using CVD, ALD, or similar processes. ILD layer 152 may contain a dielectric material formed using, for example, FCVD, spin coating, CVD, or other deposition methods. ILD layer 152 may be formed from an oxygen-containing dielectric material, which may be a silicon oxide-based material, such as silicon oxide, phospholipid glass (PSG), borosilicate glass (BSG), boron-doped phospholipid glass (BPSG), or similar materials. A planarization process, such as CMP or mechanical polishing, can be performed to make the top surfaces of the ILD layer 152, the virtual gate stack 138, and the gate spacer 146 flush with each other. In Figure 10, the level of the top surface 104A of the STI region 104 is shown, with the fin 106 higher than the top surface 104A.

[0051] Referring to Figures 11 and 12, Figure 11 illustrates a perspective view of the structure after the removal of the dummy gate stack 138, and Figure 12 illustrates a cross-sectional view along line XX in Figure 11. In some embodiments, the removal of the dummy gate stack 138 includes one or more etching processes that remove the hard mask layer 144, the dummy gate electrode 142, and the dummy gate dielectric 140 from the dummy gate stack 138, thereby forming a gate trench 154. For example, selective etching processes, such as selective wet etching, selective dry etching, or combinations thereof, can be used to perform the removal of the dummy gate stack 138. In the process flow 200 shown in Figure 35, the respective processes are illustrated as process 216. The top surface and sidewalls of the fin 106 are exposed in the gate trench 154. The gate trenches 154 used for logic circuits in the first circuit region 120 are designated as gate trench 154A, while the gate trenches used for RF circuits in the second circuit region 122 are designated as gate trench 154B. Due to the different applications of the logic transistors and RF transistors, gate trenches 154A and 154B may have different dimensions. Therefore, the gate stacks subsequently formed in gate trenches 154A and 154B may have different dimensions. For example, the first width D1 of the gate trench 154A in the first circuit region 120 (which is also the gate width of the logic transistor formed in gate trench 154A) is smaller than a reference size (e.g., 40 nm in some examples), while the second width D2 of the gate trench 154B in the second circuit region 122 (which is also the gate width of the RF transistor formed in gate trench 154B) is larger than the reference size. In some embodiments, the ratio of D2 / D1 is between 1.2 and 3. In some embodiments, the ratio of D2 to D1 is greater than 2.

[0052] Referring to Figure 13, a gate dielectric layer 160 is formed in gate trenches 154A and 154B and contacts the upper surface and sidewalls of fin 106. In the process flow 200 shown in Figure 35, each process is described as process 218. According to some embodiments of this disclosure, the gate dielectric layer 160 includes an interfacial layer (IL) 162, which is formed on the exposed top surface and sidewall surfaces of fin 106. IL 162 may include an oxide layer, such as a silicon oxide layer, which is formed by a thermal oxidation, chemical oxidation, or deposition process of fin 106. The gate dielectric layer 160 may also include a high dielectric constant dielectric layer 164 above IL 162. The high dielectric constant dielectric layer 164 may be formed of a high dielectric constant dielectric material comprising Si, Hf, Zr, Pb, Sb, La, or the like. For example, the high-dielectric-constant dielectric layer 164 may be formed or composed of hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, combinations thereof, multilayers thereof, or similar materials. The thickness of the high-dielectric-constant dielectric layer 164 may be between about 10 Å and about 40 Å. The dielectric constant (k value) of the high-dielectric-constant dielectric material is greater than 3.9 and may be greater than about 7.0 or higher. The high-dielectric-constant dielectric layer 164 covers and is in contact with each underlying layer IL 162. The high-dielectric-constant dielectric layer 164 is formed as a conformal layer and extends on the sidewalls of the fin 106 and the top surface and sidewalls of the gate spacer 146. According to some embodiments of this disclosure, the high-dielectric-constant dielectric layer 164 is formed using ALD, CVD, or similar methods.

[0053] Referring to Figure 14, a barrier metal layer 166 is formed by deposition in gate trenches 154A and 154B. In the process flow 200 shown in Figure 35, each process is illustrated as process 220. The barrier metal layer 166 is deposited on the top surface and sidewalls of the high-dielectric-constant dielectric layer 164. In one embodiment, the barrier metal layer 166 comprises a metal nitride, such as TaN, to prevent metal elements in subsequently formed features from migrating to the underlying gate dielectric layer 160. The barrier metal layer 166 also functions as an etch stop layer in subsequent etch processes. The barrier metal layer 166 is conductive and has a conformal profile. According to some embodiments of this disclosure, the barrier metal layer 166 is formed using ALD, CVD, or similar methods.

[0054] Referring to Figure 15, a primary metal layer 168 is deposited, which completely fills gate trenches 154A and 154B and covers the top surface of semiconductor structure 100. In the process flow 200 shown in Figure 35, the respective process is illustrated as process 222. The primary metal layer 168 can be deposited by deposition methods such as ALD, CVD, plasma-enhanced CVD (PECVD), PVD, electroplating, or similar deposition methods. The primary metal layer 168 may comprise a homogeneous layer, which is formed entirely of the same material. Alternatively, the primary metal layer 168 may comprise a plurality of sublayers formed of different materials from each other. The primary metal layer 168 has an n-type or p-type working function. Therefore, the primary metal layer 168 serves both as a working functional layer and as an overlay filler metal. According to some embodiments, the primary metal layer 168 is formed of tungsten, aluminum, cobalt, or alloys thereof. In some embodiments, a glue layer (not shown) is conformally deposited over a barrier metal layer 166 prior to the deposition of the primary metal layer 168. The adhesive layer may be a metal-containing layer, which may contain TiN or other suitable materials, and may be formed along the sidewalls and bottom of the gate trenches 154A and 154B using ALD, CVD, PVD, combinations thereof or similar methods.

[0055] Referring to Figure 16, a photoresist layer is deposited and patterned on the semiconductor structure 100 to form a patterned photoresist layer 170 that exposes the first circuit region 120 of the logic circuit. In various embodiments, the photoprocessing for forming the patterned photoresist layer 170 may also include other steps such as soft baking, mask alignment, exposure, post-exposure baking, development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography processes, and / or combinations thereof. After forming the patterned photoresist layer 170, an etching process is performed to remove the main metal layer 168 from the first circuit region 120 for the logic circuit. The respective process is illustrated as process 224 in the process flow 200 shown in Figure 35. During the etching process, a barrier metal layer 166 may be used as an etch stop layer. In some embodiments, the etching process may include a dry etching process, a wet etching process, and / or a combination thereof. In one example, the barrier metal layer 166 comprises TaN, and the etching process is a wet etching process in which the etching solution contains hydrogen peroxide, which spontaneously dissociates in the aqueous solution to form H+ and H2O2 ions. In the aqueous solution, both H2O2 and H2O2 react with the main metal layer 168, but not substantially with TaN. By making the etching solution more acidic, H+ ions promote the dissociation and reaction of H2O2 with the metal elements in the main metal layer 168, thereby increasing the metal etching rate. The etching process releases the gate trench 154A and exposes the barrier metal layer 166 in the first circuit region 120 for logic circuitry. After the etching process, the patterned photoresist layer 170 can be removed by means of, for example, solvents, photoresist strippers, ashing, or other suitable techniques.

[0056] Referring to Figure 17, the working functional layer 172 and the main metal layer 174 above the working functional layer 172 are deposited on the top surface of the semiconductor structure 100. In the process flow 200 shown in Figure 35, each process is described as process 226. In an embodiment of an n-type transistor, the working functional layer 172 may comprise Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaC, TaCN, TaSiN, TaAlC, Mn, Zr, combinations thereof, or the like, and may be formed along the sidewalls and bottom of the gate trench 154A using ALD, CVD, PVD, combinations thereof, or similar methods. In an embodiment of a p-type transistor, the working functional layer 172 may comprise TiN, WN, TaN, Ru, Co, combinations thereof, or the like, and may be formed along the sidewalls and bottom of the gate trench 154A using ALD, CVD, PVD, combinations thereof, or similar methods. The primary metal layer 174 may comprise tungsten, aluminum, cobalt, or alloys thereof, and may be deposited to fill the gate trench 154A by deposition methods such as ALD, CVD, PECVD, PVD, electroplating, or similar methods. The functional layer 172 and the primary metal layer 174 are also deposited on the primary metal layer 168 of the second circuit region 122 for the RF circuit.

[0057] Referring to Figure 18, after forming the functional layer 172 and the main metal layer 174, a planarization process, such as chemical mechanical polishing (CMP) or mechanical polishing, is performed to remove excess portions of the deposited layers. In the process flow 200 shown in Figure 35, each process is described as process 228. The remaining portions of the layers in gate trench 154A form gate stack 112A in the first circuit region 120 of the logic circuit, including gate dielectric layer 160, barrier metal layer 166, functional layer 172, and main metal layer (or metal fill layer) 174. The remaining portions of the layers in gate trench 154B form gate stack 112B in the second circuit region 122 for RF circuitry, including gate dielectric layer 160, barrier metal layer 166, and main metal layer (or metal fill layer) 168. Each of the gate stacks 112A and 112B may contain other sublayers, such as one or more capping layers, adhesive layers, other suitable layers, and combinations thereof, which will not be described here for simplicity.

[0058] According to some embodiments, the main metal layer 168 in the gate stack 112B for RF transistors and the main metal layer 174 in the gate stack 112A for logic transistors are formed of the same material but have different grain sizes. For example, both main metal layers 168 and 174 are homogeneous layers, formed entirely of the same material, such as tungsten (W). The grain size of region 168A in main metal layer 168 is smaller than that of region 174A in main metal layer 174. For example, the average grain size of main metal layer 168 may be less than about 5 nm, while the average grain size of main metal layer 174 may be between about 8 nm and about 500 nm. The ratio of the average grain size of main metal layer 174 to the average grain size of main metal layer 168 is greater than 1.2, or may be greater than about 10. The difference in grain size between main metal layer 168 and main metal layer 174 may be due to different deposition processes. For example, the metal material in the main metal layer 168 can be deposited in an ALD process, while the metal material in the main metal layer 174 can be deposited in a CVD process.

[0059] Referring to Figure 19, an etch-back process is performed to recess gate stacks 112A and 112B, thereby forming trenches between opposing gate spacers 146. The trenches are then filled with a dielectric material to form dielectric regions 176. In the process flow 200 shown in Figure 35, each process is described as process 230. Dielectric regions 176 are formed of dielectric materials such as silicon nitride, porous silicon oxynitride, silicon oxycarbide, or similar materials. Dielectric regions 176 are also planarized so that their top surface is coplanar with the top surface of the ILD layer 152. Regarding the recessed gate stacks 112A and 112B, due to the extra layer—the working functional layer 172—in the gate trench 154A, the width W1 of the main metal layer 174 is smaller than the width W2 of the main metal layer 168, the height H1 is smaller than the height H2 of the main metal layer 168, and the volume V1 is smaller than the volume V2 of the main metal layer 168. In some embodiments, the ratio of W2 / W1 is greater than 1.2, for example, in the range of about 1.2 to about 2; the ratio of H2 / H1 is greater than about 1.1, for example, in the range of about 1.1 to about 1.5; and the volume V2 / V1 is greater than 1.4, for example, in the range of about 1.4 to about 2.

[0060] Referring to Figure 20, a second ILD layer 178, a gate contact plug 180, a source / drain silicon region 182, and a source / drain contact plug 184 are formed. In the process flow 200 shown in Figure 35, each process is described as process 232. The ILD layer 178 may be formed from a dielectric material selected from the same group of candidate materials used to form the ILD layer 152. The formation of the source / drain contact plug 184 includes etching the ILD layers 178 and 152 to expose the underlying portion of the CESL 150, and then etching the exposed portion of the CESL 150 to expose the source / drain region 126 to form a contact opening. In subsequent processes, one or more metals are deposited into the contact openings, and an annealing process is performed on the semiconductor structure 100 to allow the one or more metals to react with the semiconductor material of the exposed portions of the source / drain regions 126, generating silicide features. Unreacted portions of the one or more metals are removed, leaving the silicide features at the bottom of the contact openings, thereby forming the source / drain silicide regions 182. The one or more metals may include titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co), or combinations thereof (e.g., alloys of two or more metals), and may be deposited using CVD, PVD, ALD, or other suitable methods. The source / drain silicide region 182 may comprise titanium silicon (TiSi), nickel silicon (NiSi), tungsten silicon (WSi), nickel platinum silicon (NiPtSi), nickel platinum germanium silicon (NiPtGeSi), nickel germanium silicon (NiGeSi), ytterbium silicon (YbSi), platinum silicon (PtSi), iridium silicon (IrSi), erbium silicon (ErSi), cobalt silicon (CoSi), combinations thereof, or other suitable compounds. In some embodiments, the thickness of the source / drain silicide region 182 ranges from approximately 1 nm to 15 nm. Subsequently, a filler metal material, such as copper, tungsten, aluminum, cobalt, or similar material, is then filled into the contact opening, followed by planarization to remove excess material, thereby forming the source / drain contact plug 184. The formation of the gate contact plug 180 may include etching a second ILD layer 178 and a dielectric region 176 to expose the gate stack 112, and filling the corresponding openings with a metallic material, such as copper, tungsten, aluminum, cobalt, etc., to form the gate contact plug 180. The gate contact plug 180 may also include a diffusion barrier layer, such as titanium nitride. The formation of the gate contact plug 180 and the source / drain contact plug 184 may share some etching and deposition processes (such as forming their respective openings and depositing metallic materials) and planarization processes.

[0061] An exemplary semiconductor device 100 is formed by performing the processes shown in Figures 3 to 20, comprising a logic transistor having a gate stack 112A for logic circuitry in a first circuit region 120 and an RF transistor having a gate stack 112B for RF circuitry in a second circuit region 122. As shown, the gate stacks 112A and 112B may share some common formation processes, such as forming a dummy gate stack, forming source / drain regions, and replacing the dummy gate stack with components when forming the gate stack 112B in circuit regions 120 and 122. Separate etching and deposition processes are performed in the first circuit region 120 to replace the main metal layer 168 with other metal layers (e.g., functional layer 172 and main metal layer 174) that are more suitable for forming the gate stack 112A for logic circuitry applications. Returning to Figure 16, during the etching process, even though the main metal layer 168 in the second circuit region 122 is covered by the patterned photoresist layer 170, the portion below the edge of the patterned photoresist layer 170 is eventually exposed to the etching solution applied at step 224 of the process flow 200 shown in Figure 35. The etching solution first erodes this portion of the main metal layer 168, forming a gap between the edge of the patterned photoresist layer 170 and the underlying barrier metal layer 166, and gradually widens this gap into the gate trench of the second circuit region 122. The boundary of this gap 171 after the etching process is illustrated by dashed lines in Figure 16. Figure 21 further illustrates the structure that may result after the etching process and the removal of the patterned photoresist layer 170. As shown in Figure 21, the gate stack 112B of the RF transistor is damaged due to lateral leakage of the etching solution into the RF region, and the RF performance of the device may have been compromised.

[0062] Figure 22 is a partial layout of a semiconductor structure 100 constructed according to some embodiments. The semiconductor structure 100 has an optimized layout to enhance circuit performance for logic circuitry in a first circuit region 120 and RF circuitry in a second circuit region 122. The central region of the layout is an exemplary second circuit region 122. The peripheral region of the layout is an exemplary first circuit region 120. In the embodiment shown in the figure, the first circuit region 120 surrounds the second circuit region 122. A guard ring region 121 is located between the first circuit region 120 and the second circuit region 122. The guard ring region 121 includes one or more guard rings surrounding the second circuit region 122.

[0063] The first circuit region 120 includes protruding fins 106A and gate stacks 112A for forming logic transistors. In a further embodiment, some rows and / or columns of transistors closest to the second circuit region 122, such as the rows illustrated in region 120A, may be dummy transistors. Dummy transistors are not functional transistors but are constructed around functional block regions. Dummy transistors are provided for other purposes, such as tuning pattern density and / or isolation. Dummy transistors (including dummy gates within dummy transistors) may have a structure similar to that of functional transistors. For example, the dummy gates in a dummy transistor may include the same gate stack 112A as in a functional transistor. Besides dummy transistors, the remaining transistors formed in the columns and rows on the outer circumference of the first circuit region 120, such as the rows illustrated in region 120B, may be functional transistors.

[0064] The second circuit region 122 includes protruding fins 106B and gate stacks 112B for forming RF transistors. In a further embodiment, a series and / or rows of transistors located at the edges of the second circuit region 122, such as the rows illustrated in region 122A, may be dummy RF transistors. The dummy RF transistors are not functional RF transistors but are constructed around functional blocks. The dummy RF transistors are provided for other purposes, such as tuning pattern density and / or isolation. The dummy RF transistors (including dummy gates within the dummy RF transistors) may have a structure similar to that of functional RF transistors. For example, the dummy gates in the dummy RF transistors may include the same gate stacks 112B as in functional RF transistors. Apart from the dummy RF transistors, the remaining transistors formed in the second circuit region 122 may be functional RF transistors.

[0065] Guard ring region 121 includes one or more guard rings. Guard rings are configured and arranged to shield interference, reduce noise, and improve circuit performance. For example, guard rings may be configured to bias the substrate to shield interference. In the described embodiment, guard ring region 121 includes protruding fins 106C and gate stacks 112C and 112D disposed on fins 106C. Fins 106C may have a different width (measured in the Y direction) than fins 106A and 106B. For example, the width of each of the fins 106C may be larger than that of fins 106A and 106B. Furthermore, the width of fins 106C may be non-uniform. In the described embodiment, some fins 106C are wider than others.

[0066] Each of the gate stacks 112C and 112D extends continuously to completely surround (or encircle) the second circuit region 122, forming an edge trench structure. In the embodiment shown in the figures, each of the gate stacks 112C and 112D is oriented parallel to the adjacent edge of the second circuit region 122. The edge trench structure including the gate stack 112C is configured as a first guard ring (or inner guard ring). The edge trench structure including the gate stack 112D is configured as a second guard ring (or outer guard ring). The gate stacks 112C and 112D can be biased to the power supply voltage (e.g., electrically grounded) or kept floating through the gate contact plug. Furthermore, the gate stacks 112C and 112D are disposed on the same set of fins 106C and sandwiching virtual source / drain regions (e.g., epitaxial features) therebetween. The virtual source / drain region sandwiched between gate stacks 112C and 112D is electrically grounded via metal wires 113 connected to their respective source / drain contacts. In the embodiment shown in the figure, metal wires 113 are positioned between gate stacks 112C and 112D and extend continuously to completely surround (or encircle) the second circuit region 122.

[0067] By completely surrounding the second circuit region 122, the trench-shaped guard ring prevents the etching solution from penetrating into the gate stack of the second circuit region 122 at least at process 224 in the process flow 200 shown in FIG. 35, as further illustrated in FIGS. 23-31. It also offers other benefits, such as providing noise shielding for high-frequency operation of the surrounded RF circuitry. FIGS. 23-31 are cross-sectional views along line X'-X' in FIG. 22. For clarity, FIGS. 23-31 have been simplified to better understand the innovative concepts disclosed herein. For example, source / drain regions, silicon features, CESL, ILD layers, and other features may be omitted, while additional features may be added to the semiconductor structure 100, and some features described below may be replaced, modified, or eliminated in other embodiments of the semiconductor structure 100. In some embodiments, the semiconductor structure 100 is substantially similar to the semiconductor structure described for the foregoing with reference to FIGS. 3-20, but with an outer guard ring and an inner guard ring inserted between the logic transistor in the first region 120 and the RF transistor in the second region 122.

[0068] Referring to Figure 23, at the end of process 222 in the process flow 200 shown in Figure 35, the gate dielectric layer 160 (containing IL 162 and a high dielectric constant dielectric layer 164), the barrier metal layer 166 (e.g., TaN), and the main metal layer 168 (e.g., tungsten) are sequentially deposited in the gate trenches of the first circuit region 120, the guard ring region 121, and the second circuit region 122. In other words, the gate stacks 112A-D spanning the first circuit region 120, the guard ring region 121, and the second circuit region 122 initially have the same material composition as the gate stack 112B of the subsequent RF transistor.

[0069] Referring to Figure 24, a patterned photoresist layer 170 forms a first circuit region 120 exposing the logic circuitry. The guard ring region 121 and the second circuit region 122 are covered by the patterned photoresist layer 170. In various embodiments, the photolithography process for forming the patterned photoresist layer 170 may also include other steps such as soft baking, mask alignment, exposure, post-exposure baking, development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography processes, and / or combinations thereof.

[0070] Referring to Figure 25, an etching process is performed to remove the primary metal layer 168 from the first circuit region 120 of the logic circuit. During the etching process, the barrier metal layer 166 may act as an etch stop layer. In one example, the barrier metal layer 166 contains TaN, and the etching process is a wet etching process in which the etching solution contains hydrogen peroxide, which spontaneously dissociates in the aqueous solution to form H+ and HO2+ ions. In the aqueous solution, both HO2+ and H2O2 react with the primary metal layer 168, but substantially do not react with TaN. The etching process releases the gate trenches in the first circuit region 120 and exposes the barrier metal layer 166 in the first circuit region 120 used for the logic circuit. However, lateral etching of the etching solution may occur, potentially exposing a portion of the primary metal layer 168 under the edge of the patterned photoresist layer 170 to the etching solution and causing it to be eroded. A gap 171 appears under the patterned photoresist layer 170 and extends laterally toward the gate stack 112B in the second circuit region 122. The gate stacks 112D and 112C of the outer and inner guard rings act as barriers, slowing the progress of lateral etching. Even if the etching solution leaks laterally into the area under the patterned photoresist layer 170, potentially etching away the main metal layer 168 in the outer and / or inner guard rings, the gate stack 112B in the second circuit region 122 remains intact when the gate trench in the first circuit region 120 is released and the etching process stops (e.g., controlled in timer mode). In the illustrative embodiment shown in FIG. 25, the main metal layer 168 in the gate stack 112D of the outer guard ring is etched, with the gap 171 extending even to the region between the outer and inner guard rings. However, the gate stack 112C in the inner guard ring and the gate stack 112B in the second circuit region 122 remain intact. Some etch solution may accumulate in the release gate trench of the outer guard ring due to lateral leakage and / or etch residue (shown as 190 in Figure 25), as molecules have difficulty escaping through the narrow opening of gap 171. The etch solution and / or etch residue 190 will eventually evaporate into the environment or be cleaned by a cleaning process after the patterned photoresist layer 170 is subsequently removed. Even if the gate stack 112D of the outer guard ring is damaged due to lateral leakage of the etch solution, the gate stack 112D is not a functional gate stack, and the RF performance of the device will not be affected.

[0071] Referring to Figure 26, the functional layer 172 and the main metal layer 174 above it are deposited in the gate trenches of the first circuit region 120 and the outer guard ring, and are deposited on the main metal layer 168 remaining in the inner guard ring and the second circuit region 122. The functional layer 172 can adjust the operating function of the logic transistor. The main metal layer 174 may have the same material composition as the main metal layer 168, such as tungsten, but differ in grain size, as discussed above with reference to Figure 18.

[0072] Referring to Figure 27, after forming the functional layer 172 and the main metal layer 174, a planarization process, such as chemical mechanical polishing (CMP) or mechanical polishing, is performed to remove excess portions of the deposited layers. The remaining portions of the layers in the gate trench form the gate stack 112A in the logic transistor, the gate stack 112D in the outer guard ring, the gate stack 112C in the inner guard ring, and the gate stack 112B in the RF transistor. Gate stacks 112A and 112D each include a gate dielectric layer 160, a barrier metal layer 166, a functional layer 172, and a main metal layer (or metal filler layer) 174. Gate stacks 112C and 112B each include a gate dielectric layer 160, a barrier metal layer 166, and a main metal layer (or metal filler layer) 168. Each of the gate stacks 112A-D may contain other sublayers, such as one or more capping layers, adhesive layers, other suitable layers, and combinations thereof, which will not be described here for the sake of simplicity.

[0073] Referring to Figure 28, an etch-back process is performed to recess the gate stacks 112A-D, forming a dielectric region 176 on the recessed gate stacks 112A-D, followed by the formation of gate contact plugs 180 and source / drain contact plugs 184. In some embodiments, the gate contact plugs 180 on the outer guard ring and the inner guard ring electrically ground the gate stacks 112D and 112C, respectively. Additionally, the gate stacks 112D and 112C on the outer guard ring and the inner guard ring may remain floating. In some embodiments, the source / drain contact plugs 184 falling onto the dummy source / drain region (epithelial feature) sandwiched between the gate stacks 112D and 112C electrically couples the dummy source / drain region to a metal line 113 (Figure 22), thereby providing electrical grounding. Regarding the recessed gate stacks 112D and 112C, in some embodiments, the gate width D3 of gate stack 112D may be equal to the gate width D4 of gate stack 112C. However, due to an additional layer in gate stack 112D—the working functional layer 172—the width W3 of the main metal layer 174 is smaller than the width W4 of the main metal layer 168, the height H3 is smaller than the height H4 of the main metal layer 168, and the volume V3 is smaller than the volume V4 of the main metal layer 168. In some embodiments, the ratio of W4 / W3 is greater than 1.2, for example, in the range of about 1.2 to about 2; the ratio of H4 / H3 is greater than about 1.1, for example, in the range of about 1.1 to about 1.5; and the volume V4 / V3 is greater than 1.4, for example, in the range of about 1.4 to about 2. In some embodiments, the gate width of the guard ring is wider than the gate width of the RF transistor and the logic transistor, and the main metal layers 168 and 174 in different regions have D4 = D3 > D2 > D1, W4 > W3 > W2 > W1, H4 = H2 > H3 = H1, and V4 > V3 > V2 > V1.

[0074] Figure 29 illustrates an alternative embodiment where lateral leakage of the etching solution further removes the primary metal layer 168 from the gate trench of the inner guard ring, for example, due to over-etching with a longer etching time to ensure complete removal of the primary metal layer 168 to form the gate trench in the first circuit region 120. Even if the gate stacks 112D and 112C of the outer guard ring are damaged due to lateral leakage of the etching solution, the gate stack 112B in the RF transistor remains intact. Since the gate stacks 112D and 112C are not functional gate stacks, the RF performance of the device is not affected.

[0075] Referring to Figure 30, the functional layer 172 and the primary metal layer 174 above it are deposited in the gate trench, outer guard ring, and inner guard ring of the first circuit region 120, and remain on the primary metal layer 168 in the second circuit region 122. The functional layer 172 can adjust the operating function of the logic transistor. The primary metal layer 174 may have the same material composition as the primary metal layer 168, such as tungsten, but differ in grain size, as discussed above with reference to Figure 18.

[0076] Referring to Figure 31, after a planarization process to remove excess portions of the deposited layer, an etch-back process is performed to recess the gate stacks 112A-D, forming dielectric regions 176 on the recessed gate stacks 112A-D, followed by the formation of gate contact plugs 180 and source / drain contact plugs 184. The gate stacks 112D and 112C of the outer guard ring contain the same material layers. In some embodiments, the gate width D3 of the gate stack 112D may be equal to the gate width D4 of the gate stack 112C, and the main metal layer 174 has the same dimensions in both the gate stacks 112D and 112C (e.g., width W3=W4, height H3=H4, and volume V3=V4). In some embodiments, the gate width of the guard ring is wider than that of the RF transistor and the logic transistor, and the main metal layers 168 and 174 in different regions have D4=D3>D2>D1, W4=W3>W2>W1, H2>H4=H3=H1, and V4=V3>V2>V1.

[0077] Figure 32 shows another embodiment of the layout of a portion of the constructed semiconductor structure 100. The top view shown is substantially similar to the top view depicted in Figure 22, but with an additional protective ring in the protective ring region 121, comprising a gate stack 112E formed on the protruding fin 106D. This additional protective ring is deposited between the outer protective ring and the first circuit region 120. Unlike the outer and inner protective rings discussed above, this additional protective ring is not continuous but segmented, hence it is also referred to as a segmented protective ring, in comparison to an edge trench-like protective ring. In particular, the gate stack 112E does not extend continuously around the second circuit region 122, but is segmented, extending along its length in the Y direction. The segmented protective ring biases the substrate toward ground, providing additional noise shielding during high-frequency operation. However, the gaps between the segments of the segmented protective ring are not effective in preventing lateral leakage of the etching solution. Therefore, the material composition of the gate stack 112E of the segmented protection ring is substantially similar to that of the gate stack 112A in the first circuit region and possibly to that of the gate stack 112D in the outer protection ring, but is different from that of the gate stack 112B protected in the second circuit region 122.

[0078] Figure 33 shows another alternative embodiment of the layout of a portion of the constructed semiconductor structure 100. The top view shown is substantially similar to the top view depicted in Figure 22, but has an additional edge-groove-like protective ring in the protective ring region 121, including protruding fins 106D and gate stacks 112E and 112F disposed on the fins 106D. Fins 106D may have a different width (measured in the Y direction) than fins 106A and 106B. For example, some fins 106D may have a larger width than any of fins 106A, 106B, and 106C. Furthermore, the width of fins 106D may be non-uniform, with some fins 106D being wider than others.

[0079] Each of the gate stacks 112E and 112F extends continuously to completely surround (or encircle) the second circuit region 122. In the embodiment shown in the figures, each of the gate stacks 112E and 112F is oriented parallel to the adjacent edge of the second circuit region 122. The trench-like structure containing the gate stack 112E is configured as a third guard ring (or a second inner guard ring). The trench-like structure containing the gate stack 112F is configured as a fourth guard ring (or a second outer guard ring). The gate stacks 112E and 112F can be biased towards the power supply voltage (e.g., electrically grounded) or kept floating via gate contact plugs. Furthermore, the gate stacks 112E and 112F are disposed on the same set of fins 106D, sandwiching a dummy source / drain region (e.g., an epitaxial feature) therebetween. The dummy source / drain region sandwiched between the gate stacks 112E and 112F is electrically grounded via a metal wire 123 connected to the source / drain contact plug. In the embodiment shown in the figures, metal line 123 is located between gate stacks 112E and 112F and extends continuously to completely surround (or encircle) the second circuit region 122. In some embodiments, the gate widths of gate stacks 112C and 112D may be equal to each other, while the gate widths of gate stacks 112E and 112F may be equal to each other but larger than the gate widths of gate stacks 112C and 112D. In some examples, the ratio of the gate widths of gate stacks 112E and 112F to the gate widths of gate stacks 112C and 112D may be greater than about 1.5. Furthermore, the gate spacing between gate stacks 112E and 112F may be greater than the gate spacing between gate stacks 112C and 112D, for example, a ratio greater than about 1.5 in some examples. In some embodiments, the linewidth of metal line 123 is greater than the linewidth of metal line 113.

[0080] By having two pairs of edge-groove guard rings—the first pair including dummy gate stacks 112C and 112D, and the second pair including dummy gate stacks 112E and 112F—the second circuit region 122 is better protected from gate damage caused by lateral leakage of the etching solution. In one example, the lateral leakage reaches the second outer guard ring, where the gate stack 112F has the same metal gate composition as the logic transistors in the first circuit region 120, while the gate stacks 112E, 112D, and 112C have the same metal gate composition as the RF transistors in the second circuit region 122. In one example, the lateral leakage reaches the second inner guard ring, where the gate stacks 112F and 112E of the second outer guard ring have the same metal gate composition as the logic transistors in the first circuit region 120, while the gate stacks 112D and 112C have the same metal gate composition as the RF transistors in the second circuit region 122. In one example, lateral leakage reaching the gate stacks 112F and 112E of the first outer protection ring, the gate stack 112D of the second inner protection ring, and the gate stack 112C of the first outer protection ring has the same metal gate composition as the logic transistors in the first circuit region 120, while the gate stack 112C has the same metal gate composition as the RF transistors in the second circuit region 122. In another example, lateral leakage reaching the gate stacks 112F and 112E of the first inner protection ring, the gate stack 112D of the first outer protection ring, and the gate stack 112C of the first inner protection ring has the same metal gate composition as the logic transistors in the first circuit region 120, while the RF transistors in the second circuit region 122 are protected from lateral leakage and have a different metal gate composition than those used in the RF application.

[0081] Figures 34A through 34D illustrate embodiments of this disclosure that can be applied to some exemplary transistors so that these transistors can be used as logic transistors and / or RF transistors. Figure 34A illustrates a cross-sectional view of a dual-gate transistor, wherein two gates are formed on opposite sides of a channel. Figure 34B illustrates a perspective view of a FinFET formed on substrate 102. Figure 34C illustrates a perspective view of a GAA transistor comprising two channel layers, with metal gate stacks enclosing each of the two channel layers. Figure 34D illustrates a GAA transistor comprising a single channel layer. The gate stacks of these transistors can be configured to improve circuit performance using embodiments of this disclosure.

[0082] This disclosure provides various embodiments of IC structures with multiple circuit regions having different functions, such as logic circuits and RF circuits. In the aforementioned embodiments, the RF circuit is completely surrounded by one or more trench-like guard rings, thereby eliminating or reducing process defects caused by lateral leakage of the etching solution during gate replacement processes. Therefore, the entire IC structure exhibits enhanced circuit performance without compromising manufacturing quality.

[0083] In one example embodiment, this disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region, a first transistor including a first gate stack disposed in the first circuit region, a second transistor including a second gate stack disposed in the second circuit region, the first gate stack and the second gate stack having different material compositions, and a guard ring structure disposed between the first circuit region and the second circuit region, the guard ring structure completely surrounding the second circuit region. In some embodiments, the second transistor is a high-frequency transistor, and the first transistor is a logic transistor. In some embodiments, the first circuit region completely surrounds the second circuit region. In some embodiments, the guard ring structure includes at least one continuously extending dummy gate stack completely surrounding the second circuit region. In some embodiments, the guard ring structure includes a first dummy gate stack and a second dummy gate stack, wherein each of the first and second dummy gate stacks continuously extends and completely surrounds the second circuit region. In some embodiments, the first and second dummy gate stacks are disposed on at least the same active region. In some embodiments, the active region has a fin shape protruding from the semiconductor substrate. In some embodiments, the first gate stack and the first dummy gate stack contain the same material composition different from the second gate stack and the second dummy gate stack. In some embodiments, the first gate stack, the first virtual gate stack, and the second virtual gate stack contain the same material composition, different from that of the second gate stack. In some embodiments, the first gate spacing of the first gate stack is smaller than the reference spacing, while the second gate spacing of the second gate stack is larger than the reference spacing.

[0084] In another example, this disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a logic circuit region and a radio frequency (RF) circuit region, a first transistor including a first gate stack disposed in the logic circuit region, a second transistor including a second gate stack disposed in the RF circuit region, and a guard ring structure disposed between the logic circuit region and the RF circuit region. The guard ring structure includes an inner guard ring completely surrounding the RF circuit region and an outer guard ring completely surrounding the inner guard ring and the RF circuit region. In some embodiments, the guard ring structure further includes an epitaxial feature disposed between the inner and outer guard rings, and a metal line electrically coupled to the epitaxial feature, the metal line completely surrounding the RF circuit region. In some embodiments, the outer guard ring includes a first dummy gate stack, and the inner guard ring includes a second dummy gate stack, wherein the first and second dummy gate stacks are disposed on the same active region. In some embodiments, the outer guard ring includes a first dummy gate stack, and the inner guard ring includes a second dummy gate stack, the first dummy gate stack including the same first material composition as the first gate stack, and the second dummy gate stack including the same second material composition as the second gate stack. In some embodiments, the outer guard ring includes a first virtual gate stack, and the inner guard ring includes a second virtual gate stack. The first and second virtual gate stacks contain the same material composition as the first gate stack but different from the second gate stack. In some embodiments, the inner guard ring includes a first metal filler layer, and the outer guard ring includes a second metal filler layer, wherein the width of the first metal filler layer is greater than that of the second metal filler layer. In some embodiments, the guard ring structure is a first guard ring structure, and the semiconductor structure further includes a second guard ring structure disposed between the logic circuit region and the first guard ring structure.

[0085] In another example, this disclosure provides a method for manufacturing a semiconductor device. The method includes forming a first gate stack in a first circuit region of a substrate, forming a second gate stack in a second circuit region of the substrate, and forming a third gate stack in a guard ring region between the first and second circuit regions. The first, second, and third gate stacks each contain the same material composition, and the third gate stack completely surrounds the second circuit region in a top view. A patterned mask layer is deposited covering the guard ring region and the second circuit region. An etching process is performed to remove a first metal filler layer in the first gate stack, and the etching process also partially etches the third gate stack to form a gap. A second metal filler layer is deposited in the gap between the second and third gate stacks, and the semiconductor device is planarized to expose the first metal filler layer in the second gate stack. In some embodiments, the first and second metal filler layers contain the same metal but have different grain sizes. In some embodiments, the first circuit region is a logic circuit region, and the second circuit region is a radio frequency (RF) circuit region.

[0086] The foregoing has outlined the features of several embodiments. Those skilled in the art will recognize that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from its spirit and scope.

[0087] 100: Semiconductor Structure 102: Semiconductor substrate / substrate 104: Isolation Characteristics / Isolation Area / STI Area 104A: Top surface 105: Semiconductor strip 106: Active area / fin active area / first active area / second active area / protruding fin / fin 106A: Top surface / protruding fins / fins 106B: Prominent fins / fin plates 106C: Prominent fins / fin plates 106D: Prominent fins / fin plates 108: Negatively Doped Wells / N Wells / Well Regions 110: Positively Doped Well / P Well 112A: Gate Stacking / Gate 112B: Gate Stacking / Gate 112C: Gate Stack 112D: Gate Stack 112E: Gate Stacking / Virtual Gate Stacking 112F: Gate Stacking / Virtual Gate Stacking 113: Metal wire 116: Oxide Pad 118: Hard mask layer 120: First Circuit Region / First Region / Circuit Region 120A: Area 120B: Area 121: Protective ring area 122: Second Circuit Region / Second Region / Circuit Region 123: Metal wire 126: Source / Drain Regions / Epilithographic Characteristics 128: Gap 132: p-type FET / pFET 133:n-type FET / nFET 134:pFET 135:nFET 138: Virtual Gate Stacking 140: Virtual gate dielectric 142: Virtual gate electrode 144: Hard mask layer 146: Gate spacer 148: concave part 150: Contact Etching Stop Layer / CESL 152: Interlayer dielectric layer / ILD layer 154: Gate trench 154A: Gate Trench 154B: Gate trench 160: Gate dielectric layer 162: Interface Layer / IL 164: High dielectric constant dielectric layer 166: Barrier Metal Layer 168: Main metal layer 168A: Area 170: Patterned photoresist layer 171: Gap 172: Working Functional Layer 174: Main metal layer 174A: Area 176: Dielectric Region 178: Second ILD layer / ILD layer 180: Gate contact plug 182: Source / Drain Silicate Region 184: Source / Drain Contact Plug 190: Residue 200: Manufacturing Process 202: Process 204: Process 206: Manufacturing Process 208: Process 210: Manufacturing Process 212: Manufacturing Process 214: Manufacturing Process 216: Manufacturing Process 218: Manufacturing Process 220: Process 222: Manufacturing Process 224: Manufacturing Process 226: Manufacturing Process 228: Manufacturing Process 230: Process 232: Manufacturing Process D1: First width D2: Second width D3: Gate width D4: Gate Width H1: Height H2: Height H3: Height H4: Height P1: First spacing P2: Second spacing W1: Width W2: Width W3: Width W4: Width

Claims

1. A semiconductor structure comprising: a semiconductor substrate having a first circuit region and a second circuit region; a first transistor including a first gate stack disposed in the first circuit region; a second transistor including a second gate stack disposed in the second circuit region, wherein the first gate stack and the second gate stack have different material compositions; a guard ring structure disposed between the first circuit region and the second circuit region, wherein the guard ring structure completely surrounds the second circuit region; and a third gate stack disposed within the guard ring structure and completely surrounds the second circuit region.

2. The semiconductor structure as claimed in claim 1, wherein the second transistor is a high-frequency transistor and the first transistor is a logic transistor.

3. The semiconductor structure as claimed in claim 1, wherein the first circuit region completely surrounds the second circuit region.

4. The semiconductor structure as claimed in claim 1, wherein the guard ring structure includes at least one virtual gate stack that extends continuously and completely surrounds the second circuit region.

5. A semiconductor structure comprising: a semiconductor substrate having a logic circuit region and a radio frequency (RF) circuit region; a first transistor including a first gate stack disposed in the logic circuit region; a second transistor including a second gate stack disposed in the RF circuit region; a guard ring structure disposed between the logic circuit region and the RF circuit region, wherein the guard ring structure includes an inner guard ring completely surrounding the RF circuit region and an outer guard ring completely surrounding the inner guard ring and the RF circuit region; and a third gate stack disposed within the guard ring structure, completely surrounding the second circuit region.

6. The semiconductor structure of claim 5, wherein the guard ring structure further includes an epitaxial feature disposed between the inner guard ring and the outer guard ring; and a metal line electrically coupled to the epitaxial feature, wherein the metal line completely surrounds the RF circuit region.

7. The semiconductor structure as claimed in claim 5, wherein the guard ring structure is a first guard ring structure, and the semiconductor structure further includes: a second guard ring structure disposed between the logic circuit region and the first guard ring structure.

8. A method of manufacturing a semiconductor device, comprising: forming a first gate stack in a first circuit region of a substrate; forming a second gate stack in a second circuit region of the substrate; forming a third gate stack in a guard ring region between the first circuit region and the second circuit region, wherein the first gate stack, the second gate stack, and the third gate stack each comprise the same material composition, and wherein the third gate stack completely surrounds the second circuit region in a top view; depositing a patterned mask layer covering the guard ring region and the second circuit region; performing an etching process to remove a first metal filler layer in the first gate stack, wherein the etching process also partially etches the third gate stack to form a gap; depositing a second metal filler layer in the gap between the second gate stack and the third gate stack; and planarizing the semiconductor device to expose the first metal filler layer in the second gate stack.

9. The method of claim 8, wherein the first metal filler layer and the second metal filler layer comprise the same metal but have different grain sizes.

10. The method of claim 8, wherein the first circuit region is a logic circuit region and the second circuit region is a radio frequency (RF) circuit region.

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